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The fout
nisstles n0aybe grouped together and used as a 5rh player, These
objects are posltloned horlzontally by 8 horizonral posltlon regtslers
([PoS (X)). These reglsrers nay be reloaded at any rlne by rhe proces-
sor, allowlng an object to be repllcated nany tiioes across a horizontal
TV 1ine.
Each byte tn rhe player graphics area represenls elght ptxels whtch
are to be displayed on the correspondtng llne(s) of rhe TV screen. A
I indlcates that the player's color-lun ts to be dtsplayed in that ptxel.
The graphics nay be anyrhtng, not Just rectangles like the ones in ftgure
II.3. The player graphlcs may f111 the enttre hetght of rhe screen or
they may be only a couple of lines high if the rest of the dlsplay dara ts
al1 0's. Each byte 1n rhe rolssile dlsplay also represenrs etgi.rt plxels,
trro pixels for each missile. Each ptxel nay be 1, 2, or 4 color clocks,
and is deternined by the SIZE registers.
(hex)
PMBASE*100
A.DDRESS OFFSET
Tvo-l1ne One-line
resolutlon resolutlon
(hex) (hex)
P3
t l horlzontal positlon
l l regasrers.
I
+400 +800
E a c h s e c t l o n o f m e m o r yn a p s d l r e c t l y
Player-Mtssile onlo total height of TV screen.
Ver!1ca1 screen Object vertical posltion is deternined
only by lts Iocatlon In lts section
of deDory. one byre of oenory equals
I or 2 television lines vertlcally,
Figure II.2 P L A Y E R - M I S S I L E D M A
II.6
Unl1ke players and Elssiles, there are oo horlzontal posltlon regtsrers
for playfleld. Each player can only have one byte of display per llne.
Playfteld, on lhe othet hand, nay requlre up to 48 bytes per line because
1t can fll1 the entire wldth of the screen.
Each lnstructlon deftnes the type (alpha character or nemory map) and
the resolutlon (s1ze of blts on screen) and the locatlon of data ln nerory
to be dlsplayed for a group (I to 16) of l1nes. Each group of lines ts
ca11ed a dlsplay b1ock.
TITE DISPI-AY I-IST CANNOTCROSSA lK BYTE MEMORYBOIINDARYUNLESS
A JUMP INSTRUCTION IS USED.
DI,ISTI,
tr.7
Dlsplav Inslructlon Fornat: Each lnstruction conslsts of either an
opcode only, or of an opcode followed by tiro (2) bytes of operadd.
-.t
l6'..d.-l \
l o p e r a n d| ) - - - - T r l p l e EyLe DIspIdy Instructlon
-_-t
lOperand I.,
Blank
( t-byte) 6lD5lD4
(3-bytes ) D 7 l D 6 lX l X l 0 l 0 l 0
D7 I = d t s p l a y . I . L s cl n s c r u c t l o n i n t e r r u p t
D6 0 = junp (creates one blank ltne on dlsplay)
"_i' _:t.I end of nexl vertlcal blank
D5-D4 X = don't care
D3_D0 I = junp
Dlsplay
(1 or 3 bytes) D 2 I D lI D O
II.8
.rr x
F H
ts.o6<raoatsl
r & t s ] t 4l & h t 4 I ' r E t s t r h E r E l
F @ 6 < l q ( J A l n
F c o 6 < f q { J A [ r ]
r @ 6 < 1 4 ( ) a F r
N.o6<FqL)crrIr
r o 6 < i 0 < J A p l ;
Fco6<rcrJoFt
( c o 6 < F ( J A d
N c o 6 < F q ( j , a
Fco6<laL)FIIr
F@6<rC(JAtst
ts@6<lqc)A14
F@6<rO(,)OEl
tsco6<roooFl
t s @ 6 < l a O A F . l
6 t s @ o < F O O t s l
t t l
--! | |
-----1 I I
I
,
Btt 7 of a dtsplay 1lst tnstructlon can be set to create a dlsplay
list tnterrupt 1f btt 7 of NMIEN 1s set. The dlsplay 11s! lnternrpt coile
can change the colors or graphics durtng the nlddle of the TV dlsptay.
The lype of lnterrlpt ls derernlned by checklng NMIST. NMIRES clears
NMIST, The current 0S will vecror through VDSLST(Itex 200 and 2Ol) to
lhe user's dlsplay 1lst lnterrupt rourine. See the OS nanual for proarau-
.olng detatls.
A single byEe lnstructlon does not reload thts counter. Thls lnp11es
a contimratlon In rremory of data to be dlsplayed frorn that displayed by
the previous instructlon. Stnce thls counter really conslsts of 4 btts of
reglster and 12 of actual counter, a conttnuous menory block cannot cross
4K bvte rnenorv boulldarles. unless the counter ls reposltloned wlth a 3
byte Load Meinory Scan Counter instrucllon.
t t t l
1 1 0 2
t t t l t t t t l
15l 14l 13l r2 3 ' 2 t 1
Flxed (4 btts) Counter ( l2 bits)
1 r .l 0
Menory Scan Counter
Addresses each byte
Mernory
Shlft reglster data 1s dlsplayed for four Tv scan 11nes ln thls exarnple.
In IR modes 8,A,D, and E, two btts are used to speclfy the color
of each ptxel, This al1ows four dlfferent colors ro be dlsplayed.
l{olrever, only four plxels can be packed llrto each byte, lnstead of elght
aB in the prevlous Ecdes. The bi! asslgnnents are shoqrnbelor.
SHIFT RECISTER 7 6 t 5 4 1 3 2 t t 0 | 7 6 t 5 4 2 t t 0
2 blts foro
one plxel
II. I1
l4eoorv }lap Dlsplay ltlodes
ro | 4
I
s l A l 4 l 8 0 101 l?30
l t l lr0 lPrl
I 160 0 BAK
I I ?r0
00 BAK
2 I 0l PTO
I r0 ?r1
I 160 0l
I 10
320 40
I Prl
t t t t l IGIIM)
rt. t2
Character Dlsplav Instructlonst The flrst step 1n ushg the character
map dode 1s to cxeate a character set ln neEory (or the bu1lt-tn OS
character set at hex E000 nay be used). The character set contalns elgh!
bytes of !g!g for the graphlcs for each character. The neantng of the
data depends on the hode. The charecter set can contaln 64 or 128 characters,
also depending on the oode. The USB (l,losr Slgntftcant !yte) of rhe
address of the character set ls stored ln CHBASE(or the OS Shadon CHBAS).
Only the most slgntftcant s1x or seven blts of CHBASare used (see CIIBASE
descrlptlon ln sectlo[ III). The other one or two blts and the LSB of the
addless are assuued to be zero, so lhe character set fitst start aE an
acceptable page boundary.
Tte dext step ls to set up the dtsplay 11st for the destred node.
Then the actual dtsplay 1s set up. Thls constsrs of a strlflg of chatacter
lgggg or codes. Each nane takes one byte. The last 6 or 7 bits of the
nene selects a character. For a 64 charactet set, the naEe would range
froE 0 through 63 (decloal). For a 128 characrer ser, rhe range \rould be
0 through 127 (declnal). The upper one or rwo blts of rhe nane byle are
used to speclfy the color or orher speclal tnfornatlon, dependtng on the
Character nanes (codes) are fetched by the neroory scan counter, and
are placed ln a shtf! reglster. On any glven ltne of dlsplay the shifr
reglster rotates, changing only the nane portlon of the character address,
as shol'n belon.
After a full 1lne of character data has been dlsplayed the line
counter v111 lncrenent. The next l1ne agaln addresses all characrers by
na.oe for lhat ftne rnrmber.
The 40 character per ltne aodes use the slx most slgnlficant blts
of CEBASE,forclng the character set to start on a lK byte rnemory boundary.
The aet rrust have 128 charactels of 8 bytes each. Thls gives a total of
1024 bytes for the set.
f 4 l I28
II.I3
Character Dlsplay Internal
codes for
(20 Characrer per llne mode exarnple)
Codes (naines)
Stored ln
Shlft Register
shlft
Resls!er
Llne
Char:acter Set
1n llemory
Addresses data in
r1.14
There are slx charcter inap modes, IR rnodes 2 through 7. Modes 2,6
and 7 are supported by the OS and BASIC (GRAPHICS0,f and 2).
In IR dodes 6 and 7, the upper two bits of each character Iraoe selec!
one of four playfleld colors, For each 3e!g bit that contains a one, tfre
selected playfleld color is dlsplayed. For each zero data btr, the
background color ts dtsplayed. The four characler colors plus the background
color glves a total of flve dlfferent colors. the loode 6 characters are
elght lines htgh and the dode 7 characters are slxteen lines htgh (each
data byte ls dlsplayed for two ltnes).
The l/2 clock lleDory nap node (1R code llll) and lhe l/2 clock chalacter
node (IR codes 0011 and 0010) are both playfleld type 2 coLltsions and w111
be slored in btl 2 of the playfietd colltsion registers.
T1.15
IR l,lode 3-Upper and l,ower Case
Upper Case
Data
Act\ra1
Dlsplay
E
II.I6
Chalacter Map Displav Modes
I os I I l c h a r s . l s c a nl c o l o r l D a t a l c o l o r I B i t I
I and lrnst.loolors I per lllneslclockslBtrs lselect lvalueslcolor
l B A s r c l R e lsp. e r Ista. lper lper lper lattsrnl 1Il lRec.
lModeslttEx I Mode lLine lchar.l?txel lPlxell Naroe lDara lselect
r r r r t t t -
t l l
o t 2 I4 4 0 l 8 l : l l | o I PF2
l r l P r l
0
I I PFT
lB{t 7 01 ?FO
l ' o l0 PTI
I 1I PF2
I
lBlt 7 11 PF3
00 BAK
lBtt 7 01 PFO
l = 0 l0 PFI
I ll PF2
I
lBit 7 II PF3
0 BAK
00 I PFO
OI I PT'I
IO I PF2
! PF3
o BAK
00 Pr'0
0I ?FI
10 PE2
| | | | | | | 1l I I L Pr'3
rr.17
Vertlcal and llorlzontal Flne Scrolllna: ?layfleld objects are dlfflcult
to Eove srnoothly. Me.oory nap playfield can be rnoved by rewrttlog secrlons
of nenory. llowever, thls 1s extreEely tlne-consunlng if large secrlons
of the screen rfils! be noved snoothly. Character playfleld oblects can be
6oved easlly ln a jerky fashlon by chaoglng the nenory scan counter.
Ilorever, thls results 1n a large posltlon junp fro.n one character posttion
to another, not a smooth Dotlon. For thls teason hardnare reglsters
(VSCRoLand HSCROI,)and counters are provtded ro a1low snooth horlzonlal
or vertlcal notlon, up to one character wldth horlzonrally and up to one
character helgh! vertlcally. After this ouch snooth xnotion has been
done by lrrcreaslng the value in these reglsters, nenory 1s reErltten or
the nenory scan counter ts nodlfled and sDooth .0otlon 1s resuned for
another characrer distance,
II. T8
o
2
I 2 T1 I 3
t: T 5
7
'7
l i 5
7
J I
2
5 7 I z J
1 l z 3
-l 2 5 5
I z 3 5
I
I z 5 5 7
2 l 5 7
2 T
5 I
5 7 I 2
5 I 2 J
F
7 I
2 3 4
-t z 2 3 5
I
I fz 3 5
- 2 I 1 3 7
II.19
0S Mode 0 Dtsplav Ltst (40 chars x 24 1lnes)
7C20 70'\
7 0 1 24 blatrk l1nes
70)
4 2 ) reload meroory acan counter r.Ith 7C40,
4 0 I IR roode 2
7C)
i)
; l
t
' . ( 23 nore IR mode 2 tnstructions
2 l
i -))
4l Junp back to 7C20 and
20 1 walt for end of vertlcal b1ank.
1C)
7C40
l
)
960 bytes of dtsplay
(character naoes)
data
The ANTIC chlp steaLs cycles fron the 6502 tr order to do memory
xefresh and fetch graphtcs data ehen needed. The general rule to r:emenber
ls that each byte fetched fron nernory re$lres one Dachine cyc1e. If a
dlsplay Ilst BeEory nap inslruction extends over several llnes then the data
ls only fetched on the flrst 1lne. MeEory refresh takes 9 cycles out of
every l1ne, unless pre-enpted by a htgh-resolutlon graphlcs mode. Menory
refresh conllnuea durtng vertlcal b1ank.
l,rsstle Dl4A takes one cycle per l1ne ln the one-1lne resolutlon Bode
and one cycle every'other 11ne ln the tlro 1lne resolution node. l,Ilsslle
DMA can be enabled rlthou! dolng playex DMA. l{owever, lf player DMA ts
enabled lhen olsslle DMAn111 also be done (see Dl4AcTL, GMCTL blls).
Player DMA iequlres 4 cycles every one or tlro llnes, dependlng on the
resolution used.
II.20
Each fetch of a dtsplay ltst byte takes one cycle, so three cycles
are required for a three byte tnstructlon.
The menory refresh ls done fast enough !o nake up for the lost cycLes
tn the hlgh resolutlon rnodes. Once rnenory refresh slarts or a 1lne, lt
occurs every four cyclea unless pre-enpted by Dl4A,
A11 lntelrupts reach the 6502 near rhe end of horizontal btank.
Wlth standard o! narrow screen lrldths, refresh DMA starts after the end of
horlzontal b1ank.
II.2I
Itortzontal Blank DUA Tlntne
When DMA ts enabled, cycles are slolen at the tiEes shown belol'.
End of
Lprevrous+l Horlzontal BIank_____J
ll,lne | |
20 nachtne cycles (40 color clocks)
-_
.r - v^ tr e r-r e s n
cycres.
char, and graphlcs
I,ISYNC dara DMA (depends on
orr.hl. m-,{ c )
Interrupt
Address DMA (3-byte dlsplay llst
lnstrucrion)
Player
Dlsplay 1ls t lnstruction fetch DMA
Mlsslle Dl,{A
Thus tbe total DMA per frane ls 10838 nachine cycles. one fraroe
1s 262 llr\8 with 114 machlne cycles per ltne for a total of 29868 nachtne
cycles per fraDe. Thus 362 of each frarne is required for DMA tn 0S graphlcs
node 0.
NTSCvs. ?Al, Svstens: There axe tr^roverslons of the ATARI 800: the NTSC
(Untted States T,V. slandard) and PAI- (one of the European T.V. standards).
The PAL systeu has been destgned so that mosl programs wlll lun wlthout
belng modlfled. Ilowever, sone dlfferences nay be notlceable. There 1s a
hardtrare reglscer (PAL) vhich a progran can read to deternlne which type of
system lt Is runnins on and adjult;ccordlngly.
The PAL T.V. has a slo\rer frame rate (50 Hz. instead of 60 t{2.) so
gaues lflll be slot'er irnless an adlustneflt is oade. pAL has roore T.V.
..__ 1lnes per frax0e (312 lnstead of 262r. T\e Arart 800 harilr,rare cordpensates
-
fot thts by adding extra 11nes at the beglnnlng of vertlcal blank. Display
llsts do not have to be altered. llor,rever, thelr actual vertlcal heisht \1111
be shorter. PAL ATARI 800 colors are simtlar to NTSCbecause of a hardware
nodlflcetlon.
B. POIGY
Audlol Ttere are 4 seni-tndependent audlo channels, each lrith its o\rn
frequency, nolse, arld volune control. Each has an 8 b1t "dlvtde by Ni,
frequency dlvider, controlled by an 8 blt regtster (AUDFX). (See andlo-serlal
port block dlagran.) Each channel also has an 8 btt conrrol regtster (AUDCX)
\rhlch selects the tlolse (poly counler) conrent, and the volune.
Poly Nolse Cou[ters: There ale 3 polynoEial counters (17 b1t, 5 btt
and 4 blt) used !o generate random nolse. The 17 btt poly counter can be
reduced to 9 bils (AUDCTLblr 7), These counlers are ;11 clocked by 1.79
MEZ. Thel! outputs, however, can be sampled tndependently by the four
audlo chamels at a rate detelnlned by each channel,s frequency dlvlder.
Thus eech channel appears ro contatn separate poly counters (3 types)
clocked at lts olrn frequency. Thls poly counter noise saopllng is controlled
by blts 5,6 and 7 of each A1IDCXregtster. Because the poly counters are
senpled by the 'rdlvtde by N[ frequeocy dtvldet, lhe output obvlously cannot
change faster than the saopllng !ate. IIr these nodes (poly noise outputted)
the dlvlders are therefore acting asirlow pass,'filrer clocks, allo\rlng only
the low freqrency noise to pass.
rr.23
Audio Nolse tr1lters:
trreqrelrcy
Notse
Frequency
voL
chennel ,) fctaonet t
- b y N o' "
lL-
I
v
f!equency
(or3&
-bvN
,J
channel ;\
Freqtrency
Clock
Elah Pass Fllters: The htgh pass filter conststs of a "D'r fllp flop
attd an elcluslve-OR Gate. Ihe noise control clrcult outpu! ls sanpled by
thls fltp flop dt a rate set by the "Aigh Pass" c1ock. The input and output
of the lllp Flop pass through the excluslve-oR Gate. If the fllp flop lnput
ls changing mrch faster than the clock rate, the stgnal !1111 pas8 easlly
through the excluslve-OR Gate. l{owever, lf lt is Lower tha[ the clock ra!e,
the f11p flop outpul w111 tend to foUow the loput and the two excluslve-oR
Gate lnputs lll1l nostly be tdenttcal (ll or 00) gtvtng very 11!t1e drtput.
Thls glves the effect of a crude hlgh pass fllter, passhg nolse whose
olnftolid frequency 1s set by the htgh pas8 clock rate. Only channels
I and 2 have such a htgh pass ftlter, The hlgh pass clock fo! chatlnel I
cones fro.n the chanfle] 3 dlvlder. The hlgh pass clock for channel 2 cones
froo the channel 4 dlvider. Thls filter 1s lncluded ooly if bit I or 2 of
AIIDCTL ls true.
The ardlo output of any chennel can be conpletely turned off by wrltlng
zero to the volude control blts of AUDCX. A11 ones slves rnaxfid]n volur0e.
c. SERIA]- PORT
r1.25
Output data ts nornally transnitted as loglc leveLs (t4v=lrue ov=Fatse).
Data can also be transmirred as two lone lnforDatlon. Thls rdode ls selected
by bit 3 of SKCTI-. In rhls node andlo chanoel I 1s transroitled 1n place of
loglc true, and audlo channel 2 1r place of togic zero. channel 2 mlst be
the lower tone of the tone Pair.
The processor can force the data outpu! ltre to zero (or to audlo
channel 2, lf 1n two rone node) by settlng btt 7 of sKcTL. Thls 1s requlred
lo force a break (I0 zeros) code tlansolsslon.
Serial Output Clock: The serial output data always changes when the
serlal output clock goes true. Tte clock then returns to zero 1n the cente!
of the output dara blr tlne.
The baud (bil) rale of the data and clock i3 deternined by audlo
channel 4 audio channel 2, or by the lnput cLock' dependtng on the serlal
dode selected by btts 4, 5, and 6 of SKCTL. (see charl at end of thls
Direct Serlal Input: The serial data lnput line can be read directly
by the rnlcroprocessor 1f deslred, ignoring lhe shlft reglster, by readtng
b1I 4 of SKSTAT.
Note that two lone output (bit 3 of SKCTL) Eay be used 1n any
. of these
nodes except for the bortoE pair. Thts is because channel 2 is
cne output lransntt rate and 1s therefore nor available for
one
Note that the output clock rate is tdentlcal !o lhe outpur dara rare.
Mode Control
Force Break
p 7l p 6l p sL D 4
l D 3l D 2l D rI D O S(CTL REGISTER
lTrars. R a t e S e t by Chan. 4
1 4 l4 lnpu t lRecelve Rate by External
C1ock.
11,27
D. INTERRUPTSYSTEU
In this systern NMI interrupls are used for video dlsplay and reset.
IRQ lnterrupts are used for serlal porl com'rnlcatlon, peripheral devlces,
tlners, and keyboard inputs.
Slnce any of these lnterrupls rtrlIl cause the processor lo Jurnp to lhe
same NMI address, lhe syslen also has NMI status blts rrtich nay be exantned
by the processor to deterrnlne whlch source caused the NMI lnterrupt, Blts
5, 6, and 7 of NMIST serve this functlon (see NI1IST register descrtptlon).
These status blts are set by the correspondlng lnterrupt funcllon (even tf
the loterrupt 1s Easked fron the processor by NMIEN). The status bits toay
be reset logether by wriling to the address NMIRES.
Tno of the lntelnrpt enabLe blts (blts 6 and 7 of NMIEN) are cleared
autornatlcally durlng sysren po!/er turr oo and therefore these NMI internrpts
aie inilially dlsabled (nasked), preventing any pover turn on servlce routlne
fron being lnte.rupted before proper lnltiallzatlorl of reglsters and polnlers.*
They can then be enabled by the processor nheneve! deslred, by wrltlng lnro
blts 6 and 7 of NMIEN. Except for the reset button lnterrupt, they can also
be dlsabled by the processor by writing a zero lnlo bits 6 or 7 or NMIEN.
The reset button cannot be dlsabledj allowing an unstoppable escape from any
posslble "hangup" conditlon.
These NMI lnterrupt functlons are each separaled ln tlne (to prevent
ovetlaps) and converted to pulses by the systeo hardware, in order to supply
N M Tt r a n s l r l o n s r e q u i r e d b y t h e n t c r o p r o c e s s o r I o g t c ,
r1.28
_ -
IRQ Tnterrupts: IRQ lnterrupts are a1l "naskabte,' together by one blt
of rhe sratus teglster on the mictoprocessor. This blt is se! ro the
dtsable condltton autonatlcally by power turn on !o prevent tnlerrupt of
power Eurn on service rortines.*r. In addltlon to thts processor IRQ mask
bit, there are separate systenr IRQ lnrerrupt enable blts for each IRQ
lnterrupr functton (blts 0 thrll 7 of IRQEN). These btts are not tnltlalized
by porrer turn on, and rorsr be inttlalized by rhe progran befoie-enabling the
processot IRQ. The I rypes of tRQ tnterrupts are:
These last tvo interruprs g!9 auronatically dtsabled by powet Eurn on,
.
and thelr starus blts are reset by readtng fron porr e reglster and port B
register. (See PORTA,PACTL, P0RTB, and PBCTLRegister descrlptions,)
II.29
INTERRUPT SI]MMARY
STATUS
NAME TUNCTIONS ENAB]-E STATUS RESEl
I
I ulsPray NMIST Address
NMI llnstructlon (Bits 6 rhru 7) (Blrs 5 thru 7) NMIRES
INTERRUPTS
IJ9!9: g]3gL NorEally Zeio NornaUy Zero (Resets all NMI
lReset Button (Dtsabled) | (no lnlerruot) lstatus toeether)
E. CONTRO1LERS
T h e c o n t r o t L e r p o r t s a r e r e a d L h r o u g h t h e P O R T Aa r d P O R T Br e g i s e r s
and the PoT a{d mIG regtsters. The OS reads these registers doring
vertlcal blank and slores lnto its own RAM locatlons. These are STIC(,
PADD1othrough PADDLT, PTRIG'S and STRIG'S. The OS sets up PORTAAND
PoRTBfor inpur. Thts is done by settlng PACTI-or PORTB(Port Control)
blr 2 ro a 0 (to seleci the dlrectlon control register), then lJrlrlng all
0's to the destred port. PACTL (PBCTL) b1r 21s then changed back to
a I, allo$.'1ng the progrard to read fron the porl. The ports can aLso be
set up for outpu! by \rrirlng 1's instead of 0's whtle the direcrion control
mode is selected.
.I9J9!f9E9: The joysttcks have four s\rltches, one each for righl (R),
left (L), back (B) and foruard (F).
II.30
The IRIG reglsters are trorroally read directLy, bul they can be used
ln a latcheil oode. wrltlng a zero to btt 2 of GItAcTl- dlsables the latches
and sets them to 1. Wrltlng a I to bit 2 enables the latches' If a joy_
stlck trlgger button ls pushed al any ttne Ithlle bit 2 of GMCTL is I
the latch value r'l1L change to zero and stay that qay. A Progran can
use th13 to deterrdne whether the joystlck trlgge! buttons have ever been
pressed durlng a certain perlod of tiEe.
II.31
Llahr PerI: A llght pen ts a device rhat can detect the electron beaD
as lt sweeps across the TV screen. It 1s irsed to polnt dlrectly at an irnage
on the TV display. Appltcatlons hclude selecting memr ltens and drawlng
l1nes. Tte ATARI 400/800 hardware was deslgned so that a light pen can be
pfugged lnto any of the joystlck controller porte (see ena if sectron
III).
m:" any one of the joystick rrlgger lines (pln 6) rs pul1ed 1or, the
.---
ANTIC chlp takes rhe current VCOI]NTvalue and st;res tt in PENV. The
horlzofltal color clock value (0-227 declnal) is storect 1n pENt{.
The teast
slgnificant blt ls inaccurate and should be lgnored. Slnce there are a
nuober of delays lnvotved 1n dtsplaytng the alata and changing the ltghr
per! register, eech systeE mrst be cal brated. Softr"rare irhtch uses the
l1ght pen should contaln a user-tBteractlve caltblatlon routlne. For
exanple, the user could pol[t the Ught pen at a crosshalt tn the center
of-the screen and the progran could coruFnrrethe requtreil horlzontal
offset.
PENHwt1l wrap around fton 227 ro O near the rlght halld edge of a
statdard
width dlsplay because of lhe delay. fhe pen rd11 not l'ork lf 1t 1s polnted
at a black area of the screen, slnce the elecrron besn is turneal
oif. It ls
a good ldea to read t\ro (or nore) values anal average then, slnce
the user
rsll1 probably not hold the pen perfecrty sready.
TI.32
I1I. HAR)WAREREOISTERS
Thls sectlon 1lsts the hardware registers and operatlng Systen (OS)
shadow reglsters.
A. PAL (D014)
Not I D3 | D2 | DI lNor
U s e d l l l l u s e d
D3 D2 D]
\-- B. INTERRIJPTCONTROL
0 = dlsabled (dasked)
I - enab led
I Nor
Used
SYSTEMRESETBulton lnterrupt
1r1.1
NUIST (Non Maskable Interrupr Status)(D40F)! Thls address read the NMI
Status Reglsrer (Read by OS NMI code).
0 - no intelrupt
I = lnterrupt
I Not
D7 D6
D5 This blt ldenttfles arl NMI lntetruDt caused b\/ the SYSTn1
RESETbutron.
Not
Used
IRQST (IRQ lnrerrupt Status)(D20E): This address reads the dala fron
the IRq Interrupt Status Reglster.
0 = Interrupt
I - No Inlerrupt
D5 D4 D3 D2
IAI.2
IROEN lqcerrupt EnabIe D20E): Thls address wriles
Interrupt data to the IRQ
Enable
c, TV LINE COMROL
V0 not read.
v8 17 v6 v3 \2 vl V0 Tlro llne
resolutlon
supplted.
1 "a".a "f
II1.3
D. GRAPHICSCONTROI.
Not I
Used D5 D4
N o t l l l
Used D
Not I
Used D2 DI DO
DLISTL( Displav List Low )(D402): This address writes data lnto thc
1o!, byie of the Dlsplay Llsl CounEer.
I 0 ,List
\ counter
lBtt
oS SHADOW: SDr,sTL (hex 230) (Posrtlon,
DLISTH (Displav List Hish) (D403): This address wrltes data into the
high byte of the Dlsplay List Counler.
D TI D 6 I D D 4I D 3 I D 2
15 t4 t3 t2 TI 10 9 8 f?lserav
\ co'lnrer
lBit
\?os1t1on.
OS SHADOW: SDLSTH (}TEX231)
Not€: The top 6 birs are latches only and have no count capabll1ty, therefore
lhe displav llst can not cross a lK bvte nenorv boundarv unless a lunD
instructlon ls used.
DLISTL and DLISTIi should be changed only during vettlcal blank or arllh
Dl4A dtsabled. Other:rlse, the screen nay ro11. Bit 7 of NMIENr(rs! be set
in order to recelve dlsplay list lnterrupts.
40 characrer Modes
CI{BASE
20 Character Modes
CIIBASE
12 |lt [0
PMBASE
PI{BASE
II I.6
HSCROL(florizontal Scrolt Reelste!) (D404): This address L.rltes data
lnto lhe llorlzofltal Sclol1 Reglster. Only playfteld ls scrolled, not
Dlavers and Elss1les.
not used | | | |
D3 D2 DI DO
0 to 15 color
clo.k 'iqht Fhl fl c
VSCRoL (Vertlcal Scro1l Reslster) (D405): Thls address {rrltes dara lnro
the Vertical Scroll Reslster.
not used I
D2 D1 DO
not used I
I
PRIoR (Prtorirv) (D0lB): This address writes data into the Prlorltv
Control Reglster.
D7 D6 D2 DI DO
D7-D6 = 0 D5
l4rltlple Color Player Enable.
Thls blt causes the toglcal "or" function of the bits of
the colors of Player 0 wlth Player I, and also of Player 2
sith Player 3. Thls perrlts overlapping the poslrlon of 2
pLayers wilh a choice of 3 colors in lhe overlapped reglon.
III. 7
D4 Flfth Plaver Enable.
This bit causes all mtsstles to assune rhe coLor of playfleld
Type 3. (CoLPI3). thls allovs alsstles ro be posttloned
together with a coomon color fot use as a flfth player.
D3=l D0=l
?F 0 Pc.l
t ?F T
PFO
PF] PI J Pr I
l
PO PF2
f PFo P2 l
P 1l i
P I + P5 PFr P3 _l
I
P 2 2l
P l P0-l pF0
P3.J I PI I - i-s
l"o:- Pr'l
a ?F2 | P2 | Pzf PF2
1P1'
* +3 P5 | P3-,1 P3,J + 5
rAr I
OS SHADOITI: GPRIOR(26I)
C o L P F O- C 0 1 P F 3( P l a v f i e l d C o l o r ) ( D 0 1 6 . p o l 7 . D 0 1 8 . D 0 t 9 ) : T h e s e
addtesses $.rlte data to the Playfield Color-t-ur0 Reglsters,
D 6I D 5 I D 2 t D l t D 0
(see CoLBK for b l t asslgnnent)
OS SHADOWS: COLORO- 3 ( 2 C 4 - 2 C 7 )
III.8
Co],BK (Backeround Color)(D01A): This address wrltes data ro rhe
Background Color-Lum Reglster.
Co
Not
D7 D6 D5 D4 D3 D2 DI Used
0 0 0 0 Grey
0 0 0 1 Gold
0 0 r 0
0 0 1 1 Red-Orange
0 1 0 0
0 I 0 1 Purple
0 1 1 0 Purple-Blue
0 r 1 t Blue
1 0 0 0 Bfue
I 0 0 l 1-igh!-Blue
1 0 r 0 Tu r quoise
l 0 r 1 Green-Blue
1 1 0 0
l l 0 1 Ye11ow-creen
I 1 l 0 Orange-Green
l l l l Llght-Orange
- OS SHADOI.I:CoLORa(2C8)
E. PLAYERSAND MISSII,ES
C o L P M o- C O L P M 3( P l a v e r - M i s s i l e C o l o r ) ( D 0 1 2 , D 0 1 3 , p 0 1 4 , p 0 l 5 ) : These
addresses rr.rlte to the Player-Mlssile Color-Lun Registers. Missiles have
.- the salle color-lun as thelr player unless rnissiles are used as a 5th player
(see bit 4 of PRIoR). A 5th player missile gets irs color frorn CoLPI3.
D D3 D2 D1 DO
(see CoLBK for bit assignnents)
D7 D6 D D3 D2 DI DO
Lefl R l g hr
Playe! on TV Screen
r11.9
GRAFM(Mlsslle Graphlcs Reqlsters)O01I): Thls address r^'rltes data
dllectly lllto the Mlsslle Graphlcs Reglster, lndependent of Dl,tA.
I I I
D7ID6 D5 ID4 D3 D2 D 1I D O
L R L R ] - R ] - R
M3 M2 Ml l{0
N o t l l liorlzontal Slze
used lDrlD0 Register (Player)
0 0 Nornal stze
(8 color clocks vide)
0 1 Twtce Noroal Size
(16 color clocks h{de)
I 0 Nornal slze
Wlth nornal size objecls, each blt in the graphlcs register corresponds
to one color c1ock. Ior laxger objects, each bit ts extended over nore than
one color clock.
SIZEM (Mlsslle Slze)(D00c): Thls address I'rltes data into the ll1sslle
Slze Control Register.
Eorizontal Slze
D7 D6 D5 D4 D3 D2 D1 DO Register (Misstle)
\__\r.--l
M3 M2 Ml MO
0 0 Normal Slze
(2 color clocks \r'Ide)
0 I Twice Nornal Slze
(4 color clocks dde)
I
7 D6 D5 D4 D D2 D1 DO
III,IO
.u,- _
swwer
t, ur ouo:.
uj uuu/r; Inese addresses rN.rlte data into the Misslle itorlzontal
Positlon Reglsrers (see ItpOSpO descrlDtion).
D7 I D D 5I D D 3l D 2 l D l
I ! | i t - - - - - - _ l
p7tp6 lp5 lp4 lp3 D2
| lDrlDO
P3 P2 ?l PO M3 M2 l,1l MO
M g t E ! - Y I P L - l - \ a 2 P F r . l , 1 3(PMPi s s l ] e . r o p t a v f t e t d c o l r i s r o n s ) ( p O o O , p O O r ,
h
, v^u^ z, . u u u r r : Inese addresses read l,tisstte to playfietd Cotlisions.
A I blt neans that a colllslon has been detected since the last HITCLR.
Not used | | | I
o forced) J p3 L D2 | Dt I DO
Playfleld Type
Playfteld Type
Not Used I
D 2 D1 0
Player ltunber
Not osed I I I
rorced) lD3 lD2 lDI lD
I 0 Player Nunber
(Player 0 against player O ts always a zero). Erc.
III.lI
(co1llslon "HlT" clesr) D OI E
IM!B-
Not
I. AUDIO
AUDCTL(Audio Control) (D208): Thls address wrltes data lnto the Audlo
r'roa! C"trt.of r"gr"t.t. {Ll*-"i" SKCTL tro-tone blt 3
7 D6 D5 D D D2 DI DO
FIN FIN
6 4 KtZ 6 3 ,9 2 1 0
- Use norDal forlerla for fout
15 15.6999
Iour = Fin/2N
where N = The blnary nudber 1r) the frequency reglster (AUDF), plus I (N=AUDF+1).
The MODIFIED FORMUI.Ashould be ssed when I1rI = r.t9 ttltL and a rlore
ls desired:
2 (AIIDF + M)
rll.12
AUpII. AUpr2. AUpF3.AUpr4 (Audlo Freouencv) (p200. p202. t204. D206)
These addresses lrrlte data lnlo each of lhe four Audlo Freqrency Control
Reglsters. Each reglster controls a dlvtde by "N" counter.
0 0 0 0 0 0 0 1
I I 0 0 0 - 17 BIT poly - N
I X 1 0 -PureIone-N-r
c I I 0 0 -4BtTpoly-N
I x X - Force Output
(Volune onlY)
8 1 0 0 0 - Ealf Volume
F t l l l - Eighest Volune
Itr. l3
PITCIT VALUBST'ORTIIE I.IUSICALNoTXS-AUDCTL=0. AUDC = hex AX
AI'DF
t{ex Dec
ItrGtt c ID 29
NOTES B 3l
Atl or Bb 2l 33
23 35
e# or Ab 25
G 28 40
l# or Gb 42
! 2D 45
E 2l 41
D# or Eb 32 50
D 35
C# o! Db 39 57
c 3C 60
B 4A 64
AtAor Bb 68
48 72
G# or Ab 4C 76
G 5I 81
F# or cb 55 85
F 5B 9I
E 60 96
D/l or Eb 66 102
D 6c 108
C# or Db 72 II4
I1IDDLE C c 79 t2\
B 80 r28
A# or Bb 88 I36
90 r44
C# or Ab 99 153
G r62
F# or Gb A)D r73
I 182
E CI 193
D# or Eb cc 204
D D9 2t7
L0w c# or Db E6 230
NOTES c 243
R-ANDOM (Randon Nunber Generator) (D20A): This eddress reads the hlgh
order 8 blts of a 17 bit Dolvnonial counter (9 bit, 1f blt 7 of AlrDcTL=t).
D7 D6 D5 D4 D 2
III.I4
G. KEYAOARDAND SPEAKNR
Not used I I I I
ero forced) | D3 | D2 | DI I D0
CONSOI,Btt Assignnent:
I - 0 neans snitch
DI CaroeSelecr \ pressed,
upElon serecE I
D3 Loudspeake! .,,, - should be held at I
except when r.rltlng 0
noEenlarlly. OS nrlles a
I durtng verttc al blank.
D7 D6 D4 D3 D2 DI
D7 = Control Key
D6 - Shifr Key
Read by 0S lnto shadoo CH trhen key ls hlt. The OS has a get character
-
functton whtch converts the keycode to ATASCII (Ararl ASCII).
III.15
KEYCODETO ATASCII CON\,"ERSION
00 L 6C 4C 0c 20 2C 5B 00
OI J OA 2\ SPACE 2 0 20 20
02 ;. 3B 3A 7B 2Z 2R 5D 60
03 23 N 6E 4E OE
04 24
05 K 6B 4B 03 25 M 6D 4D OD
06 + 2R 5C ]E 26 3I
o7 27 ,|\
08 0 6F OI 28 R 12 52 T2
09 29
OA P 70 50 r0 2L E 05
OB U 75 55 15 2R Y 79 59 I9
0c RET 98 9R 9B 2C TAB 9I 9E
OD 69 49 09 2D T 74 54 l4
OE : 2D lc 2E w 77 I7
OF 3D 7C 1D a 7l 5I ll
10 76 56 l6 30 9 39 28
tl 3I
I2 c 63 03 32 0 30 29
I3 33 7 37 27
t4 34 BAC(S 7E 9C FE
15 B 62 42 02 35 8 38 40
16 x 18 58 l8 36 3C 7D 7D
I7 Z 1A 37 3E 9D FT
l8 34 24 38 T 66 46 06
I9 39 H 68 48 08
1A 3 33 23 3A D 64 04
IB 6 36 26 3B
lc ESC IB IB 3C CAPS
ID 5 35 25 3D G 67 4'l 07
IE 2 32 22 FD s 73 53 I3
IF I 3I 2l 3F 4l 01
* = speclal handling
III.I6
H. SERIAL PORT (see perlpheral conoeclor on consofe)
sKcTI- (Serial Port control)(D20F): This address vrltes data lnlo lhe
reglsler that controls the conflguatlon of the serial port' and also the
Fast Pot scan and Keyboald Enable.
D6)
D5 ) sertal Port Mode Control (see mode chalt at end of
D4) set]-a! port description, paee I1.34).
DZ Iast Po! (Fast ?ol Scar. The ?ot Scan Coonler coBPletes its
seqrence tn tlro TV 1lne tlEes instead of one ftane tlne. The
capacltor dunp transislors are completely disabled.)
D0-Dl (Borh Zero) Inltialize (State used for lestlng and inltializing
chiP) *rt
The oS enables key scan and debounce and may change the other blts for
dlfferent I/O operattons. In particular, an aborled cassette operatlofl nay
leave the two tone b1t 1n ihe true state, causlng undesirable audto signals.
Thts i0ay be corrected by \{rltlng hex 13 lo both SKCTL and SSKCTL after dotng
I/0 and/or before nodlfylng the audlo reglslers.
* NOTE: n'hen powered on, serial port output nay stay low even if this blt
ls cleared. To get S.?. hlgh (nark)' send a byte out (reconnend
00 or FF).
III.I7
SKSTAT(Serial Port-Keyboard Slarus)(D20I): This address reads rhe
status reglster glving inforBation about the sellal Dor! and kevboard.
D5 0 = Keyboard Over-run
( SKRES)
D4 0 - Direct from Serlal Input port
(D5 and D6 are se! to
D3 0 = Shtft Key Depressed zero when new data
and sane blt of IRQST
D2 0 = Last Key is Stlll Depressed
SERIN (Sertal Input Dara)(D20D): Thls address reads rhe 8 bit parallel
holdlng register that ls loaded I,hen a fult byte of serlal input dara has
beeo recelved. Thls address ls usually read in response to a serial data ln
inlerrup! (IRQ and bit 5 of IRQST). Also see IRQEN.
D7 D D4 D
6 8 10 t2
III. t8
SERoUT(Se!la1 output Data)(D2oD): This address rffites to the 8 blt
parallel holdlng reglsler tha! ls transferred to Ehe output serlal shlft
reglsier when a fu11 byte of serlal ortpul data has been transmitted. This
address ts usually \rritlen in response to a serial data out inlerrupt (IRQ
and btt 4 of IROST).
D7 D6 D4 D
I. PORTS (front
CONTRoI-LER of console)
PoRTA (Port A)(D300): Thls address reads or lrrltes data from Player 0
and Player I cortroller jacks if blt 2 of PACTL is true. Thls address
wrltes to the dlrectlon conlrol register lf bit 2 of PACTLls zeto. I/o for
both ports (A and B) goes through a 6520/6820
stlck 0Deration
0=Swilch pressed
l=Switch not pressed
Rlght Back Rlght Back
Left . l-eft ftrd.
srick0
(Jack 2) (Jack r)
Paddle
o=Str'itch pressed
l=Sirltch not pressed
board controller 0
ToP Rol.' )
2nd Row \ Jack I
3rd Rowr
4rd
Top Row .\
2nd Rol' Jack 2
3rd Row ,
4rh Ro\t )
0-tnput
l=output
III. 19
PACTL (Port A ControL) (D302) | This addless \"'rites or reads data froro
the Port A Control Reglsler.
Port A Conrrol
D6 D4 D3 D2 DI Reglster
x X x Set up register as shown
(x - descrlbed below)
0=Swltch pressed
l=Switch not pressed
Right Back Rtght Back
srick2
(Jack 4) (Jack 3)
o=Swltch pressed
1=Swltch not pressed
PTRIG6 PTRIG4
?TRIG7 PTRlG5
board C tr
Top row )
2nd Rov \ Jack 3
3 r d Ror' I
4rd
Top Ro\,r)
znd Ror' \ Jack 4
3rd Rol.' f
4th
r1r.20
Dlrectlon Contlo1 Reeister-Addressed if blt 2 of PBCTL is 0
m
l p 7 l p 6 l p 5 l p 4 l p 3 l p 2 l p 1 l p 0 I
t a c h b l t c o r r e s p o n d st o a J a c k p i n
0-tnput
PBCTI (Port B Control) (D303): This address \rrltes ol reads data fron
the Port B Control Register.
Port B Conlrol
Reglster
Sel up .egister as
sholrn (X=Described
bero!')
POT0 - P0T7 (Pol Va1ues) (D200-D207): These addresses read the value (0
to 228) ot 8 pots (paddLe controllers) connected to the 8 lines por port.
The paddle controllers are nuobered from left to right nhen facing the
console keyboard. Turning the paddle knob clockirise results in decreasing
pot values. The values are valld only after 228 TV lines follor1ng the
"POTGO"connaod described beloi.' or after AJ-LPOT
chanees.
D7 D6 D5 D
III.2I
ALIPOT (A11 Pot Lines Siw-rltaneouslv) (D208): This address reads the
present state of the 81ine pot port!
ryL9gl!le:t-.3.e1--gse4 :
No
Data Birs Used
Thls write address atarts the pot scan sequence. The pot values
(POT0 - POTT) should be read first. Thls sr1!e strobe ls then used causlog
the follo!,rlng sequellce,
trl.22
PENIT(Llqht Pen Horlzontal Color Clock Posltlon) (D40C) : Thts address
reads the llorlzontal l,lght Pen Register (based on the horlzontal color clock
counter 1n hardnare). The values range fron 0 !o declnal 227. Wraparound
occurs $hen the pel! lf near the right edge of a standard-!,/ldth screen. pENtt
and PENVare nodllled when any of the loystick trlgger llnes ts pulled loir.
t r t l
4 l D
PENV (L1eht Pen Vertlcal TV Llne Posltton) (D40D) : Thls address reads
the Vertlcal Light ?en Register (8 most slgnlflcant bits, sane as VCOUNT).
D7 D6 D5
L P 8 7 5
resolutlon supplied.
PrA (6s2016820)
Out: TIL tevels, I load
Io : ml levels, 1 load
Jack
Jack
arl.23
ge.!!!.9.1f9r-39:!-3.99s! :
Male lemale
(console) (connector)
I 2 3 5 5 4 3 2 1
8 1 6
Controllers HARDI{ARE os
PIN JOYSTICK I PADDI,E (POT) I KEYBOA.R,D VARIASLES
7 +5 +5
8 GND GND
* Wrlte
** ?oRTA or PORTB
* * * S T I C K0 , 1 , 2 o r 3
lat.24