1/8/2014

VLSI Technology and Design

Introduction

BE-EC SEMESTER-VI SUBJECT- VLSI Technology and Design GTU Subject Code :- 1710412

Prepared by: Amish J. Tankariya

SYLLABUS:

Mr. Amish J. Tankariya

1/8/2014

Mr. Amish J. Tankariya

INTRODUCTION
Integrated Circuits (IC): any transistors on one chi!" Very Large Scale Integration (VLSI) Complementary Metal Oxide Semiconductor (CMOS)
#ast$ chea!$ %lo&'!o&er( transistors circuits

Mr. Amish J. Tankariya

1/8/2014

VLSI
Very Large Scale Integration
Design)*anu+acturing o+ extremely small, co*!le, circuitry using *odi+ied se*iconductor *aterial Integrated Circuit (IC) *ay contain *illions o+ transistors$ each a +e& * in si-e A!!lications &ide ranging: *ost electronic logic de.ices
Mr. Amish J. Tankariya

/OALS O# T0IS COURS1

Learn to design and analyze state-of-t e-art digital VLSI c i!s using CMOS tec nology
Understand design issues at the layout$ transistor$ logic and register'trans+er le.els 2er+or*ance analysis and o!ti*i-ation Use co**ercial design so+t&are in the la3
Mr. Amish J. Tankariya

Com!lexity management "nderstand t e com!lete design flo#

1/8/2014

ORI/INS O# VLSI
uch de.elo!*ent *oti.ated 3y 44II need +or i*!ro.ed electronics$ es!ecially +or radar 5678 ' Russell Ohl 9Bell La3oratories: ' +irst !n ;unction 567< ' Shoc=ley$ Bardeen$ Brattain 9Bell La3oratories: ' +irst transistor 56>? No3el 2hysics 2ri-e Late 56>8s ' !uri+ication o+ Si ad.ances to acce!ta3le le.els +or use in electronics 56>< ' Sey*our Cray 9Control Data Cor!oration: ' +irst transistori-ed co*!uter ' CDC 5?87
7

Mr. Amish J. Tankariya

ORI/INS O# VLSI 9CONT":

56>6 ' @ac= St" Claire Ail3y 9Te,as Instru*ents: ' +irst integrated circuit ' 58 co*!onents on 6 **B 56>6 ' Ro3ert Norton Noyce 9+ounder$ #airchild Se*iconductor: ' i*!ro.ed integrated circuit 56?< ' Noyce$ /ordon 1" oore +ound Intel 56C5 ' Ted 0o++ 9Intel: ' +irst *icro!rocessor 97887: ' BD88 transistors on 6 **B Since then ' continued i*!ro.e*ent in technology has allo&ed +or increased !er+or*ance as !redicted 3y ooreEs La&
8

Mr. Amish J. Tankariya

1/8/2014

$%& VLSI '(SI)*+

Money, tec nology, ci,ilization

40Y VLSI I

2F

A &ay to design electronic circuits Di*ensionally G*icron$ su3*icron$ nano range Current day technology icro electronics cree!ing in all disci!lines''' 9*erger o+ .arious disci!lines in syste* design: Bio'*edical) healthH3rain *a!!ing$ arti+icial intelligence 1lectro*echanical syste*sHro3otics Co**unication$ S*art and secure ho*es$ Identi+ication

10

Mr. Amish J. Tankariya

1/8/2014

DI/R1SSION: SILICON S1

ICONDUCTORS

odern electronic chi!s are 3uilt *ostly on silicon su-strates Silicon is a )rou! IV se*iconducting *aterial Crystal lattice: co.alent 3onds hold each ato* to four neig -ours

Si Si Si

Si Si Si

Si Si Si
http://onlineheavytheory.net/silicon.html

DO2ANTS
Silicon is a semiconductor at roo* te*!erature 2ure silicon has fe# free carriers and conducts !oorly Adding do!ants increases t e conducti,ity drastically Do!ant +ro* )rou! V 9e"g" As$ 2:: extra electron 9n'ty!e: Do!ant +ro* )rou! III 9e"g" B$ Al:: *issing electron$ called ole 9!'ty!e:

Mr. Amish J. Tankariya

Si Si Si

Si

Si Si Si

Si Si Si

Si B

+ -

Si Si Si
12

As Si

Si

1/8/2014

2'N

@UNCTIONS

.irst semiconductor 9t&o ter*inal: de.ices A ;unction 3et&een !'ty!e and n'ty!e se*iconductor +or*s a diode" Current +lo&s only in one direction
p - ty p e anode n - ty p e c a th o d e

13

Mr. Amish J. Tankariya

A Brief History Birth of Morden Electronics

Invention of the Transistor
Vacuu* tu3es ruled in +irst hal+ o+ B8th century Large$ e,!ensi.e$ !o&er'hungry$ unrelia3le 567C: first transistor 9D ter*inal de.ices: Shoc=ley$ Bardeen and Brattain at Bell La3s' &inner o+ No3el !ri-e in !hysics"

14

Mr. Amish J. Tankariya

1/8/2014

A Brief History, contd..

56><: .irst Integrated Circuit #li!'+lo! using t&o transistors Built 3y @ac= Ail3y 9No3el Laureate: at Te,as Instru*ents Ro3ert Noyce 9#airchild: is also considered as a co'in.entor

Mr. Amish J. Tankariya

Kilbys IC
smithsonianchips.si.edu/ augarten/

15

A Brief History, contd.

.irst /laner IC 3uilt in 56?5

Mr. Amish J. Tankariya

B88D Intel 2entiu* 7 I!rocessor 9>> *illion transistors: >5B 3it DRA 9J 8"> 3illion transistors: >DK co*!ound annual gro&th rate o.er 7> years *o ot er tec nology has gro&n so +ast so long Dri.en 3y *iniaturi-ation o+ transistors S*aller is chea!er$ +aster$ lo&er in !o&erL Re.olutionary e++ects on society

16

1/8/2014

MOS Integrated Circuits

56C8Es !rocesses usually had only n OS transistors Ine,!ensi.e$ 3ut consu*e !o&er &hile idle 56<8s'!resent: C OS !rocesses +or lo& idle !o&er
Mr. Amish J. Tankariya

Intel 1101 256-bit SRAM

Intel 4004 4-bit Proc

17

1NIAC ' T01 #IRST 1L1CTRONIC CO 2UT1R 9567?:

18

Mr. Amish J. Tankariya

Digital Integrated Circuits

Introduction

Prentice Hall 1995

1/8/2014

19

20

Mr. Amish J. Tankariya

Mr. Amish J. Tankariya

10

1/8/2014

21

Mr. Amish J. Tankariya

/1N1RAL:
/enerally$ Si-e o+ IC is *easured 3y no o+ logic gates 9Transistors:" A unit o+ *easure is gate e0ui,alent is a *1*' gate . 2 (1 3 4)5, or four transistors 1,a*!le: 588= gate IC MJ 5$88$888 t&o in!ut NAND gates Chi!s are s!eci+ied &ith set of mas6s Minimum dimensions o+ *as=s deter*ine transistor si-e 9and hence s!eed$ cost$ and !o&er:
22

Mr. Amish J. Tankariya

11

1/8/2014

20YSICAL LAYOUT
7ransistor size f M distance 3et&een source and drain 7 e area of t e 7ransistor can -e a!!roximated -y )ate 1rea ($xL) And the )ate 1rea &ill 3e !ro!ortional to the ($8L) ratio o+ the transistor" Set 3y *ini*u* &idth o+ !olysilicon The another *easure o+ the IC %feature size9 is the s*allest sha!e you can *a=e on a chi! and is *easured in : or lam-da; 9since la*3da is eNual to hal+ o+ the s*allest transistor si-e: 23 1,!ress rules in ter*s o+ M f)B 1"g" M 8"D * in 8"? * !rocess OM8"B> u* in a 8"> u* !rocess"

24

Mr. Amish J. Tankariya Mr. Amish J. Tankariya

12

1/8/2014

P Modern transistors are +e& *icrons &ide and a!!ro,i*ately <;= micron or less in length P 0u*an hair is ><-?< microns in dia*eter

Ref: http://micro.magnet.fsu.edu/creatures/technical/sizematters.html

25

Mr. Amish J. Tankariya

Moores Law
56?>: /ordon oore !lotted transistor on each chi! #it straight line on se*ilog scale Transistor counts ha.e dou3led e.ery B? *onths
Mr. Amish J. Tankariya

4hen co*!aring $ clear distinction *ust 3e *ade 3et&een the *e*ory chi!s and logic
chips.

26

13

1/8/2014

Evolution of logic complexity in IC.

27

Mr. Amish J. Tankariya

ITRS- International Technology Roadmap for Semiconductors

28

Mr. Amish J. Tankariya

14

1/8/2014

Shrinking Device Dimensions

Mr. Amish J. Tankariya

29

Increasing Function Density

Mr. Amish J. Tankariya

30

15

1/8/2014

Increasing Clock Frequency

Mr. Amish J. Tankariya

31

Decreasing Supply Voltage

Mr. Amish J. Tankariya

32

16

1/8/2014

Graphical Analysis:
Mr. Amish J. Tankariya

33

AQIN/ VISIONARY

illion transistor)chi! 3arrier &as crossed in the 56<8Es" BD88 transistors$ 5 0- cloc= 9Intel 7887: ' 56C5 7B illion$ B /0- cloc= 9Intel 27: ' B885 578 illion transistor 902 2A'<>88:

34

Mr. Amish J. Tankariya

17

1/8/2014

INTEGRATION OF A LARGE NUMBER OF FUNCTIONS ON A SINGLE CHIP USUALLY PROVIDES:

Less area8,olume and there+ore$ co*!actness Less !o#er consu*!tion Less testing re0uirements at syste* le.el %ig er relia-ility$ *ainly due to i*!ro.ed on'chi! interconnects %ig er s!eed, due to signi+icantly reduced interconnection length Signi+icant cost sa,ings

35

Mr. Amish J. Tankariya

C0I2

ANU#ACTUR1 2ROC1SS:

36

Mr. Amish J. Tankariya

18

1/8/2014

.14@IC17IO* /@OC(SS S(A"(*C(

37

Mr. Amish J. Tankariya

Chip Fabrication: Single Crystal Growth(I)

38

Mr. Amish J. Tankariya

19

1/8/2014

39

40

Mr. Amish J. Tankariya

Mr. Amish J. Tankariya

20

1/8/2014

C0OIC1 O# T1C0NOLO/Y
T&o distinct ty!es o+ technology are +a3ricated in silicon 3ased u!on
B@T 9Bi!olar @unction Transistor: OS 9 etallic O,ide Se*iconductor:

Since !rocessing o+ these technologies is .ery di++erent$ it is i*!ractical to *i, the* u! &ithin a chi!

41

Transistor Types
4i!olar transistors n!n or !n! silicon structure S*all current into .ery thin 3ase layer controls large currents 3et&een e*itter and collector Current Controlled De.ice Base currents li*it integration density Metal O,ide Se*iconductor .ield (++ect 7ransistors (MOS.(7) n OS and ! OS OS#1TS Voltage a!!lied to insulated gate controls current 3et&een source and drain Voltage Controlled De.ice Lo& !o&er allo&s .ery high integration #irst !atent in the EB8s in USA and /er*any Not &idely used until the E?8s or EC8s

42

21

1/8/2014

C0OIC1 O#

OS AND B@T

OS logic occu!ies *uch s*aller area o+ silicon than the eNui.alent B@T logic OS technology has a *uch higher !otential !ac=ing density A OS logic circuit reNuires a!!recia3ly less current and hence less !o&er than its 3i!olar counter !art 0o&e.er$ 3i!olar circuits o!erate +aster than OS circuits 1.en so$ the s!eed'!o&er !roduct +or OS logic co*!ares +a.ora3ly &ith that o+ B@T logic

43

C0OIC1 O#

OS AND B@T

The structure o+ an OS transistor is *uch si*!ler than that o+ 3i!olar de.ices and this *a=es *anu+acturing !rocess easier This in turn should result in +e&er +aults occurring in +a3rication 9high yield: Dyna*ic logic circuits cannot 3e i*!le*ented in 3i!olar technology Thus in ter*s o+ area$ !o&er dissi!ated$ yield and +le,i3ility OS technology is su!erior to B@T

44

22

1/8/2014

SU

ARY

OS Transistors are stac= o+ gate$ o,ide$ silicon and !'n ;unctions Can 3e .ie&ed as electrically controlled s&itches Build logic gates out o+ s&itches Dra& *as=s to s!eci+y layout o+ transistors

45

O4B(C7IV( 1*' O@)1*IC17IO*

O. 7%(

4OOD

46

Mr. Amish J. Tankariya

23

1/8/2014

QUESTIONS

47

Mr. Amish J. Tankariya

24