IRF830

Data Sheet January 2002

4.5A, 500V, 1.500 Ohm, N-Channel Power MOSFET

This N-Channel enhancement mode silicon gate power eld effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specied level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17415.

Features
4.5A, 500V rDS(ON) = 1.500 Single Pulse Avalanche Energy Rated SOA is Power Dissipation Limited Nanosecond Switching Speeds Linear Transfer Characteristics High Input Impedance Related Literature - TB334 Guidelines for Soldering Surface Mount Components to PC Boards

Ordering Information
PART NUMBER IRF830 PACKAGE TO-220AB BRAND IRF830

Symbol
D

NOTE: When ordering, include the entire part number.

Packaging
JEDEC TO-220AB

SOURCE DRAIN GATE

DRAIN (FLANGE)

2002 Fairchild Semiconductor Corporation

IRF830 Rev. B

This datasheet has been downloaded from http://www.digchip.com at this page

IRF830
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specied IRF830 500 500 4.5 3.0 18 20 75 0.6 300 -55 to 150 300 260 UNITS V V A A A V W W/oC mJ oC
oC oC

Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 1. TJ = 25oC to 125oC.

Electrical Specications
PARAMETER

TC = 25oC, Unless Otherwise Specied SYMBOL BVDSS VGS(TH) IDSS ID(ON) IGSS rDS(ON) gfs td(ON) tr td(OFF) tf Qg(TOT) Qgs Qgd CISS COSS CRSS LD Measured from the Modified MOSFET Contact Screw on Tab to Symbol Showing the Center of Die Internal Devices Measured from the Drain Inductances Lead, 6mm (0.25in) From Package to Center of Die
D LD G LS S

TEST CONDITIONS VGS = 0V, ID = 250A (Figure 10) VGS = VDS , ID = 250A VDS = Rated BVDSS , VGS = 0V VDS = 0.8 x Rated BVDSS , VGS = 0V, TJ = 125oC VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = 20V VGS = 10V, ID = 2.5A (Figures 8, 9) VDS 10V, ID = 2.7A (Figure 12) VDD = 250V, ID 4.5A, RG = 12, RL = 54 MOSFET Switching Times are Essentially Independent of Operating Temperature.

MIN 500 2.0 4.5 2.5 -

TYP 1.3 4.2 10 15 33 16 22 3.5 11 600 100 20 3.5

MAX 4.0 25 250 100 1.5 17 23 53 23 32 -

UNITS V V A A A nA S ns ns ns ns nC nC nC pF pF pF nH

Drain to Source Breakdown Voltage Gate to Threshold Voltage Zero-Gate Voltage Drain Current

On-State Drain Current (Note 2) Gate to Source Leakage Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Gate to Drain Miller Charge Input Capacitance Output Capacitance Reverse-Transfer Capacitance Internal Drain Inductance

VGS = 10V, ID 4.5A, VDS = 0.8 x Rated BVDSS Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature.

VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11)

4.5

nH

Internal Source Inductance

LS

Measured from the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad

7.5

nH

Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient

RJC RJA Free Air Operation

1.67 62.5

oC/W oC/W

2002 Fairchild Semiconductor Corporation

IRF830 Rev. B

IRF830
Source to Drain Diode Specications
PARAMETER Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) SYMBOL ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode
G D

MIN -

TYP -

MAX 4.5 18

UNITS A A

Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovered Charge NOTES:

VSD trr QRR

TJ = 25oC, ISD = 4.5A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 4.5A, dISD/dt = 100A/s TJ = 25oC, ISD = 4.5A, dISD/dt = 100A/s

180 0.96

350 2.2

1.6 760 4.3

V ns C

2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 25mH, RG = 25, peak IAS = 4.5A.

Typical Performance Curves

1.2 POWER DISSIPATION MULTIPLIER 1.0

Unless Otherwise Specied

5

0.8 0.6 0.4 0.2 0 0 50 100 150 TC , CASE TEMPERATURE (oC)

ID , DRAIN CURRENT (A)

0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150

FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE

FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE

ZJC , NORMALIZED TRANSIENT

1 THERMAL IMPEDANCE 0.5 0.2 0.1 0.1 0.05 0.02 0.01 SINGLE PULSE

PDM

t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 0.1 1 10

0.01 10-5

10-4

t1 , RECTANGULAR PULSE DURATION (s)

FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE

2002 Fairchild Semiconductor Corporation

IRF830 Rev. B

IRF830 Typical Performance Curves

102 OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 10 10s 100s 1 TC = 25oC TJ = MAX RATED SINGLE PULSE 1 102 10 VDS , DRAIN TO SOURCE VOLTAGE (V) 1ms 10ms 100ms DC 103

Unless Otherwise Specied (Continued)

6 5 ID , DRAIN CURRENT (A) 4 3 2 1 0 0 50 100 150 200 250 300 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS = 10V VGS = 5.5V

ID , DRAIN CURRENT (A)

VGS = 5.0V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 4.5V

VGS = 4.0V

0.1

FIGURE 4. FORWARD BIAS SAFE OPERATING AREA

FIGURE 5. OUTPUT CHARACTERISTICS

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX

VGS = 10V

VGS = 5.5V VGS = 5.0V

IDS(ON), DRAIN TO SOURCE CURRENT (A)

ID , DRAIN CURRENT (A)

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS > ID(ON) x rDS(ON)MAX

3 TJ = 125oC 2 TJ = 25oC TJ = -55oC

VGS = 4.5V

VGS = 4.0V

0 0 2 4 6 8 VDS , DRAIN TO SOURCE VOLTAGE (V) 10

0 0 1 2 4 5 3 VGS , GATE TO SOURCE VOLTAGE (V) 6 7

FIGURE 6. SATURATION CHARACTERISTICS

FIGURE 7. TRANSFER CHARACTERISTICS

10

NORMALIZED DRAIN TO SOURCE ON RESISTANCE

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX

2.2

rDS(ON) , DRAIN TO SOURCE

8 ON RESISTANCE ()

1.8

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 2.5A, VGS = 10V

6 VGS = 10V 4 VGS = 20V 2

1.4

1.0

0.6

0 0 4 16 8 12 TC , CASE TEMPERATURE (oC) 20

0.2 -60

-40

-20

20

40

60

80

100

120

140

TJ , JUNCTION TEMPERATURE (oC)

FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT

FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE

2002 Fairchild Semiconductor Corporation

IRF830 Rev. B

IRF830 Typical Performance Curves

1.25 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A

Unless Otherwise Specied (Continued)

2000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS

1.15 C, CAPACITANCE (pF)

1600

1.05

1200 CISS COSS 400 CRSS

0.95

800

0.85

0.75 -40

-20

20

40

60

80

100

120

140

160

0 1 40 10 20 30 VDS , DRAIN TO SOURCE VOLTAGE (V) 50

TJ , JUNCTION TEMPERATURE (oC)

FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE

FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE

5 gfs , TRANSCONDUCTANCE (S)

ISD , SOURCE TO DRAIN CURRENT (A)

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TJ = -55oC TJ = 25oC

2 100 5 2 10 5

PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX

TJ = 125oC

TJ = 150oC

TJ = 25oC 2 1

2 3 ID , DRAIN CURRENT (A)

3 1 2 VSD , SOURCE TO DRAIN VOLTAGE (V)

FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT

FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE

20 VGS , GATE TO SOURCE VOLTAGE (V) ID = 4.5A

15

VDS = 100V VDS = 250V

10

VDS = 400V

0 0 8 16 24 32 40 Qg , GATE CHARGE (nC)

FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE

2002 Fairchild Semiconductor Corporation

IRF830 Rev. B

IRF830 Test Circuits and Waveforms

VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD

0V

IAS 0.01

0 tAV

FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT

FIGURE 16. UNCLAMPED ENERGY WAVEFORMS

tON td(ON) tr RL VDS

+

tOFF td(OFF) tf 90%

90%

RG DUT

VDD 0

10% 90%

10%

VGS VGS 0 10%

50% PULSE WIDTH

50%

FIGURE 17. SWITCHING TIME TEST CIRCUIT

FIGURE 18. RESISTIVE SWITCHING WAVEFORMS

CURRENT REGULATOR

VDS (ISOLATED SUPPLY) VDD SAME TYPE AS DUT Qg(TOT) Qgd Qgs D VDS VGS

12V BATTERY

0.2F

50k

0.3F

DUT 0

Ig(REF) 0 IG CURRENT SAMPLING RESISTOR

S VDS ID CURRENT SAMPLING RESISTOR Ig(REF) 0

FIGURE 19. GATE CHARGE TEST CIRCUIT

FIGURE 20. GATE CHARGE WAVEFORMS

2002 Fairchild Semiconductor Corporation

IRF830 Rev. B

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Rev. H4