UNIVERSITY OF COLOMBO Examination in M.Sc.

/ Postgraduate Diploma in Applied Electronics Semester I 2011

MEL 5101 Analogue and Digital ICs and their Applications Two (2) hours This question paper consists of 6 questions and 6 pages Answer any Four (4) Questions

1. In the circuits shown figures a and b , Vref represents a positive reference voltage, and Ei represents a variable voltage. The two op amps have totem-pole type outputs.

_ Vo +

Vref

_ Vo +

Vref R nR

Ei

nR

Figure a
(a) Draw curves to show how V0 varies with Ei.

Figure b

(b) A control circuit is to be designed to maintain the temperature of a water bath at a mean temperature of 80 C by using an electric heater. Assume that a temperature variation of C around the mean temperature can be allowed. Also assume that you are provided with an analog temperature sensor which produces a voltage of 8 V at 80 C, and this value varies at the rate of 2V per degree. Derive all the relevant expressions, and design the control circuit.

2. A 555 timer whose circuit symbol, and the status of the output and the discharge transistor under different conditions of the threshold and trigger voltages are shown below. All the symbols have their usual meaning.

4 2 6 7

1 - Ground 2 - Trigger 3 - Output 4 - Reset 5 Control voltage 6 - Threshold 7 Discharge 8 - VCC

State A B C D

Trigger input (2) Below VLT (<VCC/3) Below VLT (<VCC/3) Above VLT (>VCC/3) Above VLT (>VCC/3)

Threshold input (6) Below VUT (<2VCC/3) Above VUT (>2VCC/3) Below VUT (<2VCC/3) Above VUT (>2VCC/3)

State S of F-F 1 1 0 0

State R Output Q of F-F (3) 0 0 0 1 High High Remembers old output Low

Discharge transistor Open Open

Low Low Last state High

Closed (Capacitor discharges)

(a) The waveform Ei is applied to the circuit shown below. Clearly giving reasons as to how the output waveform develops as the input passes through the time sectors AB, BC, CD, and DE, draw the expected output waveform.

(b) Design a torn burst oscillator using two 555 ICs, and explain its action. 2

3. Block diagram of the XR 2240 programmable Timer/Counter is shown below.

(a) Draw the timing diagram to show the output waveform when the 4th (8T) and 5th (16T) outputs of the counter are connected to a power supply through a common pull-up resistor (b) Show how you would wire XR 2240 for monostable operation. If C = 1 calculate the minimum and the maximum programmable timing cycles. and R = 5 M

(c) How would you modify the circuit given in (b) above to operate as a free running oscillator.

4. The figure below shows the internal circuit of a TTL gate.

(a) Briefly describe what happens (i) when both inputs are held high and (ii) when both inputs are held low (iii) when both inputs are left floating. Why is leaving any inputs of a TTL gate floating is not recommended? Giving reasons, briefly explain under what conditions the output behaves as a current sink. (b) With a suitable circuit diagram, briefly explain the operation of a CMOS gate. Explain why CMOS gates draw very low power compared to TTL? How does the power consumption vary with increasing frequency and increasing supply voltage? Give reasons for these behaviours. (c) With a suitable diagram, explain how you would implement the logic expression using a 8 to 1 multiplexer.

Draw a block diagram to show how you would combine two 4-to-1 multiplexers to construct one 8-to-1 multiplexer.

5. (a) Analyze the following circuit and indicate its behaviour in a state diagram.

A D0 Q0 Q0

D1

Q1

clk

(b) A synchronous circuit has an enable input E and a clock input Clk. When clock pulses arrive through the Clk input, the circuit counts from 0 to 4 in binary and then resets to 0, provided E is held at 0. If E is held high at the time a clock pulse arrives, the circuit stays in the same state as it was before the clock pulse. If the circuit is in any state other than a state represented by a value from 0 to 4, it changes to 0 after the first clock pulse, irrespective of the value of E. Draw a state diagram to display this behaviour. (c) Suppose the circuit in part (b) above is initially in the state represented by binary 5 and that it receives 5 clock pulses. During the first 4 clock pulses, E is held low. Immediately after the 4th clock pulse E is changed to 1. Assuming that the transitions happen at the rising edge of the clock pulse, draw a timing diagram to indicate the behavior of the circuit. (The timing diagram must show the inputs E and Clk, and all the flip-flop outputs). 6. Following is a pin diagram of a DRAM chip.

(a) Determine the number of data bits available in this chip. Explain how data are readout using the RAS, CAS and WE control signals. How many of these chips would be required to implement a 16-bit memory module with 16k words? (b) In the serial port of a normal PC, the Rx, Tx and ground pins are pin 2, pin 3 and pin 5 respectively.

The serial port of a certain laboratory test device also was found to have the same pin assignment, according to its manual. Draw a suitable diagram to show how you would connect this device to a PC for serial communication with no handshaking. What other information will you need to find from the manual of the device, for setting up software for serial communication? (d) The control word format of the 8254 timer is shown below.

Write down the control words for initializing the three counters as follows: (i) Counter 0: mode 2, binary format, read/write least significant byte only. (ii) Counter 1: mode 5, binary format, read/write both bytes. (iii) Counter 2: mode 0, binary format, read/write both bytes.

----------------------------- 0 0 0 0 0 0 ---------------------------------