Scan-Based BIST - Organization

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Architecture First Scan-Based BIST Random Test Socket STUMPS Dependencies Linear Structural Solutions Reseeding LFSRs Bit Manipulation Test Point Insertion Phase Shifters Multiple Capture Cycles Benefits and Limitations
Scan-Based BIST 1

Basic Scan-Based BIST Approaches

Manufacturing vs. System level used determines complexity of architecture For system-level use Input isolation BIST controller for
Scan/system mode clocking Shift count control Control number of test patterns Pattern count control Enable MISR compaction
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Scan BIST Controllers

During BIST sequence, must control Scan Mode for shifting

Test patterns Output responses

System Mode for

Application of test patterns

MISR compaction disable

During initial test patterns shift After completion of BIST sequence
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STUMPS by IBM

Self-Test Using MISR/Parallel SRSG

Shift Register Sequence Generator (SRSG)

by Bardell, McAnney & Savir, 1987 Used in many IBM computers Centralized BIST Can be used at chip level
requires multiple scan chains

LFSR
Chip or Scan Chain 1 Chip or Scan Chain N

Can be used at board level

requires all chip have scan design

Test-per-scan BIST MISR and LFSR combined in special purpose test chip for board or system level test
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MISR

Problems with Scan-Based BIST

Not all patterns generated by LFSR or CAR when applied to scan chains Result of pseudo-random properties of LSFR/CAR Critical test patterns for fault coverage may be missing Structural Dependencies Occur in multiple scan chains Linear Dependencies Occur in single and multiple scan chains STUMPS architectures can have both structural and linear dependencies

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Scan-Based BIST

Structural Dependencies

Recall the obvious shift in patterns in LFSR CARs also have shifting pattern properties near null boundary conditions
External Feedback LFSR 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 1 1 0 1 0 1 1 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 1 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 1 1 0 0 1 1 0 0 1 1 1 0 C. Stroud 4/13 Internal Feedback LFSR 1 1 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 0 1 1 0 1 0 0 1 Scan-Based BIST Cellular Automata Register 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 1 0 0 1 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 0 0 1 0 1 1 1 0 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 0 0 0 1 1 1 0 0 1 0 1 0 1 1 1 1 1 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 0 1 1 1 1 1 6

Structural Dependencies

Assume a 22 window of patterns Would be case for a 4-input logic cone driven by 2 adjacent scan chains and 2 adjacent bits in those scan chains Use LFSRs/CAR on previous page External FB LFSR
Produces 8/16 = 1/2 of patterns Produces 128/512 = 1/4 patterns in a 33 window

22 test External FB Internal FB pattern LFSR LFSR

0000 1000 0100 1100 0010 1010 0110 1110 0001 1001 0101 1101 0011 1011 0111 1111 any 2 adj bits not produced any 2 adj bits not produced any 2 adj bits not produced any 2 adj bits not produced not produced any 2 adj bits not produced any 2 adj bits not produced any 2 adj bits not produced any 2 adj bits bits 1&2, 4&5 not produced bits 1&2, 4&5 not produced bits 4&5 bits 1&2 bits 4&5 bits 1&2 not produced bits 1&2, 4&5 not produced bits 1&2, 4&5 bits 1&2 bits 4&5 bits 1&2 bits 4&5

CAR
bits 1&2, 7&8 bits 1&2 bits 7&8 not produced bits 7&8 not produced bits 1&2, 7&8 bits 1&2 bits 1&2 bits 1&2, 7&8 not produced bits 7&8 not produced bits 7&8 bits 1&2 bits 1&2, 7&8

Internal FB LFSR
Produces all possible patterns at adjacent non-0-coefficients P(x)=x8+x6+x5+x+1 Similar to external FB at 0 coefficients
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CAR
Produces all possible patterns in middle of register Similar to external FB at null boundary conditions 7

Scan-Based BIST

Linear Dependencies

LFSR produces 2n-1=15 patterns to a 10-bit scan chain Only 3 unique vectors applied to NOR gate
Do not detect any of the inputs sa0

Some definitions for linear dependency design guidelines: Span = largest number of flip-flops in scan chain between inputs to same logic cone Sampling polynomial describes logic cone connections Sampling polynomial to scan chain
S(x) = x8+x7+x4 = x4+x3+1 |span=5|
D Q x1 CK D Q x2 CK D Q x3 CK D Q x4 CK

1 2 3 4 5 6 7 8 9 10
Scan Vectors #1 1001000111 #2 0011110101 #3 1010110010 #1 1001000111

Scan Chain

101011001000111 101011001000111 repeat time

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repeat
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Scan-Based BIST

Linear Dependency Design Guidelines

For the following design guidelines, let: n = degree of P(x) NFF = # flip-flops in longest scan chain NCC = # clock cycles in scan mode (NCC NFF) NTV = # scan vectors to be applied Design Guidelines to reduce linear dependencies: Choose n such that 2n-1 & NFF do not have common divisor, or Choose NCC such that 2n-1 & NCC do not have common divisor Choose n such that 2n-1 NFF NTV Choose n > largest span

In previous example, n=4 but span=5

Look at sampling polynomials, linear dependencies exist if If S(x) mod P(x) = 0

Similar to signature aliasing conditions

If sub-polynomials of S(x) mod P(x) = 0

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Other Approaches to Linear Dependencies

Note that design guidelines for reducing linear dependencies tend to create large n, then 2n-1 is very large Scan Chain LFSR Long test times, particularly for test-per-scan BIST Bit Shift Cnt Flip Other approaches include Pattern Cnt Logic Reseeding LFSR Multiple polynomials for LFSR LFSR Scan Chain Bit manipulation
Bit flipping Bit fixing
fix-to-1 fix-to-0

Shift Cnt Pattern Cnt

Scan-Based BIST

Multiple capture cycles Test point insertion

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Bit Fix Logic

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Partial Scan BIST by Lucent

by Lin et al., 1993 PIs POs CUT Requires near acyclic CUT L M feedback loops have length = 1 F I S only a subset of FFs scanned Scan Chain S R R Separate BIST architecture mix of test-per-clock & test-per-scan primary output values compressed every clock cycle responses captured in scan chains every scan cycle Uses multiple (k) capture cycles after each scan cycle uses different k values during test yields higher fault coverage (~1-1.5%) & shorter test sequences (~60%) for small increase in area overhead (~1%)
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Minimizing Structural Dependencies

Design guidelines: choose n such that 2n-1 NFF NSC NFF = # flip-flops in longest scan chain NSC = # scan chains Incorporate phase shifter Removes the shifting pattern properties by adjusting phase of adjacent bits in LFSR
Similar results to CAR

Phase Shift = 9 wrt previous channel

Can be implemented with shift registers

More efficient implementation with XORs
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Phase Shifter Design

1.

Construct the dual of the TPG LFSR

Dual of internal FB LSFR is external FB LFSR with same polynomial, And vice versa

LFSR

2.

3.

Phase Shifter Initialize dual LFSR with all-0s except for 1 in ith stage and simulate for k clock cycles Chip Chip where k is maximum possible phase shift or or Scan Scan desired for any channel wrt ith stage Chain Chain The logic 1s contained in contents of dual 1 N LFSR at the jth clock cycle indicate outputs of original LFSR to be XORed to create MISR channel with a phase shift of j clock cycles wrt ith stage
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Example Phase Shifter

Assume TPG is external FB LSFR with P(x)=x4+x+1 then dual is internal FB LFSR with state diagram given below Assume we want 5-channel phase shifter and the following phase shifts per channel wrt x1 c1 = 0, c2 = 6, c3 = 4, c4 = 12 = -3, c5 = 7 Using the design procedure we get: c1 = x1 c2 = x3x4 Start here c3 = x1x2 c4=12ccs c1=0ccs c4 = x1x2x3x4 = c2c3 c5 = x1x2x4 = c3x4
c5=7ccs c2=6ccs
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c3=4ccs
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Example Phase Shifter

4 XOR gates needed to produce 5 channels with specified phase delays:

c1 = 0 c2 = 6 c3 = 4 c4 = 12 = -3 c5 = 7 0 1 2 3 4 5 6 7
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8 9 10 11 12 = -3

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Scan-Based BIST Summary Advantages

Short test application time & at-speed testing Vertical testability same for all levels of testing: devicesystem may be applied hierarchically from device through system High fault & defect coverage Provides embedded ATE reduces need for expensive external ATE Reduced system diagnostic test development 50% of BIST applications at Bell Labs initiated by diagnosticians Growing support by CAD vendors
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Scan-Based BIST Summary (cont.) Disadvantages

Area overhead typically 10-25% all costs of full scan in many BIST approaches plus more
extra logic for TPG & ORA BIST controller

Fault simulation may be lengthy but necessary to determine fault coverage Additional risk to project must design BIST & system function
longer design time if no CAD automation available both must work for chip to ship

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Scan-Based BIST

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Area Overhead of Scan-Based BIST

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