A Novel FB ZVS PWM DC-DC Converter Based on

Digital Control
Pinghua Tang, Guijie Yang, Tiecai Li, Yajing Liu
Department of Electrical Engineering
Harbin Institute of Technology
Harbin 150001,China
tphqh@163.com
Abstract - Conventional full-bridge(FB) zero-voltage-
switching (ZVS) PWM DC-DC converter has several
disadvantages, such as serious loss of duty cycle, narrow range of
ZVS of the lagging leg, and voltage overshoot in the secondary
etc. This paper presents a novel FB ZVS PWM DC-DC
converter, which adds two passive circuits based on the
conventional FB DC-DC converter. One is paralleled in the
primary to widen the ZVS range of the lagging leg; the other is in
series to the secondary to reduce the voltage overshoot and
oscillation of the secondary voltage, so the voltage stress of
rectified diodes has greatly reduced. The proposed circuit
topology has several advantages, such as easily controlled, wide
load ZVS range, and small loss of the duty cycle etc. so it can
increase the efficiency of the converter. This paper analyses the
operating principle of the converter and the ZVS qualifications.
A digital control system with double-loop is also designed using
TMS320F2812 DSP. A 48V/480W, 100kHz prototype which
based on digital control verified the validity the relative theory.
Index Terms ZVS, digital control, DC-DC converter, passive
circuit.
I. INTRODUCTION
With the advent of the FB phase-shifted ZVS PWM DC-
DC converter, it has received considerable attention, and has
been studying in the application of middle/high power[1-2].
This converter has several advantages, such as easily controlled,
ZVS of power switch using the parasitic elements, and low
voltage/current stress of the power switches and so on. These
advantages make it very attractive for high frequency and high
power applications where MOSFETs are predominantly
used[3-4]. However, this converter also has some
disadvantages, such as the serious loss of the duty cycle, large
voltage stresses of the rectified diodes, small ZVS load range
of the lagging leg etc.[5], which limit its application.
To overcome these disadvantages of the ZVS PWM DC-
DC converter, many researchers have done a lot of work to
improve the construction of the topology, but in general,
including two approaches: one is to achieve the ZCS of the
lagging leg, the other is to achieve the ZVS of the lagging leg.
However, it is also very necessary to study FB soft converter.
This paper proposes a novel ZVS PWM DC-DC converter
topology based on what the predecessors have done. The
proposed converter adds two passive circuits on the basis of the
conventional converter topology. One is paralleled in the
primary to widen the ZVS range of lagging leg; the other is in
series to the secondary to reduce the voltage overshoot and
oscillation. This novel converter topology has several
advantages, such as wide ZVS load range, small loss of duty
cycle, high efficiency, and small voltage stress of the rectified
diodes. This paper analyses the operating principle of the
converter and the ZVS qualifications. A digital control system
with double loop is also designed using TMS320F2812 DSP
chip. The experimental result demonstrates the validity of
relative theory.
II. OPERATING PRINCIPLE OF THE PROPOSED
CONVERTER
The basic structure of the proposed converter is the same
as conventional FB ZVS PWM DC-DC converter, and two
passive circuits are added as show in fig.1. One is named
Circuit1, which is composed by a reactor inductor, two diodes
and two capacitors; the other is named Ciruit2, which is
composed with three diodes and two capacitors. Ciruit1 is used
to widen the ZVS range of the lagging leg, and Circuit2 is used
to reduce the voltage stress of the rectified diodes. To illustrate
the steady-state operation of the converter, all devices and
components are assumed to be ideal.
Q
Q
Q
Q
C C
C
C
C
D
D D
D D
D C
T
D
D
D
D
L
C
L
L
C
C
lk
1 1 1
2
a
3
6
2 3
s2
4 4
b
4
3 2
a
5
s1
b
s
s1 s2
f
f
Vin
r
R
Circuit1
Circuit2
D
Fig.1 Circuit diagram of the proposed converter
The new converter has eight modes within each operating
half-cycle. The operation waveform diagram is shown in fig.2,
and equivalent circuits are shown in fig.3. Operation modes for
half cycle are described in detail as follows.
Mode1[t
0
~t
1
]: At the time t
o
, both Q
1
and Q
3
are conducting,
the current of the primary increases linearly; secondary
winding charges circuit2, in other words, the current flows
through C
s2
, D
s
and C
s1
. then the voltage of C
a
is zero, and the
voltage of C
b
is equal to V
in
, the reactor inductor, L
r
, is
1-4244-0332-4/06/$20.00 2006 IEEE
8457
Proceedings of the 6th World Congress on Intelligent Control
and Automation, June 21 - 23, 2006, Dalian, China
unsaturated, the value of L
r
is very big, and the current which
flows it is zero. As is shown in fig3(a).
t
t
t
t
t
t
t
Q1 Q2 Q1
Q3 Q4 Q3
Vgs
Vgs
VT1
VT2
Ilk
Ics
ILr
t0 t1 t2 t3 t4 t5 t6 t7 t8 t9
Fig.2 Operation waveforms of the proposed converter
Mode2[t
1
~t
2
]: At the time t
1
, both Q
1
and Q
3
conduct, the
input power is delivered to the load directly through the
transformer. Circuit2 is full charged. As is shown in fig.3(b).
Mode3[t
2
~t
3
]: At the time t
2
, Q
1
is turned off. It achieves
zero-voltage turn-off because of the clamping of C
1
. Then the
energy stored in the leakage inductor and part of energy in the
filter inductor charges C
1
, and C
2
also charges C
1
. D
2
naturally
conducted when the voltage of the C
2
is zero, this is the
qualification to achieve the zero voltage turn-on of Q
2.
At the
same time, the current of the primary reduces, and the power
which delivered to the secondary reduces, D
s1
and D
s2
begin to
conduct, so the power which stored in the circuit2 begins to
deliver to the load. As is shown in fig.3(c).
Mode4[t
3
~t
4
]: At the time t
3
, zero voltage turn-on Q
2
, the
current of the primary winding reduces to zero, so it is the
secondary winding, the remainder energy in circuit2 delivers to
load. As is shown in fig.3(d).
Mode5[t
4
~t
5
]: At the time t
4
, the energy stored in circuit2
has been reduced to zero, and the voltage of the circuit2 is zero
too, then D
s2
, D
s
, D
s1
conduct at the same time just like a free
wheeling diode. In this interval, the power which the load need
is supplied by C
f
. As is show in fig.3(e).
Mode6[t
5
~t
6
]: At the time t
5
, Q
3
can achieve zero voltage
turn-off because of the clamping of C
3
. Then the reactor
inductor, L
r
, becomes saturated. In this interval, L
r
works just
like a small inductor, and its value is bigger than L
lk
. The
current of L
r
increases linearly, and charges C
3
quickly.
Circuit1 begins to work, C
a
is charged and C
b
is discharged. As
is shown in fig.3(f).
Q
Q
Q
Q
C C
C
C
C
D
D D
D D
D C
T
D
D
D
D
L
C
L
L
C
C
lk
1 1 1
2
a
3
6
2 3
s2
4 4
b
4
3 2
a
5
s1
b
s
s1 s2
f
f
Vin
r
R
D
(a) Mode1
Q
Q
Q
Q
C C
C
C
C
D
D D
D D
D C
T
D
D
D
D
L
C
L
L
C
C
lk
1 1 1
2
a
3
6
2 3
s2
4 4
b
4
3 2
a
5
s1
b
s
s1 s2
f
f
Vin
r
R
D
(b) Mode2
Q
Q
Q
Q
C C
C
C
C
D
D D
D D
D C
T
D
D
D
D
L
C
L
L
C
C
lk
1 1 1
2
a
3
6
2 3
s2
4 4
b
4
3 2
a
5
s1
b
s
s1 s2
f
f
Vin
r
R
D
(c) Mode3
Q
Q
Q
Q
C C
C
C
C
D
D D
D D
D C
T
D
D
D
D
L
C
L
L
C
C
lk
1 1 1
2
a
3
6
2 3
s2
4 4
b
4
3 2
a
5
s1
b
s
s1 s2
f
f
Vin
r
R
D
(d) Mode4
8458
Q
Q
Q
Q
C C
C
C
C
D
D D
D D
D C
T
D
D
D
D
L
C
L
L
C
C
lk
1 1 1
2
a
3
6
2 3
s2
4 4
b
4
3 2
a
5
s1
b
s
s1 s2
f
f
Vin
r
R
D
(e) Mode5
Q
Q
Q
Q
C C
C
C
C
D
D D
D D
D C
T
D
D
D
D
L
C
L
L
C
C
lk
1 1 1
2
a
3
6
2 3
s2
4 4
b
4
3 2
a
5
s1
b
s
s1 s2
f
f
Vin
r
R
D
(f) Mode6
Q
Q
Q
Q
C C
C
C
C
D
D D
D D
D C
T
D
D
D
D
L
C
L
L
C
C
lk
1 1 1
2
a
3
6
2 3
s2
4 4
b
4
3 2
a
5
s1
b
s
s1 s2
f
f
Vin
r
R
D
(g) Mode7
Q
Q
Q
Q
C C
C
C
C
D
D D
D D
D C
T
D
D
D
D
L
C
L
L
C
C
lk
1 1 1
2
a
3
6
2 3
s2
4 4
b
4
3 2
a
5
s1
b
s
s1 s2
f
f
Vin
r
R
D
(h) Mode8
Fig.3 Equivalent circuit diagrams of the different modes
Mode7[t
6
~t
7
]: At the time t
6
, the current of Lr charges C
3
,
and discharges C
4
. Then the current of L
r
decreases. The
secondary is in the freewheeling interval. As is shown in
fig.3(g).
Mode8[t
7
~t
8
]: At the time t
7
, the voltage of C
4
reduces to
zero, and D
4
conducts naturally, then the voltage of Q
4
is
clamped to zero. This achieves zero voltage turn-on for Q
4
. The
current of L
r
decreases to zero. In circuit1, the voltage of C
b
reduces to zero, and the voltage of Ca increases to V
in
, D
b
conducts naturally. As is shown in fig.3(h).
The operation of the next half cycle is the same as the first
half cycle, and is shorted here.
III. ZVS QUALIFICATION OF THE PROPOSED
CONVERTER
If the power switch will be turned on at zero voltage, there
must be enough energy to discharge the parasitic capacitor, and
charge the parasitic capacitor of other power switch which
belongs to the same leg. It can be express as:
2
i in
E CV > (1)
Where i is leading or lagging.
A. Leading leg
During the turn-on process of the power switch, the quasi-
resonance between L
lk
, the inductor which return to the
primary by L
f
and parasitic capacitor. Because the value of the
L
f
is very large, so the ZVS qualification of the leading leg is
easily satisfied. It can be express as:
2 2
2
1 1
2
lk f lk lead in
L L I C V
n
| |
+ >
|
\ .
(2)
Where n is the ratio of winding between the primary and
the secondary, I
lk
is the max current of the leakage inductor.
B. Lagging leg
In conventional converter, the energy that is used to
achieve ZVS of lagging leg is supplied only by L
lk
, so it is
difficult to achieve ZVS if the L
lk
is too small. But if L
lk
is too
large, it will cause serious loss of duty cycle. However, in the
proposed converter, the ZVS of lagging leg is easily achieved,
because there are two inductors charge the parasitic capacitors
during the turn-on of the power switches, one is L
lk
, the other is
L
r
. The ZVS qualification can be expressed as:
2 2 2
1 1
2 2
lk lk ro Lr lag in
L I L I C V + >
(3)
Where L
ro
is the value when L
r
is in saturation, I
Lr
is the
max value of the current which flows through L
r
.
IV. DIGITAL CONTROL SYSTEM OF THE PROPOSED
CONVERTER
Digital control has several advantages, such as easily
control, no temperature float, and strong ability etc.[6-7]. This
paper selects a double digital loop control strategy based on
8459
TMS320F2812 DSP chip. The block diagram of the converter
system is shown as Fig.4.
Fig.4 shows that the digital system includes two control
loops, the inner is current loop, and the external is voltage
loop. Current loop samples from voltage current, and the
sampling signal is processed by TMS620F2812 DSP chip to
get inverse feedback signal for the current digital regulator.
The external loop samples from the output voltage, and the
sampling signal is also processed by the DSP chip to get the
inverse voltage feedback signal which input the voltage digital
regulator, and the output of the voltage digital is used as the
demanding signal. The output of the current digital regulator
is used to be the input of the driving circuit.
Load
Rectifier
and
filter
PWM
Converter
Current
feedback
signal
Voltage
feedback
signal
Current
digital
regulator
Voltage
digital
regulator
Sampling
and
holding
Sampling
and
holding
Driving
circuit
Vin
Current
sensor
Voltage
sensor
TMS320F2812 DSP chip
Fig.4 Block diagram of converter system
Both voltage digital regulator and current digital regulator
use PID control strategy in this system.
A. Algorithm of digital PID regulator
The common expression of the PID regulator can be
expressed as:
1
p D
I
de
u K e edt T
T dt
| |
= + +
|
\ .
)
(4)
Where e is error between demand and feedback; K
p
is
proportional coefficient, T
I
is integral time, T
D
is differential
time.
The transfer function can be gotten from (4) using Laplace
transform, and can be expressed as:
1
( ) 1
P D
I
D s K T s
T s
| |
= + +
|
\ .
(5)
Discrete form of (5) can be expressed as:
1
1
( )
k
sp
D
k p k i k k
i I sp
T
T
u K e e e e
T T

=
(
= + +
(
(

_
(6)
And (6) can be simplified as:
1
( )
k p k k D k k
u K e I K e e

= + + (7)
In upper equations:
1
1
k
k I i I k
i
I K e K e

=
= +
_
,
sp
I P
I
T
K K
T
=
,
D
D p
sp
T
K K
T
=
; and e
k
is the error at t
k
, T
sp
is sampling cycle, and
K
p
is proportional coefficient, K
I
is integral coefficient, and K
D
is differential coefficient.
V. ANALYSIS OF THE RESULT OF EXPERIMENT
According to theoretical analysis, the parameters of the
experimental circuit are selected as: V
in
=220V, V
o
=48V,
P
o
=480W. The parameters of the converter Q
1
-Q
4
are
MOSFET; f=100kHz; the ratio of T: n=28:12; L
lk
=6uH;
L
ro
=15uH; C
a
=C
b
=4.7uF/630V; C
s1
=C
s2
=220nF/630V;
L
f
=285uH; C
f
=470uF/200V.
Fig.5 shows the ZVS waveforms of Q
2
which is in the
leading leg with full load condition. The upper waveform is V
gs
,
the lower waveform is V
ds
. We can see V
ds
is zero not only
turn-on but also turn-off of the switch, so the power switches in
leading leg have achieved ZVS completely.
Fig.5 ZVS waveform of Q2
Fig.6 shows the ZVS waveforms of Q
3
which in the
lagging leg with full load condition too. The upper waveform
is V
gs
, and the lower waveform is V
ds
. We also can see V
ds
is
zero not only turn-on but also turn-off of the switch, so the
power switches in lagging leg have achieved ZVS completely.
Fig.6 ZVS waveform of Q3
Fig.7 shows the voltage waveforms of the primary. Fig.8
shows the voltage waveforms of the secondary. Two charts
show that the duty loss is very small.
Fig.9 shows the ZVS waveforms of Q
3
at light load(10%
of full load). The upper waveform is V
gs
, and the lower
waveform is V
ds
. So the proposed converter has wide load
ZVS range.
Fig.10 shows that overshoot and oscillation of the
secondary is large without circuit2. It proves that circuit2 can
reduce the voltage overshoot and oscillation of the secondary,
and reduces the voltage stress of the rectified diodes.
8460
Fig.7 Waveform of the primary
Fig.8Waveform of the secondary
Fig.9 ZVS waveform of Q
3
with light load
Fig.10 Waveform of the secondary without circuit2
Fig.11 ripple of output voltage
Fig.11 shows the ripple of the output voltage. We can find
that the ripple is less than 40mV, and the ripple coefficient is
less than 0.1% through calculating. So the voltage output
characteristic of the proposed converter is good.
Fig.12 shows the efficiency of the converter according to
the experimental data. We can see that the efficiency is 94%
with full load and 82% with 10% of full load, so the efficiency
is very high.
Fig.12 efficiency of the converter
VI. CONCLUSION
The proposed novel ZVS PWM DC-DC converter can
achieve ZVS at the frequency of 100kHz. This converter
topology adds two passive circuits on the basis of conventional
FB converter, circuit1 is used to widen ZVS range of the
lagging leg, and circuit2 is used to reduce the voltage
overshoot and oscillation of the secondary voltage. The result
of experiment demonstrated the validity of theoretical analysis,
the efficiency of the converter is very high and the
characteristic of output is good.
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