PLD-Architecture-Guide

Preface
Programmable logic devices (PLDs) are devided into 3 basic architecture types, SPLD, CPLD and FPGA. At the first glance it seems to be very confusing, cause of the vast amount of names like GAL, PLA, EPLD ... and so on. The reason therefore was the fast progress in history of programmable logic devices and the naming strategy of the PLD-vendors.

The first kind of programmable logic was an standard EPROM used as a Look-Up-Table (LUT). The EPROM address-port was used for the input signals and the EPROM data-port forced the output-signals. Signetics Corporation developed in 1975 a programmable device called "Field Programmable Logic Array" (FPLA) for glue-logic replacement. But both devices (EPROM and FPLA) have a common difference to a real programmable logic device, and that is the missing sequential logic, like a flip-flop, to create synchronous designs or statemachines.

PLD architecture tree

SPLD-architecture (SimplePLD-architecture, also known as PAL-architecture)

In 1978 the first real PLD was developed by Monolitic Memories Inc. (MMI) called as "Programmable Array Logic" (PAL). Thi was the first kind of PLD-architecture. A SPLD-architecture based device consists of two or more vendor-specific macrocells to realize the logic functions. The PLDs in the following years were all based on this architecture type with some improvements, of course.

Significant characteristics for the SPLD-architecture : one macrocell per output minimum two macrocells per device typically all macrocells identical one product term per macrocell product term typically generated by a AND-matrix and OR-matrix minimum one matrix (AND/OR) programmable dedicated flip-flop (FF) per macrocell Typical vendor-specific names for PLDs with SPLD-architecture : PAL (Programmable Array Logic) GAL (Generic Array Logic) PLA (Programmable Logic Array) Main-advantages : predictable timing easy to develop Main-disadvantages : inefficient resource utilization only for simple logic functions Important note: Devices with SPLD-architecture are often called "PLD", but "PLD" is normally used for all kinds of programmable logic devices. The abbreviation "SPLD" is also used for some vendor specific "CPLDs" (Complex PLDs) as "Segmented PLD" !

CPLD-architecture (ComplexPLD-architecture)

To reach more complexity, the logical consequence of the SPLD-architecture was the CPLD-architecture. A "complex programmable logic device" (CPLD) contains many SPLD-like (PAL-like) devices interconnected via a programmable switch matrix. The SPLD-like devices were called logic-blocks, which contain many SPLD-like macrocells. Some PLD-vendors developed their own logic-block or switch-matrix architecture and gave them vendor-specific names.

Significant characteristics for the CPLD-architecture : product terms generated in programmable macrocells typically one dedicated flip-flop per macrocell many macrocells per logic-block typically all logic-blocks identical minimum two logic-blocks per device routing between logic-blocks via global switch matrix Typical vendor-specific names for PLDs with CPLD-architecture : CPLD (Complex Programmable Logic Device) EPLD (Electrical Programmable Logic Device) EPLD (Erasable Programmable Logic Device) EEPLD (Electrically-Erasable Programmable Logic Device) SPLD (Segmented Programmable Logic Device) XPLD (eXpanded Programmable Logic Device) Main-advantages : predictable timing fast pin-to-pin delay efficient resource utilization by switch-matrix medium design complexities possible Main-disadvantages : higher complexities need a very complex (expensive) switch-matrix

FPGA-architecture

To reach very high complexities the channel-based routing strategy was forced instead of the CPLD switch-matrix strategy The FPGA-architecture consists of many logic-modules, which are placed in an array-structure. The channels between the logic-modules are used for routing. The array of logic-modules is surrounded by programmable I/O-modules and connected via programmable interconnects. This freedom of routing allows every logic-module to reach every other logic-module or I/O-module. The worldwide first PLD with FPGA-architecture was developed by Xilinx in 1984. There are two FPGA architecture subclasses, depending on the granularity of the logic-modules. Coarse-grained and finegrained FPGAs. The coarse-grained FPGAs have very large logic-modules with sometimes two or more sequential logic elements, and the fine-grained have very simple logic-modules. The FPGA-architecture offers the highest programmable logic capacity.

Significant characteristics for the FPGA-architecture : array of logic-modules different logic-modules possible distinction between FPGAs with coarse-grained or fine-grained logic-modules coarse-grained have minimum one combinatorial and one sequential element fine-grained have typically separated combinatorial- and sequential-modules routing-channels physically between logic-modules every logic-module can be interconnected to any other logic-modul or I/O-module Typical vendor-specific names for PLDs with FPGA-architecture : FPGA (Field Programmable Gate Array) LCA (Logic Cell Array) pASIC (programmable ASIC) SPGA (System Programmable Gate Array) XPGA (eXpanded Programmable Gate Array) Main-advantages : efficient resource utilization very high complexities possible high system frequencies possible Main-disadvantages : no predictable timing (some exceptions) 100% interconnect is very expensive good CAE-tools for FPGA-development strongly recommended