University of Notre Dame CSE/EE 40462/60462, Fall 2013

VLSI Circuit Design

Lecture 11 1st October 2013
Ismo Hnninen
(Visiting Assistant Professor, Dr. Tech.) Department of Electrical Engineering University of Notre Dame, USA Room: Cushing 227A Tel: +1 574 631 0996 Cel: +1 574 386 4761 Email: ismo.hanninen@nd.edu

University of Notre Dame, CSE/EE 40462/60462

VLSI Circuit Design, Outline

29 lectures in 15 weeks (27th Aug. 12th Dec. 2013)

Course Wk 1 2 3 4 5 6 7

Lecture L1: Overview L2: Physics & Semiconductor Devices L3: CMOS Circuits #1 L4: CMOS Circuits #2 L5: MOS Transistor Theory L6: MOSFET Circuits L7: MOSFET Real World Effects L8: Basic CMOS Fabrication Process L9: CMOS Layout Design & Design Rules L10: Standard Cells & Stick Figure Layouts L11: Layouts & Simulation L12: Review for EXAM 1/3 L13: Verilog #1

Homework H0: Pre-course knowledge quiz (due wk 2 Monday before noon) H1: Basic CMOS Transistor Circuits (due wk 3 Tuesday) H2: MOSFET Theory & Modeling (due wk 4 Tuesday) H3: Circuit Level Simulation Using SPICE (due wk 6 Tuesday) H4: Fabrication & Layouts (due wk 6 Tuesday)
H5: Semiconductor Layout Tools (due wk 7 Thursday) EXAM 1/3 handout (due wk 7 Tuesday) H5: Verilog (due wk 8 Tuesday)

CSE/EE 40462/60462 VLSI Circuit Design, Ismo Hnninen

11. CMOS Layout Design 3

VLSI DESIGN
Ismo Hnninen University of Notre Dame Fall 2013 Based on material from Profs. Peter Kogge, Joseph Nahas, Jay Brockman, University of Notre Dame And Prof. David Harris, Harvey Mudd College http://www.cmosvlsi.com/coursematerials.html
Slide 3 VLSI Circuit Design, 11. CMOS Layout Design 3

Outline
Review
Design Rules Layout Styles Standard Cell Layouts

Stick Diagrams Euler Paths Wiring Tracks and Spacing's Area Estimation Semiconductor Layout Tools

Slide 4

VLSI Circuit Design, 11. CMOS Layout Design 3

A Simplified Rule System

RULES

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VLSI Circuit Design, 11. CMOS Layout Design 3

Rules
A simplified, technology generations independent design rule system Express rules in terms of
Called Lambda rules

= f/2

E.g. = 0.3 mm in 0.6 mm process

Lambda rules are NOT used in commercial applications

Lambda rules need to be very conservative and thus waste space

Lambda rules are good for education!

MOSIS SCMOS SUMB Rules See Book Front Inside Cover

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VLSI Circuit Design, 11. CMOS Layout Design 3

Simplified Design Rules

Conservative rules to get you started (W&H Fig. 1.39)
Missing Rule: Poly to Dif Contact

http:// http://www3.nd.edu/~cse/2013fa/40462/links.html Slide 7 VLSI Circuit Design, 11. CMOS Layout Design 3

Transistor Width and Length

Dimensions of Gate Overlap over Source/Drain Diffusion = Active area of a transistor

Transistor Width W Perpendicular to traveling direction of carriers

Transistor Length L Parallel to traveling direction of carriers

Typically Width >> Length

Slide 8 VLSI Circuit Design, 11. CMOS Layout Design 3

Layout Styles

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VLSI Circuit Design, 11. CMOS Layout Design 3

Layout Styles
Custom
Random transistor and other component positioning and wiring

Standard Cell
Logic gates pre-designed Power rails (Vdd and Vss) on top and bottom Common N and P wells PMOS transistors on top NMOS transistors on bottom Gates wired together automatically using Place and Route Tool

Pitch-Matched Data Path

Custom or automatic layout of logic in data channels Typically 8, 16, 32, or 64 bits wide. Channels match each other and mesh (Memory will be discussed later)
Slide 10 VLSI Circuit Design, 11. CMOS Layout Design 3

Stick Diagrams
Stick diagrams help plan layout quickly
Need not be to scale Draw with color pencils or dry-erase markers Relative position of key components

What type of gates are these? What are the widths of the nmos and pmos transistors?
Slide 11 VLSI Circuit Design, 11. CMOS Layout Design 3

Repetitive Custom Layout of Ring Oscillator

Vdd

X
X

X X

X X

X X

X
X

X
Gnd

X
Slide 12

X
VLSI Circuit Design, 11. CMOS Layout Design 3

Standard Cell Layout

RE-USING CELLS

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VLSI Circuit Design, 11. CMOS Layout Design 3

Gate Layout
Layout can be very time consuming Reducing this time can be expedited if you
Build a library of standard cells Design gates to fit together nicely

Standard cell design methodology

VDD and GND should be some standard height & parallel Within cell, all pMOS in top half and all nMOS in bottom half Preferred practice: diffusion for all transistors in a row (poly vertical) All gates include well and substrate contacts

Multi-gate circuits constructed by snapping gates together

If two standard cells abut, Vdd & GND snap together Adjacent gates must still satisfy design rules at boundaries

Bigger circuits constructed by rows of such multi-gates

With routing channels between them for wiring (typically 2 metal levels)
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Inverter Layout
NOT to scale!

In

Out

What is the width of the nmos and pmos transistors? Why? What happens to size of inverter if we want to change widths?
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NAND Gate Layouts

B Out A N B

Audience Question: Why is rightmost preferred?

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Inside A Modern Standard Cell

Have Diffusion running horizontally
P type below the Vdd bus N type above the GND VDD Bus N Well PMOS Transistors
Internal Gate Wiring And Gate I/O contacts

Have Poly running vertically Use metal to appropriately wire diffusions

To Vdd & Gnd To the other diffusion To different points in current diffusion

NMOS Transistors P Well VSS Bus

Attach I/O contacts to metal

Question to be answered by later Euler Path algorithm: Can we draw diffusion as single long rectangles without gaps?
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A Simple Standard Cell Library

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VLSI Circuit Design, 11. CMOS Layout Design 3

More Complex Gates

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VLSI Circuit Design, 11. CMOS Layout Design 3

Pitch-Matching (Fig. 1.65)

Would it help if: A could be slightly shorter?

C could be slightly narrower?

D could be smaller?

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VLSI Circuit Design, 11. CMOS Layout Design 3

What If We Want to Stack Gates?

Vdd Vdd Vdd Vdd

Gnd

Gnd

Gnd

Gnd

Design Rule says what?

Vdd

Vdd

Gnd

But what if we flip one row?

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VLSI Circuit Design, 11. CMOS Layout Design 3

MIPS ALU & Data Flow via Standard Cells

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VLSI Circuit Design, 11. CMOS Layout Design 3

Now for the Full 8 Bit Data Flow

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VLSI Circuit Design, 11. CMOS Layout Design 3

What If We Cant Use the Internal Wiring Channels?

Wiring Channel

Wiring Channel

Audience Questions: 1. How many levels of metal do we need for this? 2. How would you estimate the height of the wiring channels? 3. Why is deciding which logic gate standard cell goes where important?

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VLSI Circuit Design, 11. CMOS Layout Design 3

A Fully Synthesized 8-bit MIPS

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VLSI Circuit Design, 11. CMOS Layout Design 3

Single Diffusion Stick Diagrams

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VLSI Circuit Design, 11. CMOS Layout Design 3

4-Input NAND Gate Sticks Layout

Complementary transistor pairs share common gate connection. Step 1: order gates

OUT I1 I2 I3 I4

Step 2: interconnect

If pmos are 8/2, what are the nmos transistors?

Slide 27 VLSI Circuit Design, 11. CMOS Layout Design 3

Euler Paths
We start off with
Diffusion as one row, no breaks! Poly runs vertically

Thus each transistor must touch electrically ones next to it Question:

How can we order the relationship between poly and input? Touching must match the desired transistor diagram Metal may optionally be used

Approach:
Start with some transistor & trace path through rest of that type May require trial and error, and/or rearrangement

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VLSI Circuit Design, 11. CMOS Layout Design 3

Finding Gate Ordering: Euler Paths

See if you can trace transistor gates in same order, crossing each gate once, for N and P networks independently
Where tracing means path from source/drain of one to source/drain of next Without jumping connections

ABCD works here

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VLSI Circuit Design, 11. CMOS Layout Design 3

A More Complex Example

A (B+C) + DE

E Y P

See if you can trace transistor gates in same order, crossing each gate once, for N and P networks independently
Where tracing means a path from source/drain of one to source/drain of next

B X P C O U T A X N B C E D Y N A

Without jumping
ordering CBADE works for N, not P ordering CBDEA works for P, not N ordering BCADE works for both!

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VLSI Circuit Design, 11. CMOS Layout Design 3

A More Complex Example

A (B+C) + DE
Trace interconnected gates in SAME order, crossing each gate once, for N,P networks ordering CBADE works for N, not P ordering CBDEA works for P, not N ordering BCADE works for both!

E Y P

B X P C O U T A X N B C E D Y N A

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VLSI Circuit Design, 11. CMOS Layout Design 3

Sticks Layout
A (B+C) + DE

E Y P

B X P C O U T A X N B C E D Y N A

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VLSI Circuit Design, 11. CMOS Layout Design 3

Wiring Tracks, Spacing and Area Estimation

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VLSI Circuit Design, 11. CMOS Layout Design 3

Review: Wiring Tracks

A wiring track is the space required for a wire
4 width, 4 spacing from neighbor = 8 pitch

Transistors also consume one wiring track (WHY?)

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VLSI Circuit Design, 11. CMOS Layout Design 3

Review: Well spacing

Wells must surround transistors by 6
Implies minimum of 12 between opposite transistor flavors Leaves room for one wire track for free

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VLSI Circuit Design, 11. CMOS Layout Design 3

First Cut Area Estimation

Estimate area by counting required metal wiring tracks
Multiply by 8 to express in Where does the 8 come from?

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VLSI Circuit Design, 11. CMOS Layout Design 3

Example: NAND3
Horizontal n-active and p-active strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND/VSS rail at bottom 32 by 40

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VLSI Circuit Design, 11. CMOS Layout Design 3

Example: O3AI
Sketch a stick diagram for O3AI and estimate area

( A B C)D

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VLSI Circuit Design, 11. CMOS Layout Design 3

Example: O3AI
Sketch a stick diagram for O3AI and estimate area

( A B C)D

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VLSI Circuit Design, 11. CMOS Layout Design 3

Example: O3AI
Sketch a stick diagram for O3AI and estimate area

( A B C)D

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VLSI Circuit Design, 11. CMOS Layout Design 3

Another Example
Consider F= ~((A+B) (C+D))
Sketch transistors Sketch stick diagram Estimate area

(H&W Question 1.17)

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Typical Layout Densities

Element Random Logic Datapath SRAM DRAM ROM

Area (in

2)

1000-1500/transistor 250-750/transistor 1000/bit 100/bit 100/bit

(H&W Table 1.10)

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VLSI Circuit Design, 11. CMOS Layout Design 3

Semiconductor Layout Tools

CADENCE DESIGN ENVIRONMENT

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VLSI Circuit Design, 11. CMOS Layout Design 3

Layout Tools
Drawing, Analyzing, and Verifying Circuit Layouts CAD-tools are necessary for practical layout work
Cadence Design Systems is one of the major Electronic Design Automation companies

We use Cadence Virtuoso Front to Back Design Environment (icfb)

Large software suite for layout, schematic, simulation, synthesis Linux/Unix machines, remote access using Xming and tunneling preferred Set up using instructions in homework H5*

The homework H5 assignments in nutshell:

AMI 0.6 m process technology, follow MOSIS SCMOS SUBM rules ( = 0.3 m) Layout NMOS transistor cell and run Design Rule Check (DRC) Layout PMOS transistor cell and run DRC Layout CMOS Inverter using your new cells and run DRC Run Layout Versus Schematic (LVS) check on your CMOS Inverter Layout 3-Stage Ring Oscillator and run DRC
Slide 44 VLSI Circuit Design, 11. CMOS Layout Design 3