ASIC

DESIGN
M.E.[EC] SEMESTER-I
Subject Code :- 710403
(GTU)
Prepared by:
Mr. Amish J. Tankariya
INTRODUCTION:
An ASIC (a-sick) is an application-specific
integrated circuit
History of integration:
Small-scale integration (SSI, ~10 gates per chip, 60s)
Medium-scale integration (MSI, ~1001000 gates per chip,
70s)
Large-scale integration (LSI, ~100010,000 gates per chip,
80s)
Very large-scale integration (VLSI, ~10,000100,000 gates
Mr. Amish J. Tankariya
Very large-scale integration (VLSI, ~10,000100,000 gates
per chip, 90s)
Ultra-large scale integration (ULSI, ~1M10M gates per
chip)
History of technology:
Bipolar technology and transistortransistor logic (TTL)
preceded ...
Metal-oxide-silicon (MOS) (nmos or NMOS)
The introduction of complementary MOS (CMOS) greatly
reduced power 2
CONTINUE....
Generally, Size of IC is measured by no of logic gates (Transistors). A
unit of measure is gate equivalent is a NAND gate F = (A B),
or four transistors
Example: 100k gate IC => 1,00,000 two input NAND gates
The another measure of the IC feature size is the smallest shape
you can make on a chip and is measured in or lambda.
(since lambda is equal to half of the smallest transistor length,
=0.25 um in a 0.5 um process.)
Mr. Amish J. Tankariya
=0.25 um in a 0.5 um process.)
Origin of ASICs:
Standard parts - initially used to design microelectronic systems
Gradually replaced with a combination of glue logic (remaining logic
functions), custom ICs, dynamic random-access memory (DRAM)
and static RAM(SRAM)
History of ASICs: The IEEE Custom Integrated Circuits
Conference (CICC) and IEEE Inter-national ASIC Conference
document the development of ASICs
3
CLASSIFICATION OF VLSI DESIGN AT
DIFFERENT LEVEL:
Front End (Coding) (Results)
Back End (Schematics of RTL)
(No parasitic Extraction)
Physical End (Layouts)
Mr. Amish J. Tankariya
(Parasitic Extraction)
4
Mr. Amish J. Tankariya
5
Y- CHART
Mr. Amish J. Tankariya
6
ASIC DESIGN FLOW
S-1 Design Entry: Schematic entry
or HDL description
S-2: Logic Synthesis: Using
Verilog HDL or VHDL and Synthesis
tool, produce a netlist-logic cells
and their interconnect detail
S-3 System Partitioning: Divide a
large system into ASIC sized pieces
S-4 Pre-Layout Simulation: Check
design functionality
Mr. Amish J. Tankariya
design functionality
S-5 Floorplanning: Arrange netlist
blocks on the chip.
S-6 Placement: Decide the
locations in a block
S-7 Routing: Make the cell and
block interconnections
S-8 Extraction: Measure the
interconnect R/C cost
S-9 Post-Layout Simulation :
Check to see the design still works
with the added load of the
interconnect.
7
CLASSIFICATION
Mr. Amish J. Tankariya
8
ASIC ASIC VS VS SSTANDARD TANDARD IC IC
o Standard ICs ICs sold as Standard Parts SSI/LSI/ MSI IC
such as MUX, Encoder, Memory Chips, or Microprocessor IC
(NOT ASIC)
o Application Specific Integrated Circuits (ASIC) A Chip for
Toy Bear, Auto-Mobile Control Chip, Different Communication
Chips [ICs not Found in Data Book]
Concept Started in 1980s
Mr. Amish J. Tankariya
o Concept Started in 1980s
o An IC Customized to a Particular System or Application
CustomICs
o Digital Designs Became a Matter of Placing of Fewer CICs or
ICs plus Some Glue Logic
o Reduced Cost and Improved Reliability
o Application Specific Standard Parts (ASSP) Controller
Chip for PC or a Modem
9
SSTANDARD TANDARD IC: IC:
oOlder generation IC technology such as TTL ICs could often
require to interconnect 5 to 15 ICs.
oThe wiring would often be very complex and messy.
Mr. Amish J. Tankariya
10
Example of system Design using standard ICs Example of system Design using standard ICs
PROGRAMMABLE
LOGIC
Mr. Amish J. Tankariya
LOGIC
DEVICES
WHY PROGRAMMABLE LOGIC?
Facts:
It is most economical to produce an IC in large
volumes
Many designs required only small volumes of ICs
Need an IC that can be:
Produced in large volumes
Mr. Amish J. Tankariya
Produced in large volumes
Handle many designs required in small volumes
A programmable logic part can be:
Made in large volumes
Programmed to implement large numbers of
different low-volume designs
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Many programmable logic devices are field-
programmable, i. e., can be programmed outside of
the manufacturing environment
Most programmable logic devices are erasable and
reprogrammable.
Allows updating a device or correction of errors
PROGRAMMABLE LOGIC - ADDITIONAL ADVANTAGES
Mr. Amish J. Tankariya
Allows updating a device or correction of errors
Allows reuse the device for a different design - the
ultimate in re-usability!
Ideal for course laboratories
13
WHAT IS PROGRAMMABLE LOGIC?
In the world of digital electronic systems, there are three
basic kinds of devices:
Memory: store random information such as the contents
of a spreadsheet or database.
Microprocessors : execute software instructions to
Mr. Amish J. Tankariya
Microprocessors : execute software instructions to
perform a wide variety of tasks such as running a word
processing program or video game.
Logic : Logic devices provide specific functions, including
device-to-device interfacing, data communication, signal
processing, data display, timing and control operations,
and almost every other function.
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FIXED LOGIC V/S PROGRAMMABLE LOGIC
Logic devices can be classified into two broad categories.
Fixed : the circuits in a fixed logic device are permanent,
they perform one function or set of functions - once
manufactured, they cannot be changed.
Mr. Amish J. Tankariya
Programmable : programmable logic devices (PLDs) are
standard, off-the-shelf parts that offer customers a wide
range of logic capacity, features, speed, and voltage
characteristics - and these devices can be changed at any
time to perform any number of functions.
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FIXED LOGIC
The time required to go from design, to prototypes, to a
final manufacturing run can take from several months to
more than a year, depending on the complexity of the
device.
If the device does not work properly, or if the requirements
change, a new design must be developed.
The up-front work of designing and verifying fixed logic
Mr. Amish J. Tankariya
The up-front work of designing and verifying fixed logic
devices involves substantial "non-recurring engineering"
costs, or NRE.
NRE represents all the costs customers incur before the
final fixed logic device emerges from a silicon foundry,
including engineering resources, expensive software design
tools, expensive photolithography mask sets for
manufacturing the various metal layers of the chip, and the
cost of initial prototype devices.
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PROGRAMMABLE LOGIC DEVICE
With PLDs designers use inexpensive software tools to quickly
develop, simulate, and test their designs.
Design can be quickly programmed into a device, and
immediately tested in a live circuit.
There are no NRE costs and the final design is completed much
Mr. Amish J. Tankariya
There are no NRE costs and the final design is completed much
faster than that of a custom, fixed logic device.
During the design phase customers can change the circuitry as
often as they want until the design operates to their satisfaction.
Once the design is final, customers can go into immediate
production by simply programming as many PLDs as they
need with the final software design file.
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PLD ADVANTAGES
PLDs offer customers much more flexibility during the design cycle because design
iterations are simply a matter of changing the programming file, and the results of design
changes can be seen immediately in working parts.
Low development cost
Less space requirement
Fast Design Time
Less power requirement
High reliability
Mr. Amish J. Tankariya
High reliability
Easy circuit testing
Easy design modification
Less design time
PLDs do not require long lead times for prototypes or production parts
PLDs do not require customers to pay for large NRE costs and purchase expensive mask
sets
PLDs can be reprogrammed even after a piece of equipment is shipped to a customer.
In fact, thanks to programmable logic devices, a number of equipment manufacturers
now have the ability to add new features or upgrade products that already are in the field.
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WHO MAKES PLDS ?
Mr. Amish J. Tankariya
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SOME DEFINITIONS
Programmable Logic - a logic element whose
function is not restricted to a particular function. It
may be programmed at different points of the life
cycle. It is programmed by the semiconductor vendor,
by the designer prior to assembly, or by the user, in
Mr. Amish J. Tankariya
by the designer prior to assembly, or by the user, in
circuit.
Gate Array - Transistors or gates are fabricated in a
2 dimensional array on a die to form the standard
base of an application specific integrated circuit. The
devices is programmed by custom metal layers
interconnecting nodes in the array.
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SOME DEFINITIONS
Standard Cell - This device differs from the gate
array since each cell may be different and
optimized for each "standard" function. There are
no standard layers to the device and each layer of
the chip is a unique design.
Mr. Amish J. Tankariya
the chip is a unique design.
Programmable Read Only Memory (PROM) -
This device has a fixed, fully decoded AND plane
and a programmable OR plane. The programmable
element for these devices include EPROM,
EEPROM, fuses and antifuses.
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SOME DEFINITIONS
Programmable Array Logic (PAL) - This device
has a programmable AND plane and a fixed OR
plane. Device uses an amorphous silicon antifuse as
the programmable element. These are often
referred to as Simple Programmable Logic
Devices (SPLDs).
Mr. Amish J. Tankariya
Devices (SPLDs).
Programmable Logic Array (PLA) - This device
has both programmable AND and OR planes. PLA
structures may also appear as part of some CPLDs.
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PROGRAMMABLE LOGIC DEVICES
(WITH DIFFERENT VIEWPOINT)
Programmable Arrays
OR Array
AND Array
Classifications of Simple Programmable Logic Devices (SPLD)
Read-Only Memory (ROM)
Mr. Amish J. Tankariya
Read-Only Memory (ROM)
Programmable Array Logic (PAL)
Programmable Logic Array (PLA)
Generic Array Logic (GAL)
More complex
FPGA (field programmable gate arrays)
CPLD (Complex Programmable Logic Devices) 23
OR ARRAY
Mr. Amish J. Tankariya
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AND ARRAY
Mr. Amish J. Tankariya
25
READ
ONLY
MEMORY: MEMORY:
(ROM)
READ ONLY MEMORY:
Consists of an array of semiconductor devices interconnected to
store an array of binary data.
Cant be changed once burned in.
Conceptually, consist of a decoder and a memory array.
ROM Types
Mr. Amish J. Tankariya
Mask programmable ROM
fuses programmed during manufacture
Programmable ROM (PROM)
0s programmed by blowing fuses or burning
Erasable PROM (EPROM)
programming erased by UV light
Electrically erasable PROM (EEPROM)
programming erased via control signals
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Example: A 8 X 4 ROM ( 2
N
xM ROM)
(N = 3 input lines, M= 4 output lines)
In general, a 2
N
xM ROMwill have
an internal Nx 2
N
decoder and
M OR gates, each with 2
N
input.
The fixed "AND" array is a
decoder with 3 inputs and 8
READ ONLY MEMORY EXAMPLE
D7
D6
D5
D4
D3
A2
X X X
X
X
X
X
Mr. Amish J. Tankariya
decoder with 3 inputs and 8
outputs implementing minterms.
The programmable "OR
array uses a single line to
represent all inputs to an
OR gate.
An x in the array corresponds
to attaching the mintermto the OR
Read Example: For input (A
2
, A
1
, A
0
)
= 001, output is (F
3
,F
2
,F
1
,F
0
) = 0011.
D3
D2
D1
D0
A2
A1
A0
F
0
F
1
F
2
F
3
X
X
X
X
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PROGRAMMABLE READ-ONLY MEMORY
(PROM)
Mr. Amish J. Tankariya
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PROMS
Input: k Address lines (A)
Output: d Data lines (D)
Function:
Each possible value of A [0..(2^k)-1] has a unique set of d bits
that are output on D when the corresponding address is
provided on A
A0
0
1
Mr. Amish J. Tankariya
Decoder
A0
A1
A2
Ak-1
D0 D1 Dd-1
fuses
0
1
2
(2^k)-1
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What are functions F
3
, F
2
, F
1
and F
0
in terms of (A
2
, A
1
, A
0
)?
PROM EXAMPLE:
D7
D6
D5
D4
D3
D2
A2 A
X X X
X
X
X
X
Mr. Amish J. Tankariya
F
3
= D
7
+ D
5
+ D
2
= A
2
A
0
+ A
2
A
1
A
0

F
2
= D
7
+ D
0
= A
2
A
1
A
0
+ A
2
A
1
A
0

F
1
= D
4
+ D
1
= A
2
A
1
A
0
+ A
2
A
1
A
0
F
0
= D
7
+ D
5
+ D
1
= A
2
A
0
+ A
1
A
0
D2
D1
D0
A2
A1
A0
A
B
C
F
0
F
1
F
2
F
3
X
X
X
X
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EXAMPLE:
Problem: Tabulate the truth for an 8 X 4 ROM that implements the
following four Boolean functions:
A(X,Y,Z) = m(3,6,7);
B(X,Y,Z) = m(0,1,4,5,6)
C(X,Y,Z) = m(2,3,4);
D(X,Y,Z) = m(2,3,4,7)
Solution:
Mr. Amish J. Tankariya
Inputs Outputs
X Y Z A B C D
0 0 0 0 1 0 0
0 0 1 0 1 0 0
0 1 0 0 0 1 1
0 1 1 1 0 1 1
1 0 0 0 1 1 1
1 0 1 0 1 0 0
1 1 0 1 1 0 0
1 1 1 1 0 0 1
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IMPLEMENTATION USING 8X4 ROM.
0
1
2
Z
3-to-8
X
X
X X
Mr. Amish J. Tankariya
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2
3
A B
C D
Z
Y
X
3-to-8
Decoder
4
5
6
7
X
X
X
X
X
X
X X
X
IMPLEMENTING LOGIC IN PROMS
A B F1 F2 F3
Mr. Amish J. Tankariya
F1=A+B
F2=AB
F1=AB+AB
0
0
1
1
0
1
0
1
1
1
0
1
0
0
1
0
0
1
1
0
F1=D0+D1+D3
F2=D2
F1=D1+D2
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D3
A
X
IMPLEMENTING LOGIC IN PROMS
X
F1=D0+D1+D3
F2=D2
F1=D1+D2
4 X 3 ROM ( 2
2
x3 ROM)
2-to-4
Decoder
Mr. Amish J. Tankariya
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D2
D1
D0
A
B
F
0
F
1
F
2
X
X
X
X
X
EXAMPLE: 2: USING 8X6 ROM, IMPLEMENT DESIGN THAT
GENERATES SQUARE OF INPUT, AT THE OUTPUT.
Design a square lookup table for F(X) = X F(X) = X
2 2
using ROM
Mr. Amish J. Tankariya
Inputs Outputs
X2 X1 X0 SQ F5 F4 F3 F2 F1 F0
0 0 0 0 0 0 0 0 0 0
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0 0 0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0 0 1
0 1 0 4 0 0 0 1 0 0
0 1 1 9 0 0 1 0 0 1
1 0 0 16 0 1 0 0 0 0
1 0 1 25 0 1 1 0 0 1
1 1 0 36 1 0 0 1 0 0
1 1 1 49 1 1 0 0 0 1
0
1
2
X2
3-to-8
Mr. Amish J. Tankariya
F5=D6+D7
F4=D4+D5+D7
F3=D3+D5
F2=D2+D6
F1=0
F0=D1+D3+D5+D7
2
3
F5 F4 F3 F2
F1 F0
X2
X1
X0
3-to-8
Decoder
4
5
6
7
37
0
1
2
3
X2
X1
3-to-8
Decoder
4
Mr. Amish J. Tankariya
Lets think something more ahead........
Ready??
= X0 = X0
Effectively Effectively
Not Not Used Used
F5 F4 F3 F2
F1 F0
X1
X0
Decoder
4
5
6
7
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0
1
2
3
X2
X1
3-to-8
Decoder
Mr. Amish J. Tankariya
3
F5 F4 F3 F2
F0
X1
X0
Decoder
4
5
6
7
F1
39
Using 8x2 ROM, Implement Full
adder logic Design.
Using 8x2 ROM, Implement Full
EXERCISE:
Mr. Amish J. Tankariya
40
Using 8x2 ROM, Implement Full
Subtraction logic Design.
Using ROM, Implement the logic
design that generates gray code for
given 4 bit binary input.
PROGRAMMABLE
ARRAY
LLOGIC
(PAL)
PROGRAMMABLE ARRAY LOGIC (PAL)
The PAL is the opposite of the ROM, having a programmable
set of ANDs combined with fixed ORs.
Disadvantage
NxM ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.
Advantages
For given internal complexity, a PAL can have larger N and M
Mr. Amish J. Tankariya
For given internal complexity, a PAL can have larger N and M
Some PALs have outputs that can be complemented, adding
POS functions
No multilevel circuit implementations in ROM (without external
connections from output to input).PAL has outputs from OR
terms as internal inputs to all AND terms, making
implementation of multi-level circuits easier.
42
PROGRAMMABLE ARRAY LOGIC: (PAL)
Basic PAL configuration is the same as a PLA
The number of AND gates fed to each OR gate is fixed
AND terms are not shared by OR gates
Special case of PLA
AND is programmable
Mr. Amish J. Tankariya
AND is programmable
OR is fixed
Less expensive than PLA
Easier to program
Less flexibility
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PROGRAMMABLE ARRAY LOGIC (PAL)
Mr. Amish J. Tankariya
It was developed to overcome certain disadvantages of PLA, such as longer
delays due to the additional fusible links that result from using two
programmable arrays and more difficult complexity.
The PAL is most common one-time programmable (OTP) logic device and is
implemented with bipolar technology (TTL or ECL)
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PROGRAMMABLE ARRAY LOGIC
Mr. Amish J. Tankariya
Basic structure of PAL
PAL implementation of SOP form
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PAL:
Each PAL input must drive many AND gates
Buffers must be used
An unprogrammed segment
Mr. Amish J. Tankariya
Notation:
46
PAL REPRESENTATION
Mr. Amish J. Tankariya
Standard PAL representation
47
PAL IMPLEMENTATION:
Mr. Amish J. Tankariya
Example of Any Random Design:???????????
(Dont waste your time in analyzing the design type)
48
PAL IMPLEMENTATION:
Mr. Amish J. Tankariya
49
SOLVE THE EXAMPLE:
Illustrate the simultaneous PAL Implementation of
below 3 function:
A) fa (A,B,C,D)= m(0,2,7,10) + d(12,13)
B) fb (A,B,C,D)= m(2,4,5) + d(6,7,8,10)
C) fc (A,B,C,D)= m(2,7,8) + d(0,13)
Mr. Amish J. Tankariya
C) fc (A,B,C,D)= m(2,7,8) + d(0,13)
A)
B)
C)
Ans: F1= ABC+BCD+ABC
F2= ACD+BCD+ABD+ABC
F3= ACD+ABC+ABCD
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SOLUTION:
Result of the above 3 function
Is as below
Mr. Amish J. Tankariya
51
PAL DEVICE
A
IO1
IO1 IO1
B B A A
IO1 IO2
Programmable
AND Plane
Mr. Amish J. Tankariya
B
IO2
Fixed
OR Plane
52
PAL DEVICE DESIGN EXAMPLE
A
IO1
IO1 IO1
B B A A D D C C
Not
programmed
Mr. Amish J. Tankariya
B
IO2
D C B A D C A IO1 IO2
D C B A D C A D C B A C AB IO2
D C B A C AB IO1
+ + =
+ + + =
+ =
Reused
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PROGRAMMABLE ARRAY LOGIC
EXAMPLE
4-input, 4-output PAL
with fixed, 3-input
OR terms
What are the
equations for F
1
through F ?
Mr. Amish J. Tankariya
through F
3
?
54
FIG SHOW THE TYPICAL PAL
STRUCTURE. WITH 16 INPUTS
AND 8 OUTPUT.
PAL:P16H8
Mr. Amish J. Tankariya
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PROGRAMMABLE
LOGIC
AARRAY
(PLA)
PROGRAMMABLE LOGIC ARRAY (PLA)
Mr. Amish J. Tankariya
PLA Programmable Logic Array (PLA) is a relatively small FPD
that contains two levels of logic, an AND-plane and an
OR-plane, where both levels are programmable
57
UNPROGRAMMED PLA
Mr. Amish J. Tankariya
58
Programmable AND Plane
Programmable Node
Programmable OR Plane
Un-programmed
PLA STRUCTURE:
Mr. Amish J. Tankariya
X
Y
O1 O2 O3 O4
Connect
Disconnect
X X Y Y
X
Y
XY XY
XY
XY
Un-programmed
59
Programmable AND Plane
Programmable OR Plane
YZ
XZ
PLA PROGRAMMING:
Mr. Amish J. Tankariya
X Y
Z
XY+YZ
? ?
XZ+XYZ
XYZ
XY
60
Consider a PLA with
3 inputs
4 outputs
And implement the following function using it.
PROGRAMMABLE LOGIC ARRAY:
EXAMPLE
Mr. Amish J. Tankariya
F0= AB + AC
F1= AC + B
F2= AB + BC
F3= B + AC
61
STEP:1
F0= AB + AC
F1= AC + B
F2= AB + BC
F3= B + AC
Mr. Amish J. Tankariya
List the Product Terms (5 unique product terms)
AB
AC
B
BC
AC
62
STEP:2
PLA TABLE IMPLEMENTATION:
F0= AB + AC
F1= AC + B
F2= AB + BC
F3= B + AC
Mr. Amish J. Tankariya
63
STEP:3
PLA IMPLEMENTATION:
Mr. Amish J. Tankariya
64
PLA
EXAMPLE:
Input
F
1
= AB+ C
F
2
= AC + BC
F
3
= AB + AC
F
4
= AC + BC + ABC
Mr. Amish J. Tankariya
Product
Input
(Specified) Outputs
Term A B C F
1
F
2
F
3
F
4


AB' 1 0 - 1 0 1 0
C - - 1 1 0 0 0
A'C' 0 - 0 0 1 1 1
BC - 1 1 0 1 0 1
AB'C 1 0 1 0 0 0 1

65
PLA REPRESENTATION
Inputs
AB'
C
C B A
Mr. Amish J. Tankariya
Outputs
A'C'
BC
AB'C
F
1
F
2
F
3
F
4
66
INTERNAL PLA STRUCTURE
+ V
+ V
A B C
A' B' C'
AB'
C
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
Outputs
67
+ V
+ V
A B C
A' B' C'
AB'
C
INTERNAL PLA STRUCTURE
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
Outputs
The AND plane lines get pulled up to +V
68
+ V
+ V
A B C
A' B' C'
AB'
C
Internal PLA Structure
0
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
The AND plane lines stay at +V unless one
of the connected inputs pulls it low.
Outputs
69
+ V
+ V
A B C
A' B' C'
AB'
C
Internal PLA Structure
1
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
The AND plane lines stay at +V unless one
of the connected inputs pulls it low.
Outputs
70
+ V
+ V
A B C
A' B' C'
AB'
C
Internal PLA Structure
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
The OR plane lines get pulled down to Ground
Outputs
71
+ V
+ V
A B C
A' B' C'
AB'
C
Internal PLA Structure
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
The OR plane lines get pulled down to Ground
Outputs
72
+ V
+ V
A B C
A' B' C'
AB'
C
Internal PLA Structure
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
The OR plane lines stay at GND unless one
of the AND plane lines pulls it high.
Outputs
73
+ V
+ V
A B C
A' B' C'
AB'
C
Internal PLA Structure
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
The OR plane lines stay at GND unless one
of the AND plane lines pulls it high.
Outputs
74
+ V
+ V
A B C
A' B' C'
AB'
C
Internal PLA Structure
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
The OR plane lines stay at GND unless one
of the AND plane lines pulls it high.
Outputs
75
+ V
+ V
A B C
A' B' C'
AB'
C
Internal PLA Structure
Inputs
Mr. Amish J. Tankariya
+ V
+ V
+ V
+ V
F
1
F
2
F
3
F
4
A'C'
BC
AB'C
The OR plane lines stay at GND unless one
of the AND plane lines pulls it high.
Outputs
76
ANOTHER PLA EXAMPLE:
Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
in this PLA:
C B A D
8 terms
1 2 3 4
5 6
7 2 8
Mr. Amish J. Tankariya
X Y Z
4 input, 6 AND Plane,
3 OR plan lines
How can we implement 8 product terms with 6 AND plane lines?
77
PLA EXAMPLE
Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
A B
X
A B
Y
A B
Z
Mr. Amish J. Tankariya
A B
X
A B
Y
A B
Z
C D
00 01 11 10
C D
00 01 11 10
C D
00 01 11 10
00 00 00
01 01 01
11 11 11
10 10 10
78
PLA EXAMPLE
Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
A B
X
A B
Y
A B
Z
Mr. Amish J. Tankariya
A B
X
A B
Y
A B
Z
C D
00 01 11 10
C D
00 01 11 10
C D
00 01 11 10
00
1 1 1 1
00 00
01
1
01 01
11
1 1
11 11
10
1 1 1
10 10
79
PLA EXAMPLE
Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
A B
X
A B
Y
A B
Z
Mr. Amish J. Tankariya
A B
X
A B
Y
A B
Z
C D
00 01 11 10
C D
00 01 11 10
C D
00 01 11 10
00
1 1 1 1
00
1 1 1 1
00
01
1
01 01
11
1 1
11
1 1
11
10
1 1 1
10
1 1 1 1
10
80
PLA EXAMPLE
Implement these equations:
X = ABC + BD + ABD + CD
Y = BC + D
Z = CD + BD + ABC
A B
X
A B
Y
A B
Z
Mr. Amish J. Tankariya
A B
X
A B
Y
A B
Z
C D
00 01 11 10
C D
00 01 11 10
C D
00 01 11 10
00
1 1 1 1
00
1 1 1 1
00
1 1
01
1
01 01
11
1 1
11
1 1
11
1 1 1 1
10
1 1 1
10
1 1 1 1
10
1 1 1
81
A B
X
A B
Y
A B
Z
PLA Example
CD is in X and Yand looks useful
Mr. Amish J. Tankariya
A B
X
A B
Y
A B
Z
C D
00 01 11 10
C D
00 01 11 10
C D
00 01 11 10
00
1 1 1 1
00
1 1 1 1
00
1 1
01
1
01 01
11
1 1
11
1 1
11
1 1 1 1
10
1 1 1
10
1 1 1 1
10
1 1 1
82
BD is in all three functions
PLA EXAMPLE
CD is in X and Y and looks useful
A B
X
A B
Y
A B
Z
Mr. Amish J. Tankariya
A B
X
A B
Y
A B
Z
C D
00 01 11 10
C D
00 01 11 10
C D
00 01 11 10
00
1 1 1 1
00
1 1 1 1
00
1 1
01
1
01 01
11
1 1
11
1 1
11
1 1 1 1
10
1 1 1
10
1 1 1 1
10
1 1 1
83
PLA EXAMPLE
CD is in X and Y and looks useful
BD is in all three functions
ABC and ABC cover a lot of minterms
A B
X
A B
Y
A B
Z
Mr. Amish J. Tankariya
A B
X
A B
Y
A B
Z
C D
00 01 11 10
C D
00 01 11 10
C D
00 01 11 10
00
1 1 1 1
00
1 1 1 1
00
1 1
01
1
01 01
11
1 1
11
1 1
11
1 1 1 1
10
1 1 1
10
1 1 1 1
10
1 1 1
84
BD is in all three functions
PLA Example
CD is in X and Yand looks useful
ABC and ABC cover a lot of minterms
A B
X
A B
Y
A B
Z
Mr. Amish J. Tankariya
The only ones left are AB and CD
A B
X
A B
Y
A B
Z
C D
00 01 11 10
C D
00 01 11 10
C D
00 01 11 10
00
1 1 1 1
00
1 1 1 1
00
1 1
01
1
01 01
11
1 1
11
1 1
11
1 1 1 1
10
1 1 1
10
1 1 1 1
10
1 1 1
85
PLA EXAMPLE
X = CD + BD + AB + ABC
Y = CD + BD + ABC + ABC
Z = BD + CD + ABC
A B
X
A B
Y
A B
Z
All of the functions are covered using only 6 product terms
Mr. Amish J. Tankariya
A B
X
A B
Y
A B
Z
C D
00 01 11 10
C D
00 01 11 10
C D
00 01 11 10
00
1 1 1 1
00
1 1 1 1
00
1 1
01
1
01 01
11
1 1
11
1 1
11
1 1 1 1
10
1 1 1
10
1 1 1 1
10
1 1 1
How is this possible?
86
PLA EXAMPLE
X = CD + BD + AB + ABC
Y = CD + BD + ABC + ABC
Z = BD + CD + ABC
Product Input Output
Term
A B C D X Y Z
Mr. Amish J. Tankariya
C'D'
B'D'
AB'
ABC
A'BC
CD
87
PLA EXAMPLE
X = CD + BD + AB + ABC
Y = CD + BD + ABC + ABC
Z = BD + CD + ABC
Product Input Output
Term
A B C D X Y Z
Mr. Amish J. Tankariya
C'D' - - 0 0
B'D' - 0 - 0
AB' 1 0 - -
ABC 1 1 1 -
A'BC 0 1 1 -
CD - - 1 1
88
PLA EXAMPLE
X = CD + BD + AB + ABC
Y = CD + BD + ABC + ABC
Z = BD + CD + ABC
Product Input Output
Term
A B C D X Y Z
Mr. Amish J. Tankariya
C'D' - - 0 0 1 1 0
B'D' - 0 - 0 1 1 1
AB' 1 0 - - 1 0 0
ABC 1 1 1 - 1 1 0
A'BC 0 1 1 - 0 1 1
CD - - 1 1 0 0 1
89
PLA EXAMPLE
X = CD + BD + AB + ABC
Y = CD + BD + ABC + ABC
Z = BD + CD + ABC
Product Input Output
Term A B C D X Y Z
C'D' - - 0 0 1 1 0
B'D' - 0 - 0 1 1 1
AB' 1 0 - - 1 0 0
ABC 1 1 1 - 1 1 0
A'BC 0 1 1 - 0 1 1
CD - - 1 1 0 0 1
C B A D
Mr. Amish J. Tankariya
X Y Z 90
PROGRAMMABLE LOGIC ARRAY:
EXAMPLE
F
1
= AB +BC + AC
F
2
= AB + AB
= (AB + AB)
X
A
B
C
1 X
X
X
A B
Mr. Amish J. Tankariya
5 different
product
Terms
????
Term A B C F1 F2
AB 1 1 -- 1 1
BC -- 1 1 1 --
AC 1 -- 1 1 --
3-input, 2-output PLA
with 4 product terms
1
F
1
F
2
C C B B A A
0
2
3
4
X
X X
X X
X
X
X
X
X
X
A C
B C
A B
Here X-OR is
working as
controlled
inverter
AB 0 1 -- -- 1
91
EXAMPLE FOR PRACTICE:
Realize the following functions using PLA
A) F1= m(0,1,4,6)
F2= m(2,3,4,6,7)
F3= m(0,1,2,6)
F4= m(2,3,5,6,7)
Mr. Amish J. Tankariya
B) F1= m(1,2,4,6)
F2= m(2,6)
F3= m(0,1,6,7)
F4= m(1,2,3,5,7)
C) Write a Program Table to implement BCA to XS-
3 Code Conversion using PLA.
92
Features of PLAs:
PLAs come in various sizes
Typical size is 16 inputs, 32 product terms, 8
outputs
Each AND gate has large fan-in this limits the
number of inputs that can be provided in a PLA
16 inputs 2
16
= possible input combinations; only
Mr. Amish J. Tankariya
16 inputs 2 = possible input combinations; only
32 permitted (since 32 AND gates) in a typical PLA
32 AND terms permitted large fan-in for OR gates
as well
This makes PLAs slower and slightly more
expensive than some alternatives
8 outputs could have shared minterms, but not
required
93
PROGRAMMABLE LOGIC ARRAY (PLA)
Compared to a ROM and a PAL, a PLA is the most flexible
having a programmable set of ANDs combined with a
programmable set of ORs.
Advantages
A PLA can have implementation of large equations than
that of the same size ROMor PAL.
A PLA has all of its product terms connectable to all outputs,
overcoming the problem of PAL of the limited inputs to the
Mr. Amish J. Tankariya
overcoming the problem of PAL of the limited inputs to the
ORs
Some PLAs have outputs that can be complemented, adds POS
functions implementation.
Disadvantage
Expensive to manufacture
Often, the product term count limits the application of a PLA.
Offer somewhat poor speed-performance, due to the two levels of
configurable logic,
94
PLAs are more flexible than PALs since both AND &
OR planes are programmable in PLAs.
Because both AND & OR planes are programmable,
PLAs expensive to fabricate and have large
propagation delay than PAL.
PAL VS PAL
Mr. Amish J. Tankariya
95
propagation delay than PAL.
By using fix OR gates, PALs are cheaper and faster
than PLAs.
PALs usually contain D flip-flops connected to the
outputs of OR gates to implement sequential circuits.
PLAs and PALs are usually referred to as SPLD.
GENERIC ARRAY LOGIC (GAL)
The Generic Array Logic (also known as GAL) device was an innovation
Mr. Amish J. Tankariya
The Generic Array Logic (also known as GAL) device was an innovation
of the PAL and was invented by Lattice Semiconductor.
The GAL was an improvement on the PAL because one device was able
to take the place of many PAL devices or could even have functionality not
covered by the original range.
Its primary benefit was that it was erasable and re-programmable making
design changes easier for engineers.
The differences between GAL and PAL device is that the GAL is
reprogrammable
The GAL is programmable again and again because it uses E
2
CMOS
(electrically erasable CMOS) technology instead of bipolar technology and
fusible links.
96
ROM, PAL AND PLA CONFIGURATIONS
(a) Programmable read-only memory (PROM)
Inputs
Fixed
AND array
(decoder)
Programmable
OR array
Outputs
Programmable
Connections
Programmable Fixed
Programmable
Mr. Amish J. Tankariya
(b) Programmable array logic (PAL) device
Inputs
Programmable
AND array
Fixed
OR array
Outputs
Programmable
Connections
(c) Programmable logic array (PLA) device
Inputs
Programmable
OR array
Outputs
Programmable
Connections
Programmable
Connections
Programmable
AND array
97
SUMMARY:
Mr. Amish J. Tankariya
98
COMPARISON BETWEEN PROM, PAL, PLA
Mr. Amish J. Tankariya
99
PLD PROGRAMMING DEVICES
A DEVICE PROGRAMMER is used to
transfer the Boolean logic pattern into
the programmable device.
In the early days of programmable logic,
every PLD manufacturer also produced a
specialized device programmer for its
family of logic devices.
Later, universal device programmers
came onto the market that supported
Mr. Amish J. Tankariya
Later, universal device programmers
came onto the market that supported
several logic device families from
different manufacturers.
Today's device programmers usually can
program common PLDs (mostly
PAL/GAL equivalents) from all existing
manufacturers.
Common file formats used to store the
Boolean logic pattern (fuses) are JEDEC,
Altera POF (Programmable Object File),
or Xilinx BITstream.
100
PLD LANGUAGES
Many PLD programming devices accept input in a
standard file format, commonly referred to as 'JEDEC
files. They are analogous to software compilers.
The languages used as source code for logic compilers
are called hardware description languages, or HDLs.
HDL frequently used for low-complexity devices
Mr. Amish J. Tankariya
HDL frequently used for low-complexity devices
CUPL Universal Compiler for Programmable Logic
ABEL Advanced Boolean Expression Language
Palasm Sorry No AcronymHere
HDL frequently used for higher-level -complexity
devices:
Verilog
VHDL
101
DESIGN FLOWCHART OF PLD
DEFINATION CODE
WRITING
CODE
IMPLEMENTATION
CODE
SIMULATION
Mr. Amish J. Tankariya
BINARY/HEX FILE
GENERATION
INTERFACING
IMLEMENTATION IN DEVICE
102
CONCLUSION:
The value of programmable logic has always
been its ability to shorten development
cycles for electronic equipment
manufacturers.
And help them to get their product to
market faster.
Mr. Amish J. Tankariya
market faster.
Integrate more functions inside their
devices,
Reduce costs.
Time-saving.
Programmable logic is certain to expand
its popularity with digital designers.
103
QUESTIONS
104