Experiment 1

All Gates
VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity allgatess is
Port ( Ain,Bin : in std_logic;
Op_not : out std_logic;
Op_or : out std_logic;
Op_and : out std_logic;
Op_nor : out std_logic;
Op_nand : out std_logic;
Op_xor : out std_logic;
Op_xnor : out std_logic);
end allgatess;
architecture allgatess of allgatess is
begin
Op_not <= not Ain;
Op_or <= Ain or Bin;
Op_and <= Ain and Bin;
Op_nor <= Ain nor Bin;
Op_nand <= Ain nand Bin;
Op_xor <= Ain xor Bin;
Op_xnor <= Ain xnor Bin;
end allgatess;
PAGE No.____ 1

Verilog Code
module allgatess (A, B, not1, or2, and3, nor4, nand5, xor6, xnor7);
input A,B;
output not1, or2, and3, nor4, nand5, xor6, xnor7;
reg not1, or2, and3, nor4, nand5, xor6, xnor7;
always@(A or B) begin
not1 = ~ (A);
and3 = (A) & (B);
or2 = A | B;
nand5 = ~((A) & (B));
nor4 = ~((A) | (B));
xor6 = (A)
^ (B);
xnor7 = ~((A)^ (B));
end
endmodule

PAGE No.____ 2

SIMULATION WAVEFORM

PAGE No.____ 3

Pattern Generator and Logic Analyzer output

PAGE No.____ 4

Experiment 2 A
2:4 Decoder
External View

Decoder 2:4

Z[0:3]

En

Truth Table
EN
0
1
1
1
1

A B Z[3] Z[2]
X X
1
1
0 0
1
1
0 1
1
1
1 0
1
0
1 1
0
1

Z[1]
1
1
0
1
1

Z[0]
1
0
1
1
1

PAGE No.____ 5

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder_dataflow is
port(A,B,En: in std_logic;
z: out std_logic_vector(3 downto 0));
end decoder_dataflow;
architecture decoder_dataflow of decoder_dataflow is
begin
z(3) <= not(A and B and en);
z(0) <= not((not a) and (not b) and en);
z(2) <= not(a and (not b) and en);
z(1) <= not((not a) and b and en);
PAGE No.____ 6

end decoder_dataflow;

VERILOG CODE
module decoder_dataflow(a,b, enable, z);
input a,b,enable; output[3:0] z;
wire abar,bbar;
assign abar= ~ a;
assign bbar= ~ b;
assign z[0] = ~ (abar & bbar & enable);
assign z[1] = ~ (abar & b & enable);
assign z[2]= ~ (a & bbar & enable);
assign z[3]= ~ (a & b & enable);
endmodule

PAGE No.____ 7

SIMULATION WAVEFORM- 2:4 Decoder

PAGE No.____ 8

Pattern Generator and Logic Analyzer output

PAGE No.____ 9

2: 4 DECODER- Dataflow Modeling

Experiment 2B
PAGE No.____ 10

MUX 8:1
External View

MUX81

D[7:0]

Truth Table
En
SEL[2:0]
0
Xxx
1
000
1
001
1
010
1
011
1
100
1
101
1
110
1
111
VHDL CODE
library IEEE;

Y
0
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]

En

Sel[2:0]

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
PAGE No.____ 11

entity mux_dataflow is
Port ( D : in STD_LOGIC_VECTOR (7 downto 0);
EN : in STD_LOGIC;
SEL : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC);
end mux_dataflow;
architecture mux_dataflow of mux_dataflow is
begin
y<= 0 when en=0 else
d(0) when (en & sel ="1000") else
d(1) when (en & sel = "1001") else
d(2) when (en & sel = "1010") else
d(3) when (en & sel = "1011") else
d(4) when (en & sel = "1100") else
d(5) when (en & sel = "1101") else
d(6) when (en & sel = "1110") else
d(7);
end mux_dataflow;
VERILOG CODE
PAGE No.____ 12

module mux_dataflow(en,da, sel, y);

input en;
input [7:0]da;
input [2:0]sel;
output y;
assign y =
(en ==0)? 0 :(sel==3'b000)?da[0]:(sel==3'b001)?da[1]:(sel==3'b010)?da[2]:
(sel==3'b011)?da[3]:(sel==3'b100)?da[4]:(sel==3'b101)?da[5]:(sel==3'b110)?da[6]:da[7];
Endmodule

SIMULATION WAVEFORM- 8:1 MUX

PAGE No.____ 13

Pattern Generator and Logic Analyzer output

PAGE No.____ 14

Experiment 2C
PAGE No.____ 15

8:3 Encoder
External View
Encoder3to8

Y[2:0]

X[7:0]

Truth Table
En
X[7:0]
0
XXXXXXX
1
00000001
1
00000010
1
00000100
1
00001000
1
00010000
1
00100000
1
01000000
1
10000000
VHDL CODE
library IEEE;

En

Y[2:0]
000
000
001
010
011
100
101
110
111

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
PAGE No.____ 16

entity encoder_dataflow is
Port ( EN : in STD_LOGIC;
X : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end encoder_dataflow;
architecture encoder_dataflow of encoder_dataflow is
begin
Y<= "000" WHEN EN='1' ELSE
"000" WHEN EN='0' AND X="00000001" ELSE
"001" WHEN EN='0' AND X="00000010" ELSE
"010" WHEN EN='0' AND X="00000100" ELSE
"011" WHEN EN='0' AND X="00001000" ELSE
"100" WHEN EN='0' AND X="00010000" ELSE
"101" WHEN EN='0' AND X="00100000" ELSE
"110" WHEN EN='0' AND X="01000000" ELSE
"111" WHEN EN='0' AND X="10000000" ELSE
"000" ;
end encoder_dataflow;
Verilog Code
module encode(x, En, y);
input En;
input [7:0] x;
output [2:0] y;
reg [2:0] y;
PAGE No.____ 17

always @ (En , x)
begin
if (En==1)
y = 3'b0;
else
case (x)
8'b00000001 : y = 3'b000;
8'b00000010 : y = 3'b001;
8'b00000100 : y = 3'b010;
8'b00001000 : y = 3'b011;
8'b00010000 : y = 3'b100;
8'b00100000 : y = 3'b101;
8'b01000000 : y = 3'b110;
8'b10000000 : y = 3'b111;
default: y = 3'b000;
endcase
end
endmodule

SIMULATION WAVEFORM- Encoder

PAGE No.____ 18

Pattern Generator and Logic Analyzer output

PAGE No.____ 19

Experiment 2D
PAGE No.____ 20

Priority Encoder
External View

GS

Priority Encoder8to3

Y[2:0]

X[7:0]
En0

Truth Table
En

En

x0x1x2x3x4x5x6x

Y[2:0]

GS

EN0

000
000
000
001
010
011
100
101
110
111
000
111

1
1
0
0
0
0
0
0
0
0
0
0

1
0
1
1
1
1
1
1
1
1
1
1

1
1
0
0
0
0
0
0
0
0
0
0

xxxxxxxx
11111111
xxxxxxx0
xxxxxx0x
xxxxx0xx
xxxx0xxx
xxx0xxxx
xx0xxxxx
x0xxxxxx
0xxxxxxx
10010100
01111111

PAGE No.____ 21

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Encoderp is
Port ( x : in STD_LOGIC_VECTOR (7 downto 0);
y : out STD_LOGIC_VECTOR (2 downto 0);
en : in STD_LOGIC;
en0 : out STD_LOGIC;
gs : out STD_LOGIC);
end Encoderp;
architecture Encoderp of Encoderp is
begin
gs<= '1' when en='1' or x="11111111" else '0';
en0<= '0' when x="11111111" else '1';
y <= "000" when ((en='0') and (x(7)='0')) else
"001" when ((en='0') and (x(6)='0')) else
PAGE No.____ 22

"010" when ((en='0') and (x(5)='0')) else

"011" when ((en='0') and (x(4)='0')) else
"100" when ((en='0') and (x(3)='0')) else
"101" when ((en='0') and (x(2)='0')) else
"110" when ((en='0') and (x(1)='0')) else
"111" when ((en='0') and (x(0)='0')) else
"111" ;
end Encoderp;
Verilog Code
module enp(x, y, en, en0, gs);
input [7:0] x;
output [2:0] y;
input en;
output en0,gs;
reg en0,gs;
reg [2:0] y;
always@(x or en)
begin
if((en==1'b1)||(x==8'b11111111))
gs<=1'b1;
else
PAGE No.____ 23

gs<=1'b0;
end
always@(x)
begin
if(x==8'b11111111)
en0<=1'b0;
else
en0<=1'b1;
end
always@(x,en)
begin
if((en==1'b0)&& x[7]==1'b0) y<=3'b000;
else if((en==1'b0)&& x[7]==1'b0) y<=3'b000;
else if((en==1'b0)&& x[6]==1'b0) y<=3'b001;
else if((en==1'b0)&& x[5]==1'b0) y<=3'b010;
else if((en==1'b0)&& x[4]==1'b0) y<=3'b011;
else if((en==1'b0)&& x[3]==1'b0) y<=3'b100;
else if((en==1'b0)&& x[2]==1'b0) y<=3'b101;
else if((en==1'b0)&& x[1]==1'b0) y<=3'b110;
else y<=3'b111;
end
endmodule

PAGE No.____ 24

SIMULATION WAVEFORM- Priority Encoder

PAGE No.____ 25

Pattern Generator and Logic Analyzer output

PAGE No.____ 26

Experiment 2E
Comparator
External View

AGB

A[3:0]

Comparator
B[3:0]

ALB
AEB

Truth Table
A[3:0]

B[3:0]

AGB

ALB

0000
1111
1111

1111
0000
1111

0
1
0

1
0
0

AEB

0
0
1

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparatorNbit is
Generic (N: integer := 3);
Port( A,B: in STD_LOGIC_VECTOR(N downto 0);
ALB,AGB,AEB: out STD_LOGIC);
end comparatorNbit;
PAGE No.____ 27

architecture comparatorNbit of comparatorNbit is

begin
process(A,B)
begin
if ( A < B ) then
ALB <= '1';
else ALB <= '0';
end if;
if ( A > B ) then
AGB <= '1';
else
AGB <= '0';
end if;
if ( A = B ) then
AEB <= '1';
else
AEB <= '0';
end if;
end process;
end comparatorNbit;

PAGE No.____ 28

Verilog Code
module comparator(A, B, AEB, ALB,AGB);
input [3:0] A, B;
output AEB, ALB,AGB ;
reg AEB, ALB,AGB;
always @ (A or B)
begin
if(A > B)
AGB = 1;
else
AGB = 0;
if(A< B)
ALB = 1;
else
ALB= 0;
if(A == B)
AEB = 1;
else
AEB = 0;
endmodule

PAGE No.____ 29

SIMULATION WAVEFORM- N Bit Comparator

PAGE No.____ 30

2: 4 DECODER- Dataflow Modeling

Pattern Generator and Logic Analyzer output

PAGE No.____ 31

Experiment 2F
DeMux 8:1
External View
DEMUX18

Truth Table
En
0
1
1
1
1
1
1
1
1

SEL[2:0]
xxx
000
001
010
011
100
101
110
111

En

D[0]
0
Y
0
0
0
0
0
0
0

D[1]
0
0
Y
0
0
0
0
0
0

D[2]
0
0
0
Y
0
0
0
0
0

D[3]
0
0
0
0
Y
0
0
0
0

D[4]
0
0
0
0
0
Y
0
0
0

D[5]
0
0
0
0
0
0
Y
0
0

D[6]
0
0
0
0
0
0
0
Y
0

D[7]
0
0
0
0
0
0
0
0
Y

D[7:0]

Sel[2:0]

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
PAGE No.____ 32

entity DEMUX_1to8 is
port(d : out STD_LOGIC_VECTOR (7 downto 0);
en: in std_logic;
SEL : in STD_LOGIC_VECTOR (2 downto 0);
Y : in STD_LOGIC);
end DEMUX_1to8;
architecture DEMUX_1to8 of DEMUX_1to8 is
begin
process (en, sel)
begin
d <= "00000000";
if (en= '0')
then
d <= "00000000" ;
else
case sel is
when "000" => d(0) <= y;
when "001" => d(1) <= y;
when "010" => d(2) <= y;
when "011" => d(3) <= y;
when "100" => d(4) <= y;
when "101" => d(5) <= y;
when "110" => d(6) <= y;
when "111" => d(7) <= y;
when others => d <= "00000000";
end case;
PAGE No.____ 33

end if;
end process;
end DEMUX_1to8;
Verilog Code
module demux(en,sel, y,d);
input en, y;
input [2:0] sel;
output [7:0] d;
reg [7:0] d;
always@ ( en , sel)
begin
d= 8'd0;
if ( en == 0)
d = 8'd0;
else
case(sel)
3'd0 : d[0] = y;
3'd1 : d[1] = y;
3'd2 : d[2] = y;
3'd3 : d[3] = y;
3'd4 : d[4] = y;
3'd5 : d[5] = y;
3'd6 : d[6] = y;
3'd7 : d[7] = y;
default : d = 8'd0;
endcase
end
PAGE No.____ 34

endmodule

SIMULATION WAVEFORM- 1:8 DeMux

PAGE No.____ 35

Pattern Generator and Logic Analyzer output

PAGE No.____ 36

Experiment 2G
PAGE No.____ 37

Binary to Gray
External View
BINARY to GRAY
B[3:0]

G[3:0]

Truth Table

VHDL Code
PAGE No.____ 38

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity g2b_data is
Port ( b : in STD_LOGIC_VECTOR (3 downto 0);
g : out STD_LOGIC_VECTOR (3 downto 0));
end g2b_data;
architecture g2b_data of g2b_data is
begin
g(3)<= b(3);
g(2) <= b(3) xor b(2);
g(1) <= b(2) xor b(1);
g(0) <= b(1) xor b(0);
end g2b_data;
Verilog Code
module b2g_dataflow(b, g);
input [3:0] b;
output [3:0] g;
assign g[3]=b[3];
assign g[2]=b[2]^b[3];
assign g[1]=b[1]^b[2];
assign g[0]=b[0]^b[1];
endmodule
PAGE No.____ 39

SIMULATION WAVEFORM- Binary To Gray

PAGE No.____ 40

Pattern Generator and Logic Analyzer output

PAGE No.____ 41

Experiment 3
FULL ADDER
External View

Cin

SUM

FULL ADDER

Truth Table
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

CARRY

Cin
0
1
0
1
0
1
0
1

Sum
0
1
1
0
1
0
0
1

Carry
0
0
0
1
0
1
1
1

PAGE No.____ 42

VHDL Code
1. Dataflow Modeling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladderd is
Port ( a,b,cin : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end fulladderd;
architecture fulladderd of fulladderd is
begin
sum<= a xor b xor cin ;
carry<=(a and b) or (b and cin) or (cin and a);
end fulladderd;
Verilog Code
module fulladeer_dataflow(a,b,cin, sum,carry);
input a,b,cin;
output sum,carry;
assign sum = a ^ b ^ cin ;
assign carry= (a & b)|(b & cin)|(cin & a);
endmodule
PAGE No.____ 43

2. Behavioral Modeling
VHDL Modeling
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladder_behavioral is
Port ( a,b,cin : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end fulladder_behavioral ;
architecture fulladder_behavioral of fulladder_behavioral is
begin
process(a,b,cin)
begin
sum<= a xor b xor cin ;
carry<=(a and b) or (b and cin) or (cin and a);
end process;
end fulladder_behavioral ;
Verilog Code
module fulladder_behavioral(a,b,cin, sum,carry);
input a,b,cin;
output sum,carry;
PAGE No.____ 44

reg sum,carry
always@(a,b,cin)
begin
sum = a ^ b ^ cin ;
carry= (a & b)|(b & cin)|(cin & a);
endmodule
3. Structural Modeling
VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fulladder_structural is
Port ( a,b,cin : in STD_LOGIC;
sum,carry : out STD_LOGIC);
end fulladder_structural;
architecture fulladder_structural of fulladder_structural is
component xor33 is
port(a,b,c:in std_logic; z:out std_logic);
end component;
component or33 is
port(a,b,c:in std_logic; z: out std_logic);
PAGE No.____ 45

end component;
component and22 is
port(a,b:in std_logic; z: out std_logic);
end component;
signal x1,x2,x3:std_logic;
begin
A1: xor33 port map(a,b,cin,sum);
A2: and22 port map(a,b,x1);
A3: and22 port map(b,cin,x2);
A4: and22 port map(cin,a,x3);
A5: or33 port map(x1,x2,x3,carry);
end fulladder_structural;

PAGE No.____ 46

Component Definition
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity xor33 is
Port ( a,b,c : in STD_LOGIC;
z : out STD_LOGIC);
end xor33;
architecture xor33 of xor33 is
begin
z<= a xor b xor c;
end xor33;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity and22 is
Port ( a,b : in STD_LOGIC;
z : out STD_LOGIC);
end and22;
architecture and22 of and22 is
begin
z<= a and b;
end and22;
PAGE No.____ 47

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity or33 is
Port ( a,b,c : in STD_LOGIC;
z : out STD_LOGIC);
end or33;
architecture or33 of or33 is
begin
z<= a or b or c;
end or33;
Verilog Code
module fulladder_structural(a,b,cin, sum,carry);
input a,b,cin;
output sum,carry;
xor(sum,a,b,cin);
and(x1,a,b);
and(x2,b,cin);
and(x3,cin,a);
or(carry,x1,x2,x3);
endmodule

PAGE No.____ 48

SIMULATION WAVEFORM-Full Adder

PAGE No.____ 49

Pattern Generator and Logic Analyzer output

PAGE No.____ 50

Experiment 4
11 bit ALU
External View

Truth Table
Enable
0
1
1
1
1
1
1
1
1
1
1
1
1
1

Opcode
XXXX
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100

Y[21:0]
Tri-state condition
A+B
A-B
A complement
A*B
A AND B
A OR B
A NAND B
A NOR B
A XOR B
A XNOR B
A+1
B+1
A-1
PAGE No.____ 51

1
1
1

1101
1110
1111

B-1
B complement
reset

VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu11 is
Port ( A : in STD_LOGIC_VECTOR (10 downto 0);
B : in STD_LOGIC_VECTOR (10 downto 0);
Enable : in STD_LOGIC;
opcode : in std_logic_vector (3 downto 0);
y : out STD_LOGIC_VECTOR (21 downto 0));
end alu11;
architecture alu11 of alu11 is
begin
process(opcode,a,b)
variable temp1,temp2:std_logic_vector(21 downto 0);
begin
temp1:=("00000000000" & a);--converting 11 bit a to 22 bit size
temp2:=("00000000000" & b);-- converting 11 bit b to 22 bit size
if(enable='1')
then
PAGE No.____ 52

case opcode is
when "0000" =>y<=temp1 + temp2;
when "0001" =>y<=temp1 - temp2;
when "0010" => y(10 downto 0)<=not a;
y(21 downto 11)<="000000000000";
when "0011" => y<= a * b;
when "0100" => y<= temp1 and temp2;
when "0101" => y<= temp1 or temp2;
when "0110" => y(10 downto 0)<= a nand b;
y(21 downto 11)<="00000000000";
when "0111" => y(10 downto 0)<= a nor b;
y(21 downto 11)<="00000000000";
when "1000" => y<= temp1 xor temp2;
when "1001" => y(10 downto 0)<= a xnor b;
y(21 downto 11)<="00000000000";
when"1010"=>y<=temp1+1;
when"1011"=>y<=temp2+1;
when"1100"=>y<=temp1-1;
when"1101"=>y<=temp2-1;
when"1110"=>y(10 downto 0)<=not b;
y(21 downto 11)<="00000000000";
when "1111" => y<= (others =>'0');
when others => null;
end case;
PAGE No.____ 53

else
y<= (others => 'Z');
end if;
end process;
end alu11;
Verilog Code for 11 Bit ALU
module alu_22(a, b, en, opc, y);
input [010:0] a;
input [010:0] b;
input en;
input [03:0] opc;
output [021:0] y;
reg [021:0] y;
always@ (opc,en,a,b)
begin
if (en==1)
begin
case (opc)
4'd0:y=a+b;
4'd1:y=a-b;
4'd2:y={11'd0 ,~a};
4'd3:y=a*b;
4'd4:y=a & b;
4'd5:y=a | b;
4'd6:y={11'd0,~(a & b)};
PAGE No.____ 54

4'd7:y={11'd0,~(a | b)};
4'd8:y=a ^ b;
4'd9:y={11'd0,~(a ^ b)};
4'd10:y=a+1;
4'd11:y=b+1;
4'd12:y=a-1;
4'd13:y=b-1;
4'd14:y={11'd0,~ b};
4'd15:y=21'd0;
endcase
end
else
y=21'dZ;
end
endmodule

PAGE No.____ 55

SIMULATION WAVEFORM-11 bit ALU

High Impedance state

Addition

Subtraction

PAGE No.____ 56

A complement

Multiplication

AND

PAGE No.____ 57

OR

NAND

NOR

PAGE No.____ 58

XOR

XNOR

INCREMENT A

PAGE No.____ 59

INCREMENT B

DECREMENT A

DECREMENT B

PAGE No.____ 60

B complement

RESET

PAGE No.____ 61

2: 4 DECODER- Dataflow Modeling

Pattern Generator and Logic Analyzer output

PAGE No.____ 62

Experiment 5A
SR Flip-Flops
External View

preset

Q
SR FF
SR[1:0]

Qbar

reset

Truth Table
Preset
Reset
0
1
1
0
1
1
1
1
1
1
1
1

Clk
X
X

S:SR[1] R:SR[0]
X
X
X
X
0
0
0
1
1
0
1
1

Q
1
0
PS
0
1
1

Qbar
0
1
PS
1
0
1
PAGE No.____ 63

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity srff is
Port ( preset,reset,clk: in STD_LOGIC;
sr: in std_logic_vector(1 downto 0);
q,qbar : inout STD_LOGIC);
end srff;
architecture srff of srff is
begin
process (clk,preset,reset)
variable temp1, temp2 : std_logic:='0';
begin
if reset='0' then
temp1 := '0';temp2:='1';
elsif preset='0' then
temp1 := '1';temp2:='0';
elsif rising_edge (clk) then
case sr is
when "01" => temp1 := '0';
when "10" => temp1 := '1';

temp2:='1';
temp2:='0';
PAGE No.____ 64

when "00" => temp1 := temp1; temp2 := not temp1;

when "11" => temp1 := '1'; temp2:='1';
when others => Null;
end case;
end if;
q <= temp1;
qbar <= temp2;
end process ;
end srff;
Verilog Code
module srff(SR,reset,preset,clk, q, qbar);
input [1:0]SR;
input clk,reset,preset;
output q, qbar;
reg q, qbar;
initial
begin
q=1'b0;
qbar=1'b1;
end
always @ (posedge clk or negedge reset or negedge preset)
begin
if (reset==1'b0)
begin
q = 1'b0;
qbar=~ q;
end
PAGE No.____ 65

else if (preset==1'b0)
begin
q = 1'b1;
qbar=~ q;
end
else
begin
case (SR)
2'b00 : begin
q = q; qbar =~ q;
end
2'b01 : begin
q = 0; qbar =~ q;
end
2'b10 : begin
q = 1; qbar =~ q;
end
2'b11 : begin
q = 1; qbar = 1;
end
endcase
end
end
endmodule

PAGE No.____ 66

SIMULATION WAVEFORM-SR Flip Flop

PAGE No.____ 67

Pattern Generator and Logic Analyzer output

PAGE No.____ 68

EXPERIMENT 5B
JK FlipFlop
External View
Q
JK FF
JK[1:0]

Truth Table
Preset
0
1
1
1
1
1

Reset
1
0
1
1
1
1

Clk
X
X

Qbar

J: JK[1] K: JK[0]
X
X
X
X
0
0
0
1
1
0
1
1

Q Qbar
1
0
0
1
PS PS
0
1
1
0
Toggle
State

PAGE No.____ 69

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jkff is
port(JK : in std_logic_vector (1 downto 0);
clk : in std_logic; q, qb : out std_logic);
end jkff;
architecture jkff of jkff is
begin
process (clk)
variable temp1, temp2 : std_logic :=0;
begin
if rising_edge (clk) then
case JK is
when "01" => temp1 := '0';
when "10" => temp1 := '1';
when "00" => temp1 := temp1;
when "11" => temp1 := not temp1;
when others => Null;
end case;
q <= temp1;
temp2 := not temp1;
qb <= temp2;
end if;
PAGE No.____ 70

end process ;
end jkff;
Verilog Code
module jkff(JK, clk, q, qb);
input [1:0]JK;
input clk;
output q, qb;
reg q, qb;
initial
begin
q=1'b0;
qb=1'b1;
end
always @ (posedge clk)
begin
case (JK)
2'b00 : q = q;
2'b01 : q = 0;
2'b10 : q = 1;
2'b11 : q =~ q;
endcase
qb =~ q;
end
endmodule
PAGE No.____ 71

SIMULATION WAVEFORM-JK Flip Flop

PAGE No.____ 72

2: 4 DECODER- Dataflow Modeling

Pattern Generator and Logic Analyzer output

PAGE No.____ 73

Experiment 5C
D-Flipflop
External View

preset

Q
D FF
D

Truth Table
Preset
Reset
0
1
1
0
1
1
1
1

Qbar

reset

Clk
X
X

D
X
X
0
1

Q
1
0
0
1

Qbar
0
1
1
0

PAGE No.____ 74

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dff is
Port ( d,clk,reset,preset : in STD_LOGIC;
q : out STD_LOGIC; qbar: out std_logic);
end dff;
architecture dff of dff is
begin
process(clk,reset,preset)
variable temp1,temp2 : std_logic := 0;
begin
if reset='0'
then
temp1:='0';
temp2:= not temp1;
elsif preset='0'
then
temp1:='1';
temp2:= not temp1;
PAGE No.____ 75

elsif(clk'event and clk='1')

then
temp1:=d;
temp2:= not temp1;
end if;
q<= temp1;
qbar<= temp2;
end process;
end dff;
Verilog Code
module dff(clk,reset,preset,d, q,qbar);
input clk,reset,preset,d;
output q,qbar;
reg q,qbar;
always @ (posedge clk or negedge reset or negedge preset)
if (reset==1'b0)
begin
q = 1'b0;
qbar=~ q;
end
PAGE No.____ 76

else if (preset==1'b0)
begin
q = 1'b1;
qbar=~ q;
end
else
begin
q = d;
qbar = ~q;
end
endmodule

PAGE No.____ 77

SIMULATION WAVEFORM-D Flip Flop

PAGE No.____ 78

Pattern Generator and Logic Analyzer output

PAGE No.____ 79

Experiment 5D
T-Flipflop
External View

preset

Q
T FF
T

Truth Table
Preset
Reset
0
1
1
0
1
1
1
1

Qbar

reset

Clk
X
X

T
X
X
0
1

Q
Qbar
1
0
0
1
PS
PS
Toggle State

PAGE No.____ 80

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tff is
Port ( t,clk,reset,preset : in STD_LOGIC;
q,qbar : inout STD_LOGIC);
end tff;
architecture tff of tff is
begin
process(clk,reset,preset)
variable temp1,temp2 : std_logic;
begin
if reset='0'
then
temp1:='0';
temp2:= not temp1;
elsif preset='0'
then
temp1:='1';
temp2:= not temp1;
PAGE No.____ 81

elsif(clk'event and clk='1')

then
if t='1'
then
temp1:= not q;
temp2:= not temp1;
end if;
end if;
q<= temp1;
qbar<= temp2;
end process;
end tff;
Verilog Code
module tff(t,reset,preset,clk, q,qbar);
input t,reset,preset,clk;
output q,qbar;
reg q,qbar;
always @ (posedge clk or negedge preset or negedge preset)
if (reset==1'b0)
begin
q = 1'b0;
PAGE No.____ 82

qbar=~ q;
end
else if (preset==1'b0)
begin
q = 1'b1;
qbar=~ q;
end
else if (t==1'b1)
begin
q = ~ q;
qbar = ~q;
end
endmodule

PAGE No.____ 83

SIMULATION WAVEFORM-T Flip Flop

PAGE No.____ 84

Pattern Generator and Logic Analyzer output

PAGE No.____ 85

Experiment 6A
Four Bit Binary Counter
External View
clk

Truth Table
clr
1
1
1
1
1
1
1
1
1
1
1

Q[3:0]

FOUR BIT COUNTER

clr

clk

q[3:0]
0000
0001
0010
0011
0100
0110
0110
0111
1000
1001
1010

clr
1
1
1
1
1
1

clk

q[3:0]
1011
1100
1101
1110
1111
0000

0000

The active high clear input is synchronous with

clock.(means its effect on output ,only when clock is present)

PAGE No.____ 86

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fourbit is
port (clk, clr : in std_logic;
q :inout std_logic_vector (3 downto 0));
end fourbit;
architecture fourbit of fourbit is
begin
process(clk)
variable temp : std_logic_vector (3 downto 0) := "0000";
begin
if rising_edge (clk) then
if (clr = '0') then
temp := "0000";
else
temp:=temp+1;
end if;
end if;
q<= temp;
end process;
end fourbit;
PAGE No.____ 87

Verilog Code
module counter_4bit_verilog(clk, clear, q);
input clk;
input clear;
output [3:0] q;
reg[3:0] q;
initial
q = 4'b0000;
always@(posedge clk)
begin
if(clear==0)
q = 4'b0000;
else
q = q+1;
end
endmodule

PAGE No.____ 88

SIMULATION WAVEFORM- Four Bit Binary Counter

PAGE No.____ 89

Pattern Generator and logic analyzer output

PAGE No.____ 90

Experiment 6B
BCD Counter with synchrous clear
External View
clk

BCD Counter_synchrous clear

Truth Table
clr
1
1
1
1
1
1
1
1
1
1
1

Q[3:0]

clr

clk

q[3:0]
0000
0001
0010
0011
0100
0110
0110
0111
1000
1001
1010

clr
1

clk

q[3:0]
0000

0000

The active high clear input is synchronous with

clock.(means its effect on output ,only when clock is present)

PAGE No.____ 91

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_synchronous is
port (clk, clr : in std_logic;
q :inout std_logic_vector (3 downto 0));
end BCD_synchronous;
architecture BCD_synchronous of BCD_synchronous is
begin
ct : process(clk)
variable temp : std_logic_vector (3 downto 0) := "0000";
begin
if rising_edge (clk) then
if (clr = '0') then
temp := "0000";
elsif(temp="1001") then
temp:="0000" ;
else
temp:=temp+1;
end if;
end if;
PAGE No.____ 92

q<= temp;
end process ct;
end BCD_synchronous;
Verilog Code
module BCD_Syn_Verilog(clk, clear, q);
input clk;
input clear;
output [3:0] q;
reg[3:0] q;
initial
q = 4'b0000;
always@(posedge clk)
begin
if(clear==0)
q = 4'b0000;
else if(q==4'b1001)
q = 4'b0000;
else
q = q+1;
end
endmodule

PAGE No.____ 93

SIMULATION WAVEFORM- BCD (Synchronous Clear)

PAGE No.____ 94

Pattern Generator and Logic Analyzer output

PAGE No.____ 95

Experiment 6C
BCD Counter with asynchrous clear
External View
clk

BCD Counter_asynchrous clear

Truth Table
clr
1
1
1
1
1
1
1
1
1
1
1

Q[3:0]

clr

clk

q[3:0]
0000
0001
0010
0011
0100
0110
0110
0111
1000
1001
1010

clr
1

clk

q[3:0]
0000

0000

The active high clear input is asynchronous with

clock.(means its effect on output doesnt depend on clock presence)

PAGE No.____ 96

VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_asyncronouys is
port (clk, clr : in std_logic;
q :inout std_logic_vector (3 downto 0));
end BCD_asyncronouys;
architecture BCD_asyncronouys of BCD_asyncronouys is
begin
process(clk,clr)
variable temp : std_logic_vector (3 downto 0) := "0000";
begin
if (clr = '0') then
temp := "0000";
elsif rising_edge (clk) then
if(temp="1001")
then
temp:="0000" ;
else
temp:=temp+1;
end if;
end if;
q<= temp;
PAGE No.____ 97

end process ;
end BCD_asyncronouys;
Verilog Code
module BCD_asyn_verilog(clk, clear, q);
input clk;
input clear;
output [3:0] q;
reg[3:0] q;
initial
q = 4'b0000;
always @(posedge clk or negedge clear)
begin
if(clear==0)
q = 4'b0000;
else
if(q==4'b1001)
q = 4'b0000;
else
q =q +1;
end
endmodule

PAGE No.____ 98

SIMULATION WAVEFORM- BCD (Asynchronous Clear)

PAGE No.____ 99

Pattern Generator and Logic Analyzer output

PAGE No.____100

PAGE No.____101

Experiment 7
Seven segment Display
External View

Truth Table
col[0:3]

row[0:3]

0001
0001
0001
0001
0010
0010
0010
0010
0100

0001
0010
0100
1000
0001
0010
0100
1000
0001

message
[0:6]
1111110
0110011
1111111
1001110
0110000
1011011
1111011
0111101
1101101

Display
0
4
8
C
1
5
9
D
2
PAGE No.____102

0100
0100
0100
1000
1000
1000
1000
col= 0001(colomn 1)
col= 0010(colomn 2)
col= 0100(colomn 3)
col= 1000(colomn 4)

0010
0100
1000
0001
0010
0100
1000

1011111
1110111
1001111
1111001
1110000
0011111
1000111

6
A
E
3
7
B
F

row=0001(row 1)
row=0010(row 2)
row=0100(row 3)
row=1000(row 4)

PAGE No.____103

Interfacing Diagram

Procedure
1. Make the connection between FRC5 of the FPGA board to the Seven Segment connector of the
GPIO I card.
2. Make the connection between FRC4 of the FPGA board to the Key board connector of the GPIO I
card.
3. Connect the downloading cable and power supply to the FPGA board.
4. Download bit file on to FPGA .
5. Press the HEX keys and verify the displayed dat on seven segment display.
PAGE No.____104

VHDL code to display messages on the given seven segment display accepting Hex key pad input data.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seven_segment_display is
Port ( col : out std_logic_vector(3 downto 0);
row : in std_logic_vector(3 downto 0);
clk : in std_logic;
Led_sel: out std_logic_vector(3 downto 0);
message: out std_logic_vector(6 downto 0));
end seven_segment_display;
architecture seven_segment_display of seven_segment_display is
signal message_temp : std_logic_vector(6 downto 0);
signal col_temp : std_logic_vector(3 downto 0);
signal row_temp : std_logic_vector(3 downto 0);
signal clk_div : std_logic_vector( 11 downto 0);
signal clk_4k : std_logic;
signal cnt_2bit : std_logic_vector(1 downto 0);
begin
PAGE No.____105

process(clk)
begin
if clk='1' and clk'event then
clk_div <= clk_div + '1';
end if;
end process;
clk_4k <= clk_div(11);
process(clk_4k)
begin
if clk_4k = '1' and clk_4k'event then
cnt_2bit <= cnt_2bit + '1';
end if;
end process;
process(cnt_2bit)
begin
case cnt_2bit is
when "00" => col_temp <= "0001";
PAGE No.____106

when "01" => col_temp <= "0010";

when "10" => col_temp <= "0100";
when "11" => col_temp <= "1000";
when others => null;
end case;
end process;
row_temp <= row;
col <= col_temp;
Led_sel <= "0000";
process(col_temp,row)
begin
case col_temp is
when "0001" =>
case row_temp is
when "0001" => message_temp<= "1111110";
when "0010" => message_temp <= "0110011";
when "0100" => message_temp <= "1111111";
when "1000" => message_temp <= "1001110";
when others=> message_temp <= "0000000";
end case;
PAGE No.____107

when "0010" =>

case row_temp is
when "0001" => message_temp <= "0110000";
when "0010" => message_temp <= "1011011";
when "0100" => message_temp <= "1111011";
when "1000" => message_temp <= "0111101";
when others=> message_temp <= "0000000";
end case;
when "0100" =>
case row_temp is
when "0001" => message_temp <= "1101101";
when "0010" => message_temp <= "1011111";
when "0100" => message_temp <= "1110111";
when "1000" => message_temp <= "1001111";
when others=> message_temp <= "0000000";
end case;
when "1000" =>
case row_temp is
when "0001" => message_temp <= "1111001";
when "0010" => message_temp <= "1110000";
when "0100" => message_temp <= "0011111";
PAGE No.____108

when "1000" => message_temp <= "1000111";

when others=> message_temp <= "0000000";
end case;
when others=> null;
end case;
end process;
message<= message_temp;
end seven_segment_display;

PAGE No.____109

Experiment 8A
DC Motor
External View
reset

Enable

Speed
Clk
Direction

mtr1
DC MOTOR

mtr2

Truth Table
reset
0
1
1

Direction mtr1 mtr2 Rotation of rotor

X
0
0
No rotation
0
1
0
Anticlockwise
1
0
1
Clockwise

Interfacing Diagram
PAGE No.____110

F
R
C
9

FPGA KIT
FRC1

FRC7

mtr1

Direction
Enable

mtr2

Speed[0:3]

FRC

F
R
C

`
`

Reset

Dip Switch

GPIO II

F
Key R
C

L
2
9
3
D

DC
MOTOR

H-Bridge IC L293D Connection

PAGE No.____111

Procedure

1. Make the connection between FRC1 of the FPGA board to the dip switch connector of the GPIO II
card.
2. Make the connection between FRC7 of the FPGA board to the Key board connector of the GPIO II
card.
3. Make the connection between FRC9 of the FPGA board to the H-bridge connector.
4.Connect the downloading cable and power supply to the FPGA board.
4. Download bit file on to FPGA .
5. Press the HEX keys and observe variable speed.
6. Change direction dip switch and observe anti-clock wise and clock wise rotation of DC motor.
VHDL code to control speed and direction of DC Motor
PAGE No.____112

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dc_motor is
Port(enable,mtr1,mtr2 : out std_logic;
clk,reset: in std_logic;
direction: in std_logic ;
speed : in std_logic(3 downto 0));
end dc_motor;
architecture dc_motor of dc_motor is
signal clk_div : std_logic_vector( 25 downto 0);
signal clk_4k ,check: std_logic;
Signal cnt_8bit:std_logic_vector(7 downto 0):=11111110;
Signal duty_cycle:integer range 0 to 255;
begin

process(clk)
begin
PAGE No.____113

if clk='1' and clk'event then

clk_div <= clk_div + '1';
end if;
end process;
clk_4k <= clk_div(8);
Enable<=1;
check<= speed(0) and speed(1) and speed(2) and speed(3);
process(clk_4k)
begin
if clk_4k = '1' and clk_4k'event then
cnt_8bit <= cnt_8bit + '1';
end if;
end process;

process(check)
begin
PAGE No.____114

if falling_edge(check) then
case speed is
when 1110" => duty_cycle <= 225;
when 1101" => duty_cycle <= 200;
when 1011" => duty_cycle <= 175;
when 0111" => duty_cycle <= 150;
when others => duty_cycle <= 150;
end case;
end if;
end process;
Process(reset,direction)
begin
if reset=0 then
mtr1<=0;mtr2<=0;
else
if direction=0 then
mtr2<=0
if cnt_8bit >= duty_cycle then
mtr1<=1;
else
mtr1<=0;
end if;
PAGE No.____115

else
mtr1<=0
if cnt_8bit >= duty_cycle then
mtr2<=1;
else
mtr2<=0;
end if;
end if;
end if;
end process;
end dc_motor;
UCF

Experiment 8B
PAGE No.____116

Stepper Motor
External View
reset
Speed(1:0)
Clk
Direction

DAC(3:0)
STEPPER MOTOR

Truth Table
reset DirectionSpeed[0:1] Rotation of
rotor
0
X
XX
No rotation
1
0/1
00
Lowest speed
1
0/1
01
1
0/1
10
1
0/1
11
Highest speed
Direction=0 Anticlockwise
Direction=1 Clockwise

Interfacing Diagram
PAGE No.____117

F
R
C
9

FPGA KIT
FRC1

Direction

Speed[1:0]
dac[3:0]

Reset
F
R
C

FRC
Dip Switch

GPIO II

STEPPER
MOTOR

Procedure
PAGE No.____118

1. Make the connection between FRC1 of the FPGA board to the dip switch connector of the GPIO II
card.
2. Make the connection between FRC9 of the FPGA board to the Stepper motor connector.
3. Connect the downloading cable and power supply to the FPGA board.
4. Download bit file on to FPGA .
5. Change speed dip switch and observe variable speed.
6. Change direction dip switch and observe anti-clock wise and clock wise rotation of stepper motor.
VHDL code to control speed and direction of Stepper Motor

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stepper is
Port ( dac: out std_logic_vector(3 downto 0);
clk,reset: in std_logic;
speed:in std_logic_vector(1 downto 0);
direction:in std_logic);
end stepper;
architecture stepper of stepper is
signal clk_div : std_logic_vector(25 downto 0);
PAGE No.____119

signal clk_int: std_logic;

signal angle : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge (clk) then
clk_div <= clk_div + '1';
end if;
end process;
clk_int<=clk_div(21) when speed ="00"else
clk_div(19) when speed ="01"else
clk_div(17) when speed ="10"else
clk_div(15) ;
process(reset,clk_int,dir)
begin
if reset='0' then
angle <= "1001";
elsif rising_edge(clk_int) then
PAGE No.____120

if direction='0' then
angle <= angle(0) & angle(3 downto 1);
else
angle<=angle(2 downto 0) & angle(3);
end if;
end if;
end if;
end process;
dac<=angle;
end stepper;

Experiment 9
Waveform generation using 8bit DAC
PAGE No.____121

External View
reset
Clk

SINE WAVE

DAC(7:0)

SINE WAVE

reset
Clk

DAC(7:0)
SQUARE WAVE

reset
Clk

DAC(7:0)
TRAINGULAR WAVE

reset
Clk

DAC(7:0)
SAWTOOTH WAVE

8bit DAC connection

PAGE No.____122

GPIO
II
Interfacing
Diagram

FPGA KIT

CRO
PAGE No.____123

Dip Switch
FRC

DAC out
Reset

DAC
FRC
FRC1

dac[7:0]
FRC5

Procedure
PAGE No.____124

1. Make the connection between FRC1 of the FPGA board to the dip switch connector of the GPIO II
card.
2. Make the connection between FRC5 of the FPGA board to the DAC connector of GPIO II card.
3. Connect DAC out connectors to CRO channel probe.
4. Connect the downloading cable and power supply to the FPGA board.
5. Download bit file on to FPGA .
6. Change reset dip switch and observe waveform on CRO.
7. Note down lowest frequency and highest frequency for different divided clocks.

VHDL code to generate sine wave using 8 bit DAC

PAGE No.____125

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Entity sinewave is
port ( clk : in std_logic;
reset : in std_logic;
dac_out : out std_logic_vector(0 to 7));
End sine;

architecture sinewave of sinewave is

Signal clk_div:std_logic_vector(7 downto 0);
Signal I :integer range 0 to 179;
Type sine is array (0 to 179) of integer range 0 to 255;

Constant value: sine

PAGE No.____126

:=(128,132,136,141,154,150,154,158,163,167,171,175,180,184,188,
192,195,199,203,206,210,213,216,220,223,226,228,231,234,236,
238,241,243,244,246,247,248,249,250,251,252,253,254,255,255,
255,255,255,254,254,253,252,251,249,246,244,243,241,238,236,
234,231,228,226,223,220,216,213,210,206,203,199,195,192,188,
184,180,175,171,167,163,158,154,150,145,141,136,132,128,123,
119,114,110,105,101,97,92,88,84,80,75,71,67,64,60,56,52,49,45,
42,39,35,32,29,27,24,21,19,17,14,12,11,9,7,6,4,3,2,1,1,0,0,0,0,0,0,
0,0, 1,1,2,3,4,6,7,9,11,12,14,17,19,21,24,27,29,32,35,39,42,45,49,
52,56,60,64,67,71,75,80,84,88,92,97,101,105,110,114,119,123,128);

begin
Process(clk,reset)
begin
if(rst='1') then
clk_div <=(others=>'0');
elsif(clk'event and clk='1') then
clk_div <= clk_div +1;
end if;
end process;
process(clk_div (3))
begin
PAGE No.____127

if(clk_div (3)'event and clk_div (3)='1')then

dac_out<=conv_std_logic_vector(value(i),8);
I<=I+1;
if(i=179) then
i<=0;
end if;
end if;
end process;
end sinewave;

VHDL code to generate square wave using 8 bit DAC

library IEEE;
PAGE No.____128

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity square_wave is
Port ( clk : in std_logic;
reset : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end square_wave;
architecture square_wave of square_wave is
signal clk_div : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin
process(clk)
begin
if rising_edge(clk) then
clk_div <= clk_div + '1' ;
end if;
end process;
PAGE No.____129

process(clk_div (3))
begin
if reset='1' then
counter <= "00000000";
elsif rising_edge(temp(3)) then
if counter<255 and en='0' then
counter <= counter + 1 ;
en<='0';
dac_out <="00000000";
elsif counter=0 then
en<='0';
else
en<='1';
counter <= counter-1;
dac_out <="11111111";
end if;
end if;
end process;
end square_wave;
VHDL code to generate sawtooth wave using 8 bit DAC

PAGE No.____130

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity swatooth_wave is
Port ( clk : in std_logic;
reset : in std_logic;
dac_out : out std_logic_vector(0 to 7));
end swatooth_wave;
architecture swatooth_wave of swatooth_wave is
signal clk_div : std_logic_vector(3 downto 0);
signal counter : std_logic_vector(0 to 7);
signal en :std_logic;
begin

process(clk)
PAGE No.____131

begin
if rising_edge(clk) then
clk_div <= clk_div + '1' ;
end if;
end process;
process(clk_div (3))
begin
if reset='1' then
counter <= "00000000";
elsif rising_edge(clk_div (3)) then
counter <= counter + 1 ;
end if;
end process;
dac_out <=counter;
end swatooth_wave;

VHDL code to generate triangular wave using 8 bit DAC

library IEEE;
PAGE No.____132

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity triangular_wave is
Port ( clk : in std_logic;
reset : in std_logic;
dac_out : out std_logic_vector(7 downto 0));
end triangular_wave ;
architecture triangular_wave of triangular_wave is
signal counter : std_logic_vector(8 downto 0);
signal clk_div : std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
clk_div <= clk_div + '1' ;
end if;
end process;
PAGE No.____133

process(clk_div (3))
begin
if reset='1' then
counter <= "000000000";
elsif rising_edge(clk_div (3)) then
counter <= counter + 1 ;
if counter(8)='0' then
dac_out <=counter(7 downto 0);
else
dac_out <=not(counter(7 downto 0));
end if;
end if;
end process;
end triangular_wave;

Experiment 10
External Light control using relay
PAGE No.____134

External View
Contr1
Contr2

light
LIGHT_RELAY

Truth Table
cntrl1
0
0
1
1

cntrl2
0
1
0
1

Light
OFF
ON
ON
ON

GPIO
II
Interfacing
Diagram
FPGA KIT
Dip Switch
Light Light
Cntr1 Cntr
2 External
FRC
Relay
FRC1
FRC

F
R
C
9

PAGE No.____135

Light

Procedure
PAGE No.____136

1. Make the connection between FRC1 of the FPGA board to the dip switch connector of the GPIO II
card.
2. Make the connection between FRC9 of the FPGA board to the External light connector of GPIO II
card.
3. Connect light out connectors to LED through battery.
4.Connect the downloading cable and power supply to the FPGA board.
5. Download bit file on to FPGA .
6. Change cntrl1 and cntrl2 dip switch and observe switching action of LED.
VHDL code to control external light using relay

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity extlight is
Port ( cntrl1,cntrl2 : in std_logic;
light : out std_logic);
end extlight;

architecture extlight of extlight is

PAGE No.____137

begin
light<= cntrl1 OR cntrl2 ;
end extlight;
UCF
NET "cntrl1" LOC = "P74";
NET "cntrl2" LOC = "P76";
NET "light" LOC = "P5";

PAGE No.____138