IEEE/OSAIIAPR Interational Conference on Informatics, Electronics & Vision

A New Low Voltage Differential Current Conveyor

Sanjay K. Kasodniya
ksanjay@sac.isro.gov.in
Dipankar N agchoudhuri
dnc@daiict.ac.in
Nilesh M. Desai
nmdesai@sac.isro.gov.in
Abstact- Current conveyor (a current mode circuit) is a good
choice for low voltage applications as it provides high gain
bandwidth product. Current mode design technique offers
voltage independent, high bandwidth in analog circuits with
properties of accuracy and versatility in a wide range of
applications. In this paper we present a rail-to-rail low voltage
(1.5 V) diferential current conveyor (L VDCC) circuit in
standard CMOS technology that is suited for low
voltage operation. The proposed circuit uses a low-voltage
current-mirror. The output range is -1.3 to +1.4 voltage which
is nearly rail-to-rail.
This proposed differential current conveyor is
suitable for low power CMOS mixed-mode designs.
1. INTRODUCTION
Current-mode circuits have begun to emerge as an
important class of circuits, with properties of accuracy, good
performance, and versatility in a wide range of applications.
Since the second generation current conveyor (CC I l) was
introduced in 1970 [ 1], several applications, such as
amplifers, oscillators, flters and signal-processing circuits
using CC II have been proposed in the literature [ 2-3].
Current mode circuits are being widely used in high
frequency circuit design applications. Current conveyor
(CC) has been proved to be an important part of current
mode design. Current conveyors are commercially available
now (AD844) and can be used in instrumentation amplifer,
flters, DC-to-DC converter, R mixers, high-frequency
precision rectifers and medical applications such as
electrical impedance tomography. The conventional
operational amplifers cannot be used in the high-frequency
applications due to their limited gain-bandwidth product.
Differential-difference-current-conveyor (DDCC) was
introduced by Chiu [ 2]. Author has combined the
advantages of the CC II (second Generation Current
Conveyor) and differential difference amplifer (DDA), and
extended to a new building block, called DDCC. I t has been
shown that DDCC based circuits offer a competitive design
choice to CC II based and DDA based circuits.
A DDCC, whose symbol is in Fig. 1, is a fve terminal
network with terminal characteristics described by (1)
I yJ = I y2 = I y3 = 0
Vx =VYl-VY2+VY3 (1)
I
z=
I
x
Z
Fig.1. Symbol of DDCC
978-1-4673-1154-0112/$31.00 20 12 IEEE
The plus and minus sign indicate whether the conveyor is
confgured as an inverting or non inverting circuit termed
DDCC- or DDCC
+
. Here Y3 terminal can be used for
biased signal processing
The CMOS DDCC circuit is shown in Fig. 2. The input
trans conductance elements are realized with two differential
stages, MI-M2 and M3-M4. The high gain stage is
composed of a current mirror (M5 and M6) which converts
the differential current to a single-ended output current
(M7).
Fig.2. CMOS non inverting DDCC
II . Low VOLTAGE CURRENT MIRROR
A current mirror is an integral part of all analog VLS I
circuits. So many structures of current mirror are available
like simple current mirror, Wilson current mirror, modifed
Wilson current mirror, Widlar current mirror, casco de
current mirror. These current mirrors have high output
voltage swing [ 4] but input voltage swing is not high enough
for low voltage applications. These current mirror uses
diode connected confguration of the input transistor. And
because of this, they require a minimum input voltage Yin of
at least one threshold (V in : V _ ).
'd
M1 1 1M2
(a)
' "_'O .
.
+ Vshi
M1 M2
(b)
Fig.3. (a) Conventional Current mirror (b) Corresponding Low
voltage current mirror
A conventional current mirror is shown in Fig. 3(a).
Ml has been used in diode connected confguration and Y
i
n
is required to pump lin into the input port. Here, Yin depends
solely on the biasing conditions of Ml, which operates in
saturation mode. The transconductance of Ml ( gmJ)
decides the input impedance. For this structure Yin is given
by (2).
(2)
ICIEV 2012
IEEE/OSAIIAPR Interational Conference on Informatics, Electronics & Vision
Lower limit of Vin is restricted to V tn threshold voltage of
NMOS. Where I =/- nCox W
I
I Ll .
A few Low Voltage Current Mirror (LVCM) topologies
have been reported in [ 5] and [ 6] which used bulk-driven
MOS FETs which suffer either from low range of input
current (lin <150fA) or low bandwidth ( B W < 100MHz).
L VCM using a voltage shifer [ 7-8] is shown in Fig. 3(b).
The CMOS implementation is shown in Fig. 4.
v_
Fig.4. LVCM Structure
I t uses MI and M2 just like conventional current mirror.
The level-shifer M4 is operated in sub-threshold region by
selecting low bias current (lbiasl). Second level-shifer M5
provides suitable bias to M3, which is used to enhance the
output impedance (Rou t). I nput current (lin) fowing through
MI is transferred to M2.
Where
V =1V
T +
ln
l
bi
,
L
4
gS4
I
Do4
W
4
I n sub threshold region the drain-current is given by (5).
_:t.
(3)
(4)
I
r
I =
DOyye
(5)
'a
L
I nput impedance of L VCM is given by Rin ;:l I gml and
output impedance Rou t;:gm4.gm2/&! 4.g
2
d
2 . The minimum
output voltage of the LVCM is given by (6).
v =V +V
uul
'2(:.t, '3(:.t,
Current transfer can be given as
(6)
(7)
Offset current I ofet is the most critical factor in low
voltage current mirror and sets the lower limit for lin. When
I ofet = 0, V
d
sl must be zero but due to level--shifing action
of the M4, M2 has some voltage at its gate. Hence a sub
threshold current will fow in M2 when lin is zero. This
current is known as offset current, and is given by (8).
Here Iofset can be tailored according to the designer's need
838
through the appropriate selection of W and L. Threshold
voltage mismatch (Vt ;:Vtn-Vt) depends on particular
CMOS technology. Even if the threshold voltages of PMOS
and NMOS are matched I ofet cannot be reduced to zero.
Simplifed L VCM structure is shown in Fig.5 for analysis
purpose.
W L I
dV
I = I
2 4 LO_
'|
ofet biasj
L W I
2 4 LO_
\__
Fig.5. Simplified L VCM
(8)
III . PROPOSED Low VOLTAGE DIFFERENTIAL
CU ENT CONVEYOR
L VCM needs less voltage across it to operate, one can use
it to make other complex circuits work at low voltage. Here
DCC is modifed to a new Low Voltage Differential Current
Conveyor (L VDCC) circuit for the low voltage application.
LVCM
Fig.6. Proposed LVDCC
Proposed L VDCC circuit is shown in Fig.6. Terminal
behavior can be given by (9).
(9)
A simplifed circuit is shown in Fig.7 using the
simplifed-L VCM shown in Fig.5. Ibiasl is bias current for
the differential amplifer MI-M2 and M3-M4 and it is
provided by M9 and MlO. Ibias2 is bias current for the
LVCM. M5, M6 and Ml4 forms simplifed LVCM. M7,
MIl and M8, Ml2 form the class-AB gain stage.
ICIEV 2012
IEEE/OSA/IAPR Interational Conference on Informatics, Electronics & Vision
Fig.7. Simplifed LVDCC
Transistor M14 is biased such that it is in sub-threshold
region, around nano-ampere order of current is pushed in to
it I bias2. We have assumed that current mirrors have unity
gain, and transistors are perfectly matched. However in
practical realizations, several nonidealities must be present.
The major factor we will consider here are fnite
transconductance gm of the transistors, and transistor
mismatch.
The relationship between Vyl , Vy2 , Vy3 and Vx
can be obtained using small signal analysis. The transistors
are replaced by equivalent circuits. To simplify discussion,
the body effect has been neglected and the two differential
pairs are assumed to be identical. By solving node
equations, we obtain
v =
g"g"cq
(V -v +v
)
gm7gmeq
+
(gd
1
2
+
gd34
+
gd6 )(gd7
+
gdj) '
1
)'2 )'3
With gmeq
= 2.gmd
lgm2 and g
d
ij = 2.g
d
illg
d
j Where &i and
gml denote the drain conductance and transconductance of
the transistor Mi, respectively and &1 is drain conductance
of the current source. I t is clear that voltage at port V
I
, V2
and V3 will be accurately transferred to port X only if
gm7 gmeq
(g
dI
2+g
d
34 +g
d6
)(g
d7+g
dl
).
Similarly terminal impedance looking into X can
be derived by setting Vyl , Vy2 and Vy3 to zero, applying a
test voltage V x at node X and calculating the current I x , the
result is
R
= (gmy + gm4 )(gd12 + gd" + gd6)
x
(10)
The terminal impedance at Z can also be derived as Rz ;:
1/(g
d8+
&
I
).
Where
Vd gm7gmeq
VYI - vY2 + VY3 (g"7 - g"q + gdl)( TIS - 1)
gd12 + gd34 + gd6
(11)
For high frequency operation, the major limitation is due to
the stray capacitance at terminal X. The high frequency
response can be expressed in terms of Vyl , Vy2 , Vy3 and V x
839
by (11). Where Cg
d
i and Cg
Sl are the gate-to-drain
capacitance and gate-to-source capacitance of device Mi.
respectively. The pole frequency is quite low and will be the
dominant frequency limiting factor of the circuit.
The input offset voltage Vos is defned as the
differential input voltage required to cause the voltage
across a resistor between terminal X and ground to be
exactly zero. Large signal analysis is performed to solve the
node equations. Then the offset voltage can be obtained as
|
-(V -| (| -| )_

(
K
2
-K
I
)_

(
K
3-K
4
)
"' - T2 T1 T3 T4
K K K K K K K K
1+ 2 2+ I 3+ 4 3+ 4
Where VTi and Ki are the threshold voltage and the
transconductance parameter of the device Mi,
respectively. The frst term is due to mismatch among the
threshold voltages, which is bias-current independent and is
a strong function of process cleanliness and uniformity. The
second term is caused by geometrical mismatch and can be
reduced by increasing W I L or reducing bias current.
I V. SIMULATION RSULTS
The design of proposed low voltage differential
current conveyor is verifed using SP I CE simulations using
0.18J.m technology from TSMC. The circuit has been
designed for minimum power dissipation and maximum
range of voltage transfer. The supply voltage is 1.5V and
I biasl =lOOJ.A and I bias2 =2 n .
Voltage transfer characteristics is shown in Fig.S. I t
transfers voltage nicely from -1.3 volt to 1.4volts.
Current transfer characteristics is shown in Fig.9,
which shows it gives almost unity current transfer ratio
( I / I x) and the transfer of current is linear from X to Z node.
1.SV;w.-----------------------------------------------._---.. ------,
_ 0'1

.

-|,y . ------------------------------,----------------------------_ . ..
-}v 1?> gy I.25v |,v
I51 7tS1-
Fig.S. Voltage transfer curve for LVDCC
Frequency response for the output current is shown
in Fig.IO, which gives bandwidth of 15MHZ.
A summary of simulation results comparing DCC (
Fig.2) and LVDCC is given below in Tablel.
The same design was also confgured as current
amplifer as shown in Fig.ll, with Ry =lOk and Rx = lk and
seen the gain (= RyRx) is very near to the calculated one.
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IEEE/OSA/IAPR Interational Conference on Informatics, Electronics & Vision
I90L
50k
.
gg ........... -,---....... --.- -- .., ... -... ......- . . -r . ..........
0k 0w4 . 0w 60 90w l00vk
o !1n)
around 12MHz. Which gives output swing from -1.3 to
+
1.4, which is nearly rail-to-rail. Proposed low voltage
circuit has been used to implement a current amplifer for
gain of lO and seen that it gives good results with bandwidth
of 1.2MHz.
This idea can be extended to make a fully
differential current conveyor (FDCC) also .
REFERENCES
[I] A.S. Sedra and K.C. Smith, "A second generation current conveyor
and its applications," IEEE Trans. on Circuit Theory, Vol. CT-17, pp.
132--134, Feb. 1970.
[2] W. Chiu, S.l. Liu, H.W. Tsao and l. Chen, "CMOS differential
difference current conveyors and their applications," lEE Proc.--
Fig.9. Current transfer Curve for LVDCC Circuits Devices Syst., Vol. 143, No. 2, pp. 91--96, April 1996.
li
COF 2
[ =
0+--_ ........ -. _ . .- ... -- ... .
IO l(
|t91
.,..
Fig.IO. Frequency Response for lout
TABLE I. COMAISION BETWEEN DCC P^L VDCC
Parameters Dee Proposed L VDee
Bias Current 100llA
Supply 3V
Voltage Transfer ratio (V,/V
Y
1) 0.95
Output Swing
Power Dissipation
Linear Range
-2.2 to 2.8V
2.48mW
83%
Fig.ll. LVDCC as current amplifier
V. CONCLUSION
100llA
1.5V
0.95
-1.3 to 1.4 V
0.75mW
90%
As low power and hence low voltage is main
design consideration now a days, a low voltage circuit for
DCC (L VDCC) has been proposed for supply voltage of
1.5V with a good performance. I t gives bandwidth of
840
[3] S.1. Liu, D.S. Wu, H.W. Tsao and J.H. Tsay, "Nonlinear circuit
applications with current conveyors," lEE Proc., Vol. 140, No. I, pp.
1--6, Feb. 1993.
[4] P.R. Gray and R.G. Meyer, Analysis and Design of Analog
Integrated Circuits. Wiley, Singapore, 1997, Ch. 4.
[5]
[6]
V.L Proddanov and M.M. Green, "CMOS current mirrors with
reduced input and output voltage requirements," Electron. Let., Vol.
32, pp. 104--105,1996.
P. Heim and M.A. Jabri,"MOS cascode current mirror biasing
circuit operating at any current level with minimal output saturation
voltage," Electron. Let., Vol. 31, pp. 690--691,1995.
[7] S.S. Rajput and S.SJamuar, "A high performance current mirror for
low voltage designs," Proc. APCCAS, Tianjin, China, Dec. 2000
[8] S.S. Rajput and S.S. Jamuar, "Low voltage, low power, high
performance current conveyors " Proc. ISCAS 200 I, Sydney 200 I.
[9] K.C. Smith and A.S. Sedra, "The current conveyor-a new circuit
building block," Proc. IEEE, Vol. 56, pp. 1368--1 369, Aug. 1968.
[10] H.W. Chua and K. Watanabe, "Wideband CMOS current conveyor,"
Electron. Lett., Vol. 32, No. 14, pp. 1245--1246, July 1996.
[11] O. Oliaei and J. Porte, "Compound current conveyor (CCIl+ and
CCIl-)," Electron. Lett., Vol. 33, No. 4, pp. 253--254, Feb. 1997.
[12] Th. Laopoulos, S. Siskos, M. Bafleur and Ph. Givelin, "CMOS
current conveyor," Electron. Lett., Vol. 28, No. 24, pp. 2261--2262,
Nov. 1992.
[13] A.S. Sedra, G.W. Roberts and F.Gohh, "The current conveyor:
history, progress and new results," IEE Proc., Vol. 137, pp. 78--87,
April 1990.
[14] A. Awad and A.M. Soliman, "New CMOS Realization of the CClI
," IEEE Trans. on Circuits and Systems-H, Vol. 46, No. 4, pp. 460--
463, April 1999.
[15] Hassan O. Elwan and A.M. Soliman, "Low--Voltage Low--Power
CMOS Current Conveyors," IEEE Trans. on Circuits and Systems-I,
Vol. 44, No. 9, pp. 828--835, Sept. 1997.
[16] B. Wilson, "Recent developments in current conveyors and current
mode circuits," lEE Proc., Vol. 137, No. 2, pp. 63--77, April 1990.
Sanjay K. Kasodniya received the B.E. (Bachelor
of Engineering) degree in Electronics
Communications from M.B.M. Engineering College
Jodhpur, India in 1998, ad M.Tech. from liT
(India Institute of Technology )Delhi in Integrated
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Electronics Circuits in 200 I. He joined ISRO (India Space Research
Orgaisation) in 2002. He is currently working at Space Applications Centre
(ISRO) Ahmedabad, in feld of design of Mixed signal ASIC FPGA based
systems for Microwave Payloads of diferent satellites of [SRO. He in pursuing
PhD. from DAIlCT, Gandhinagar, India.
Dr. Dipanlr Nagchoudhuri is a Professor at DA
nCT. Previously, he was at llT Delhi for about thirty
years, and a Professor there fom 1982. During this
period, he held the position of Philips Chair Professor
for about two years. He has also been a visiting
faculty to University of Malaya, Kuala Lumpur, a
Visiting Professor at Siemens AG, Munich, ad at
Instituto Nacional de Astrofsica, Optica y
Electronica, Mexico. He has authored three books:
Semiconductor Devices ([989), Microelectronics
Technology (1998) ad Microelectronic Devices
(2001). He has published numerous papers in National and Interationa
Conferences. He has guided about a dozen PhD theses ad taught undergraduate
and graduate courses in electronics. He was awarded the best teacher award in
1980-1981 by the EE Students Societ. His research interests are in CMOS
technology and circuits.
Nilesh W. Desai received the B.E. (Bachelor of
Engineering) degree in Electronics ad
Communication Engineering (1986) ad is a gold
medallist of 1986 batch from L.D.College of
Engineering, Gujarat University,Ahmedabad, India.
He joined Space Applications Centre, ISRO,
Ahmedabad, in 1986. He has contributed extensively
towards ISRO's various airbore ad spacebore
Radar Projects. Presently, he is Group Director of Microwave Sensors Digital
Electronics Group (MSDG) ad Microwave Sensors Trans receiver Group
(MSTG) of SAC/ISRO, Ahmedabad.
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