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Embedded Systems
5 - Development of microprocessor-based systems

Architectures and components Debugging Manufacturing Testing

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Example

Maths is not everything

Development of Microprocessor-based Systems Architectures and Components

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Software architecture

Functional description must be broken into pieces: division among people; conceptual organization; performance;
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testability; maintenance.

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Hardware and software architectures

Hardware and software are intimately related: software doesnt run without hardware; how much hardware you need is determined by the software requirements:
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speed; memory.

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Software components

Need to break the design up into pieces to be able to write the code. Some component designs come up often. A design pattern is a generic description of a component that can be customized and used in different circumstances.

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Software state machine

State machine keeps internal state as a variable, changes state based on inputs. Uses:
control-dominated code; reactive systems.
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State machine specication

in1=1/x=a

B
r=1/out1=0

r=0/out2=1

in1=0/x=b

s=0/out1=0
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C
s=1/out1=1

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C code structure

Current state is kept in a variable. State table is implemented as a switch.

Cases define states. States can test inputs.
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Switch is repeatedly evaluated in a while loop.

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Software design techniques

Want to develop as much code as possible on a standard platform:

friendlier programming environment; easier debugging.

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May need to devise software stubs to allow testing of software elements without the full hardware/software platform.

Host/target design

Use a host system to prepare software for target system:

target system
serial line

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host system

Host-based tools

Cross compiler:
compiles code on host for target system.

Cross debugger:
displays target state, allows target system to be controlled.
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Evaluation boards

Designed by CPU manufacturer or others. Includes CPU, memory, some I/O devices. May include prototyping section. CPU manufacturer often gives out evaluation board netlist---can be used as starting point for your custom board design.

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Adding logic to a board

Programmable logic devices (PLDs) provide low/medium density logic. Field-programmable gate arrays (FPGAs) provide more logic and multi-level logic.
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Application-specific integrated circuits (ASICs) are manufactured for a single purpose.

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The PC as a platform

Advantages:
cheap and easy to get; rich and familiar software environment.

Disadvantages:
requires a lot of hardware resources;
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not well-adapted to real-time.

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Development of Microprocessor-based Systems Debugging Embedded Systems

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Debugging embedded systems

Challenges:
target system may be hard to observe; target may be hard to control; may be hard to generate realistic inputs; setup sequence may be complex.
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Software debuggers

A monitor program residing on the target provides basic debugger functions. Debugger should have a minimal footprint in memory. User program must be careful not to destroy debugger program, but , should be able to recover from some damage caused by user code.

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Breakpoints

A breakpoint allows the user to stop execution, examine system state, and change state. Replace the breakpointed instruction with a subroutine call to the monitor program.
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ARM breakpoints

0x400 MUL r4,r6,r6

0x400 0x404 ADD r2,r2,r4 0x404 0x408 ADD r0,r0,#1 0x408 0x40c 0x40c B loop uninstrumented code
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MUL r4,r6,r6 ADD r2,r2,r4 ADD r0,r0,#1 BL bkpoint

code with breakpoint

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Breakpoint handler actions

Save registers. Allow user to examine machine. Before returning, restore system state.
Safest way to execute the instruction is to replace it and execute in place. Put another breakpoint after the replaced breakpoint to allow restoring the original breakpoint.

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In-circuit emulators

A microprocessor in-circuit emulator is a specially-instrumented microprocessor. Allows you to stop execution, examine CPU state, modify registers.
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Logic analyzers

A logic analyzer is an array of low-grade oscilloscopes:

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Logic analyzer architecture

UUT
system clock

sample memory vector address controller

microprocessor

clock gen
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state or timing mode keypad display

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- Checking memory (e.g. cache misses) or I/O access - Checking execution time (marks needed)

How to exercise code

Run on host system. Run on target system. Hardware/Software verification

Run in instruction-level simulator. Run on cycle-accurate simulator (e.g. SoC).
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Run in hardware/software co-simulation environment.

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Development of Microprocessor-based Systems Manufacturing

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Manufacturing testing

Goal: ensure that manufacturing produces defect-free copies of the design. Can test by comparing unit being tested to the expected behavior.
But running tests is expensive.

Maximize confidence while minimizing testing cost.

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Design for testability

take manufacturing test into account during design

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Testing concepts

Yield: proportion of manufactured systems that work.

Proper manufacturing maximizes yield. Proper testing accurately estimates yield.

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Field return: defective unit that leaves the factory.

Faults

Manufacturing problems can be caused by many things. Fault model: model that predicts effects of a particular type of fault. Fault coverage: proportion of possible faults found by a set of test.
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Having a fault model allows us to determine fault coverage.

Software vs. hardware testing

When testing code, we have no fault model.

We verify the implementation, not the manufacturing. Simple tests (e.g., Error Correcting Codes) work well to verify software manufacturing.

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Hardware requires manufacturing tests in addition to implementation verification.

Hardware fault models

Stuck-at 0/1 fault model:

output of gate is always 0/1.

01
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Combinational testing

Every gate can be stuck-at-0, stuck-at-1. Usually test for single stuck-at-x faults
One fault at a time. Multiple faults can mask each other.

We can generate a test for a gate by:

controlling the gates input; observing the gates output through other gates.
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Sequential testing

A state machine is combinational logic + registers. Sequential testing is considerably harder.

A single stuck-at fault affects the machine on every cycle.
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Fault behavior on one cycle can be masked by same fault on other cycles.

Scan chains

A scannable register operates in two modes:

normal; scan---forms an element in a shift register.

Using scan chains reduces sequential testing to combinational testing.

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Unloading/unloading scan chain is slow. May use partial scan.

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Test generation

Automatic test pattern generation (ATPG) programs: produce a set of tests given the logic structure. Some faults may not be testable--redundant.
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redundancy may have been added for avoiding glitches Timeout on a fault may mean hard-to-test or untestable.

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Boundary scan

Simplifies testing of multiple chips on a board.

Registers on pins can be configured as a scan chain (JTAG standard interface)
Test Access Port

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JTAG

Also used as an OCDM interface

e.g. MSP430 responds to various commands sent over JTAG:
Set watchpoint and breakpoint triggers Poll CPU status (e.g., if halted at a breakpoint)
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Poll the state-storage buffer (for information stored at watchpoint trigger) Poll the program counter (PC)

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Development of Microprocessor-based Systems Example

Designing an Alarm Clock

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Alarm clock interface

Alarm on PM

Alarm off buzzer

light
set time
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Alarm ready
set alarm hour minute

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button

Operations

Set time: hold set time, depress hour, minute. Set alarm time: hold set alarm, depress hour, minute. Turn alarm on/off: depress alarm on/off.
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Alarm clock requirements

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Alarm clock class diagram

Lights*

Display

1 1

Mechanism
1

Buttons*

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Speaker*

Alarm clock physical classes

Lights*

Buttons*

Speaker*

digit-val() digit-scan() alarm-on-light() PM-light()

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set-time(): boolean set-alarm(): boolean alarm-on(): boolean alarm-off(): boolean minute(): boolean hour(): boolean

buzz()

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Display class

Display time[4]: integer alarm-indicator: boolean PM-indicator: boolean set-time() alarm-light-on() alarm-light-off() PM-light-on() PM-light-off()

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Mechanism class

Mechanism Seconds: integer PM: boolean tens-hours, ones-hours: integer tens-minutes, ones-minutes: integer alarm-ready: boolean alarm-tens-hours, alarm-ones-hours: integer alarm-tens-minutes, alarm-ones-minutes: integer
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scan-keyboard() update-time()

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Update-time behavior

update seconds with rollover Rollover? T update hh:mm with rollover F

display.set-time(current time)

Time >= alarm and alarm-on? T alarm.buzzer(true)

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AM->PM PM=true

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PM->AM PM=false

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Scan-keyboard behavior

compute button activations

alarm-ready= true
Alarm-on Set-time and not set-alarm and hours Set-time and not setalarm and minutes

only one activation

Alarm-off

Increment time tens w. rollover and AM/PM

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alarm-ready= false alarm.buzzer(false)

save button states

Increment time ones w. rollover and AM/PM

System architecture

Includes:
periodic behavior (clock); aperiodic behavior (buttons, buzzer activation).

Two major software components:

interrupt-driven routine updates time;
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foreground program deals with buttons, commands.

Interrupt-driven routine

Timer probably cant handle one-minute interrupt interval. Use software variable to convert interrupt frequency to seconds.
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Foreground program

Operates as while loop: while (TRUE) { read_buttons(button_values); process_command(button_values);

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check_alarm(); }

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Testing

Component testing:
test interrupt code on the platform; can test foreground program using a mock-up.

System testing:
relatively few components to integrate;
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check clock accuracy; check recognition of buttons, buzzer, etc.

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