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Embedded Systems
4 - Hardware Architecture

CPU Input/Output mechanisms Memory Buses and Aux I/O Input/Output interfaces
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Power Management

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CPU Buses

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CPU bus

Connects CPU to:

memory; devices.

Protocol controls communication between entities.

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Bus protocol

Determines who gets to use the bus at any particular time. Governs length, style of communication.

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Four-cycle handshake

Basis of many bus protocols. Uses two wires:

enq (enquiry); ack (acknowledgment).
enq
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dev1

data ack

dev2

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Four-cycle example

enq 1 2 3

data

ack
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time

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Typical bus signals

Clock. R/W: true when bus is reading. Address: a-bit bundle. Data: n-bit bundle. Data ready.
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Timing diagrams
one A zero 10 ns rising falling

stable
B

changing

C
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time

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Typical bus timing for read

CPU:
set R/W=1; asserts address, address enable.

Memory:
asserts data; asserts data ready.
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CPU:
deasserts address, address enable.

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Bus read state diagram

Get data

Done

See ack

Adrs

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Wait

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Transaction types

Wait state:
state in a bus transaction to wait for acknowledgment.

Disconnected transfer:
bus is freed during wait state.

Burst:
multiple transfers.
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Auxiliary Mechanisms Timers

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Timers and counters

Very similar:
a timer is incremented by a periodic signal; a counter is incremented by an asynchronous, occasional signal.

Rollover causes interrupt.

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Timers

The main applications of timers are to:

generate events of xed time-period allow periodic wakeup from sleep of the device count transitional signal edges replace delay loops allowing the CPU to sleep between operations, consuming less power maintain synchronization clocks
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Timers (MSP430)

System timing is fundamental for real-time applications The MSP430F2274 has 2 timers, namely Timer_A and Timer_B The timers may be triggered by internal or external clocks Timer_A and Timer_B also include multiple independent capture/compare blocks that are used for applications such as timed events and Pulse Width Modulation (PWM)

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Timers (MSP430) - TxCTL Control Register

15 14 13 12 11 10 9 8 7
IDx

5
MCx

3
-

2
TxCLR

1
TxIE

0
TxIFG

(Used by Timer_B)

TxSSELx

Bit
9-8 TxSSELx

Description
Timer_x clock source: 0 0 ! TxCLK 0 1 ! ACLK 1 0 ! SMCLK 1 1 ! INCLK 00!/1 01!/2 10!/4 11!/8 0 0 ! Stop mode 0 1 ! Up mode 1 0 ! Continuous mode 1 1 ! Up/down mode

7-6

IDx

Clock signal divider:

5-4

MCx

Clock timer operating mode:

2
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TxCLR TxIE TxIFG

Timer_x clear when TxCLR = 1 Timer_x interrupt enable when TxIE = 1 Timer_x interrupt pending when TxIFG = 1

1 0

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Timers (MSP430) - 4 Modes of Operation

Timer reset by writing a 0 to TxR Clock timer operating modes:

MCx Mode
00 01 10 11
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Description
The timer is halted. The timer repeatedly counts from 0x0000 to the value in the TxCCR0 register. The timer repeatedly counts from 0x0000 to 0xFFFF. The timer repeatedly counts from 0x0000 to the value in the TxCCR0 register and back down to zero.

Stop Up Continuous Up/down

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Timers (MSP430) - Timer Modes

Up Mode

Continuous Mode

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Up/Down Mode

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Timers (MSP430): Timer_A Example

Use Timer A to interrupt every 1 ms

SMCLK .set TIME_1MS .set TA_CTL TA_FREQ clr.w mov.w mov.w bis.w jmp .set .set 1200000 1000 ; 1200000 clocks / second ; 1 ms = 1/1000 s TASSEL_2+ID_0+MC_1+TAIE ; SMCLK, /1, UP, IE SMCLK/TIME_1MS ; clocks / 1 ms ; ; ; ; ; reset timerA set timerA control reg set interval (frequency) enter LPM0 w/interrupts will never get here!

&TAR #TA_CTL,&TACTL #TA_FREQ,&TACCR0 #LPM0+GIE,SR $

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TA_isr: ; timer A ISR bic.w #TAIFG,&TACTL ; acknowledge interrupt ; <<add interrupt code here>> reti .sect .word ".int08" TA_isr ; timer A section ; timer A isr

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Watchdog timer

Watchdog timer is periodically reset by system timer. If watchdog is not reset, it generates an interrupt to reset the host.
interrupt

host CPU
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reset

watchdog timer

Watchdog Timer (MSP430)

The primary function of the watchdog timer+ (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

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Watchdog Timer (MSP430)

Features of the watchdog timer+ module include:

Four software-selectable time intervals Watchdog mode Interval mode Access to WDT+ control register is password protected Control of RST/NMI pin function Selectable clock source
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Can be stopped to conserve power Clock fail-safe feature

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Watchdog Timer (MSP430) - Watchdog Power-up

After a power-up clear (PUC), the WDT+ module is automatically configured in the watchdog mode with an initial 32768 clock cycle reset interval using the DCOCLK. The user must setup or halt the WDT+ prior to the expiration of the initial reset interval.

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Watchdog (MSP430) example: stoping it

In Assembly
RESET: ! mov.w ! mov.w ! bis.b ! mov.w ...

passwd = 0x5A
; Initialize stack pointer ; Stop WDT ; Set P1.0-3 output

#0x0300,SP #WDTPW+WDTHOLD,&WDTCTL #0x0f,&P1DIR #0,r14

In C

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Auxiliary I/O Buttons & Displays

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Switch debouncing

A switch must be debounced to multiple contacts caused by eliminate mechanical bouncing:

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Encoded keyboard

An array of switches is read by an encoder. N-key rollover remembers multiple key depressions. row
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LED

Must use resistor to limit current:

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Auxiliary I/O DAC & ADC

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Digital-to-analog conversion

Use resistor tree:

R

bn bn-1 bn-2
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Vout

2R 4R 8R

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bn-3

Flash A/D conversion

N-bit result requires 2n comparators: Vin

encoder

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...

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Dual-slope conversion

Use counter to time required to charge/ discharge capacitor. Charging, then discharging eliminates nonlinearities.

Vin
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timer

Sample-and-hold

Required in any A/D: Vin

converter

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