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XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011
www.ti.com
FEATURES
EASY-TO-DESIGN INPUT/OUTPUT RANGES: 0mA20mA, 4mA20mA, 5mA25mA AND VOLTAGE OUTPUTS NONLINEARITY: 0.002% LOW OFFSET DRIFT: 1 V/C ACCURACY: 0.015% SINGLE-SUPPLY OPERATION WIDE SUPPLY RANGE: 7V to 44V OUTPUT ERROR FLAG (EF) OUTPUT DISABLE (OD) ADJUSTABLE VOLTAGE REGULATOR: 3V to 15V
DESCRIPTION
The XTR111 is a precision voltage-to-current converter designed for the standard 0mA20mA or 4mA20mA analog signals, and can source up to 36mA. The ratio between input voltage and output current is set by the single resistor RSET. The circuit can also be modified for voltage output. An external P-MOSFET transistor ensures high output resistance and a broad compliance voltage range that extends from 2V below the supply voltage, VVSP, to voltages well below GND. The adjustable 3V to 15V sub-regulator output provides the supply voltage for additional circuitry. The XTR111 is available in MSOP and DFN surface-mount packages.
24V 1 XTR111 REGF Regulator Out 5 REGS 4
(1)
APPLICATIONS
UNIVERSAL VOLTAGE-CONTROLLED CURRENT SOURCE CURRENT OR VOLTAGE OUTPUT FOR 3-WIRE SENSOR SYSTEMS PLC OUTPUT PROGRAMMABLE DRIVER CURRENT-MODE SENSOR EXCITATION
VSP I- Mirror
OD EF IS
9 8 2
15W S G D Q1
Q2
3V ISET Signal Input 6 VIN VG 3
15W
Load
10nF
GND 10 7
( Load Ground)
RSET
IOUT = 10
IOUT = 10 ISET
NOTE: (1) See Application Information, External Current Limit Circuits for other options.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners.
Copyright 20062011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the device product folder at www.ti.com.
(2)
UNIT V V V V V mA
+44 0.5 to +14 (VVSP) 5.5 to (VVSP) + 0.5 0.5 to (VVSP) + 0.5 0.5 to (VVSP) + 0.5 25
Voltage at REGS, REGF, VIN, OD, EF Voltage at REGF, VG Current into any pin (3)
(4) (5)
Output Short-Circuit Duration (6): VG REGF Operating Temperature Storage Temperature Electrostatic Discharge Rating (HBM) Continous to common and VVSP Continous to common and VVSP 55 to +125 65 to +150 2000 C C V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Refer to the Package Option Addendum at the end of this document for lead temperature ratings. Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails must be current limited. The IS pin current absolute maximum rating is +25mA and 50mA. See the following sections Explanation of Pin Functions, External MOSFET, and Voltage Regulator in Application Information regarding safe voltage ranges and currents. See text in Application Information regarding safe voltage ranges and currents.
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
ELECTRICAL CHARACTERISTICS
Boldface limits apply over the specified temperature range: TA = 40C to +85C. All specifications at TA = +25C, VVSP = +24V, RSET = 2.0k, REGF connected to REGS; OD = Low, External FET connected, unless otherwise noted.
XTR111 PARAMETER TRANSMITTER Transfer Function Specified Output Current Current Limit for Output Current Nonlinearity, IOUT/ISET Offset Current vs Temperature vs Supply, VVSP Span Error, IOUT/ISET vs Temperature vs Supply (1) Output Resistance Output Leakage Input Impedance (VIN) Input Bias Current (VIN) Input Offset Voltage (2) vs Temperature Input Voltage Range (5) Noise, Referred to Input (2) Dynamic Response (1) (2) (3) (4) (5) VVIN 0.1Hz to 10Hz; IOUT = 4mA IB VOS VVIN = 20mV From Drain of QEXT OD = high
(4) (2) (1) (2) (2) (3)
CONDITIONS
MIN
TYP
MAX
UNIT
IOUT = 10 VVIN/RSET IOUT Specified Performance (1) Derated Performance (2) 0.1mA to 25mA 0.1mA to 36mA IOS IOUT = 4mA (1) 8V to 40V Supply 0.1mA to 25mA 0.1 0 to 36 42 6 0.002 0.004 0.002 0.0002 0.0001 0.015 5 0.0001 >1 <1 2.4/30 15 0.3 1.5 0 to 12 2.5 See Dynamic Performance Section 25 1.5 0.02 0.001 0.005 0.1 0.02 25 mA mA mA % of Span % of Span % of Span % of Span/C % of Span/V % of Span ppm/C % of Span/V G A G/pF nA mV V/C V VPP
Includes input amplifier, but excludes RSET tolerance. Offset current is the deviation from the current ratio of ISET to IIS (output current). See Typical Characteristics. Span is the change in output current resulting from a full-scale change in input voltage. Within compliance range limited by (+VVSP 2V) +VDS required for linear operation of QEXT. See Application Information, Input Voltage section.
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011 www.ti.com
CONDITIONS RLOAD = 5k
MIN 2.85
MAX 3.15
3 0.01 21
mV/mA mV/V mA mA
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
PIN CONFIGURATIONS
DGQ PACKAGE MSOP-10 TOP VIEW
VSP IS VG REGS REGF 1 2 3 4 5 Exposed Thermal Die Pad on Underside. (Must be connected to GND) 10 9 8 7 6 GND OD EF SET VIN VSP IS VG REGS REGF Pad Pad 1 2 3 4 5 Exposed Thermal Die Pad on Underside. (Must be connected to GND) 10 9 8 7 6 GND OD EF SET VIN
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 9 10 Pad NAME VSP IS VG REGS REGF VIN SET EF OD GND Pad FUNCTION Positive Supply Source Connection Gate Drive Regulator Sense Regulator Force Input Voltage Transconductance Set Error Flag (Active Low) Output Disable (Active High) Negative Supply Exposed Thermal Pad must be connected to GND
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011 www.ti.com
TYPICAL CHARACTERISTICS
At TA = +25C and VVSP = +24V, unless otherwise noted.
QUIESCENT CURRENT vs SUPPLY VOLTAGE
550 530 700 650
510 490 470 450 430 410 390 370 350 Supply Voltage (V)
600 550 500 450 400 350 300 -75 -50 -25 0 25 50 75 100 125 Temperature (C)
PSRR (dB)
Gain (dB)
IR Noise (VRMS/Hz)
1s/div
10m
1mV/div
1m
100n
Figure 5.
Figure 6.
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
Population
Population
-0.01 -0.009 -0.008 -0.007 -0.006 -0.005 -0.004 -0.003 -0.002 -0.001 0 0.001 0.002 0.003 0.004 0.005 0.006 0.007 0.008 0.009 0.01
Nonlinearity (%)
Figure 7.
NONLINEARITY vs TEMPERATURE
0.03 0.02 0.1mA to 25mA
Nonlinearity (%)
0 -0.01 -0.02 -0.03 -75 -50 -25 0 25 50 75 100 125 Temperature (C) 4mA to 20mA
Population
0.01
Figure 9.
4mA to 20mA 0 -0.05 0.1mA to 25mA -0.10 -0.15 -75 -50 -25 0 25 50 75 100 125 Temperature (C)
Population
0.05
-10
Figure 11.
-0.1 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
Gain Error (%)
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 10. GAIN ERROR DRIFT DISTRIBUTION (IOUT = 0.1mA to 25mA; T = 55C to +125C)
-9
-8
-7
-6
-5
-4
-3
-2
-1
Figure 12.
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011 www.ti.com
Nonlinearity (%)
Nonlinearity (%)
4 8 12 IOUT (mA) 16
Figure 14. INPUT VOLTAGE RANGE LIMIT TO THE POSITIVE SUPPLY vs TEMPERATURE
VVSP = 12V
Nonlinearity (%)
0.004 0.002 0.000 -0.002 -0.004 -0.006 -0.008 -0.010 0 5 10 15 20 IOUT (mA) 25 30 35 40
2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 -75 -50 -25 0 25 50 75 100 125 Temperature (C)
Figure 15. OUTPUT SWING OF THE VOLTAGE ON IS PIN (VIS) vs OUTPUT CURRENT
3.0 2.5 1.8 1.7 1.6 20mA
1.5 1.4 1.3 4mA 1.2 1.1 1.0 -75 -50 -25 0 25 50 75 100 125 Temperature (C) 10mA
Figure 17.
Figure 18.
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
Population
Population
-5
-4
-3
-2
-1
VOS (mV)
VOS (mV/C)
60
47 46 45 44 43 42 41
Population
36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Figure 23.
Figure 24.
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011 www.ti.com
Population
2.850 2.865 2.880 2.895 2.910 2.925 2.940 2.955 2.970 2.985 3 3.015 3.030 3.045 3.060 3.075 3.090 3.105 3.120 3.135 3.150
Population
0
10
20
30
40
50
60
70
80
More
Figure 25. REGULATOR INPUT BIAS CURRENT DISTRIBUTION (Current into REGS Pin)
Figure 26. REGULATOR INPUT BIAS CURRENT DRIFT DISTRIBUTION (Drift of Current into REGS Pin)
-4.0 -3.6 -3.2 -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
Population
0
Population
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
3.02 3.01 3.00 2.99 2.98 2.97 2.96 2.95 0 5 10 15 20 25 30 35 40 45 50 Supply Voltage (V)
3.02 3.01 3.00 2.99 2.98 2.97 2.96 2.95 -75 -50 -25 0 25 50 75 100 125 Temperature (C)
Figure 29.
Figure 30.
10
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
STEP RESPONSE: VFS = 2.5V, RSET = 1.25k, RLD = 600 (Rising Edge Depends on CGATE at VG Pin)
Photo taken with CGATE = 130pF
5V/div
10V/div
5V/div
2V/div
10ms/div
10ms/div
Figure 31. REGULATOR LOAD TRANSIENT (VREG Gain = 1V, VREGF = 3V, CL = 470nF, ILOAD = 3mA 0.3mA)
Figure 32. REGULATOR LOAD TRANSIENT (VREG Gain = 4V, VREGF = 12V, CL = 470nF, ILOAD = 3mA 0.3mA)
2V/div 10mV/div
10mV/div 1V/div
40ms/div
40ms/div
Figure 34.
Figure 35.
11
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011 www.ti.com
APPLICATION INFORMATION
The XTR111 is a voltage-controlled current source capable of delivering currents from 0mA to 36mA. The primary intent of the device is to source the commonly-used industrial current ranges of 0mA20mA or 4mA20mA. The performance is specified for a supply voltage of up to 40V. The maximum supply voltage is 44V. The voltage-to-current ratio is defined by an external resistor, RSET; therefore, the input voltage range can be freely set in accordance with the application requirement. The output current is cascoded by an external P-Channel MOSFET transistor for large voltage compliance extending below ground, and for easy power dissipation. This arrangement ensures excellent suppression of typical interference signals from the industrial environment because of the extremely high output impedance and wide voltage compliance. An error detection circuit activates a logic output (error flag) in case the output current cannot correctly flow. It indicates a wire break, high load resistor, or loss of headroom for the current output to the positive supply. The output disable (OD) provided can be used during power-on, multiplexing and other conditions where the output should present no current. It has an internal pull-up that causes the XTR111 to come up in output disable mode unless the OD pin is tied low. The onboard voltage regulator can be adjusted between 3V to 15V and delivers up to 5mA load current. It is intended to supply signal conditioning and sensor excitation in 3-wire sensor systems. Voltages above 3V can be set by a resistive divider. Figure 36 shows a basic connection for the XTR111. The input voltage VVIN reappears across RSET and controls 1/10 of the output current. The I-Mirror has a precise current gain of 10. This configuration leads to the transfer function: IOUT = 10 (VVIN/RSET) The output of the voltage regulator can be set over the range of 3V to 12V by selecting R1 and R2 using the following equation. VREGF = 3V (R1 + R2)/R2 (1)
VVSP = 24V Supply C1 1 VSP REGF 5 I-Mirror OD EF IS R1 5.6kW 4 9 8 2 15W S G D 3V R2 8.2kW 5V 6 VIN ( Load Ground) Signal Source (Sensor or DAC, for example) 10 Load 15W 10nF Q1 (Pull Low for Normal Operation)
(1)
REGS Q2 VG 3
GND 7
SET V (R )
VIN
RSET
IOUT = 10
SET
Figure 36. Basic Connection for 0mA to 20mA Related to 0V to 5V Signal Input. The Voltage Regulator is Set to 5V Output
12
Copyright 20062011, Texas Instruments Incorporated
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
EF : The active low error flag (logic output) is intended for use with an external pull-up to logic-high for reliable operation when this output is used. However, it has a weak internal pull-up to 5V and can be left unconnected if not used. OD: This control input has a 4A internal pull-up disabling the output. A pull-down or short to GND is required to activate the output. Controlling OD reduces output glitches during power-on and power-off. This logic input controls the output. If not used, connect to GND. The regulator is not affected by OD.
13
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011
IS R6 15W Q2 VG Q1 Q2 R7 15W IOUT C3 10nF VG R8 5kW Q3 R6 15W
www.ti.com
IS
the OD pin high disables the gate driver and closes a switch connecting an internal 3k resistor from the VSP pin to the VG pin. This resistor discharges the gate of the external FET and closes the channel; see Figure 38. Table 1 lists some example devices in SO-compatible packages, but other devices can be used as well. Avoid external capacitance from IS. This capacitance could be compensated by adding additional capacitance from VG to IS; however, this compensation may slow the output down. The drain-to-source breakdown voltage should be selected high enough for the application. Surge voltage protection might be required for negative over-voltages. For positive over-voltages, a clamp diode to the 24V supply is recommended, protecting the FET from reversing.
VSP OD Switch 3kW VG
Q1
EXTERNAL MOSFET
The XTR111 delivers the precise output current to the IS pin. The voltage at this pin is normally 1.4V below VVSP. This output requires an external transistor (QEXT) that forms a cascode for the current output. The transistor must be rated for the maximum possible voltage on VOUT and must dissipate the power generated by the current and the voltage across it. The gate drive (VG) can drive from close to the positive supply rail to 16V below the positive supply voltage (VVSP). Most modern MOSFETs accept a maximum VGS of 20V. A protection clamp is only required if a large drain gate capacitance can pulse the gate beyond the rating of the MOSFET. Pulling
16V
GND
Figure 38. Equivalent Circuit for Gate Drive and Disable Switch
14
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
DYNAMIC PERFORMANCE
The rise time of the output current is dominated by the gate capacitance of the external FET. The accuracy of the current mirror relies on the dynamic matching of multiple individual current sources. Settling to full resolution may require a complete cycle lasting around 100s. Figure 39 shows an example of the ripple generated from the individual current source values that average to the specified accuracy over the full cycle.
The output glitch magnitude depends on the mismatch of the internal current sources. It is approximately proportional to the output current level and scales directly with the load resistor value. It will differ slightly from part to part. The effects of filtering the output are shown in Figure 40 and Figure 41.
External FET
50mV/div
No Filter
500W
20ms/div
External FET
50mV/div
Load Capacitor
CF 10nF
500W
20ms/div
15
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011 www.ti.com
5mV/div
RF 10kW CF 10nF
NOTE: Scale has been changed from Figure 38 and Figure 39.
500W
20ms/div
INPUT VOLTAGE
The input voltage range for a given output current span is set by RSET according to the transfer function. Select a precise and low drift resistor for best performance, because resistor drift directly converts into drift of the output current. Careful layout must also minimize any series resistance with RSET and the VIN reference point. The input voltage is referred to the grounding point of RSET. Therefore, this point should not be distorted from other currents. Assuming a 5V full-scale input signal for a 20mA output current, RSET is 2.5k. A resistance uncertainty of just 2.5 already degrades the accuracy to below 0.1%. The linear input voltage range extends from 0V to 12V, or 2.3V below the positive supply voltage (whichever is smaller). The lowest rated supply voltage accomodates an input voltage range of up to 5V. Potential clipping is not detected by an error signal; therefore, safe design guard banding is recommended. Do not drive the input negative (referred to GND) more than 300mV. Higher negative voltages turn on the internal protection diodes. Insert a resistor in series with the input if negative signals can occur eventually during power-on or -off or during other transient conditions. Select a resistor value limiting the possible current to 0.3mA. Higher currents are non-destructive (see Absolute Maximum Ratings), but they can produce output current glitches unless in disable mode.
16
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
More protection against negative input signals is provided using a standard diode and a 2.2k resistor, as shown in Figure 42.
2.2kW V-Signal VIN 1N4148
4mA20mA OUTPUT
The XTR111 does not provide internal circuits to generate 4mA with 0V input signal. The most common way to shift the input signal is a two resistor network connected to a voltage reference and the signal source, as shown in Figure 43. This arrangement allows easy adjustment for over-and under-range. The example assumes a 5V reference (VREF) that equals the full-scale signal voltage and a signal span of 0V to 5V for 4mA to 20mA (IMIN to IMAX) output. The voltage regulator output or a more precise reference can be used as VREF. Observe the potential drift added by the drift of the resistors and the voltage reference.
R1 40kW
5V Reference
120kW
Reference Voltage 5V
Input Voltage 0V to 5V
R2 10kW
VIN 1V to 5V
Figure 44. Input Voltage Level Shift for 0mA Output Current
Figure 43. Resistive Divider for IMIN to IMAX Output (4mA to 20mA) with 0V to VFS Signal Source
17
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011 www.ti.com
VOLTAGE REGULATOR
The externally adjustable voltage regulator provides up to 5mA of current. It offers drive (REGF) and sense (REGS) to allow external setting of the output voltage as shown in Figure 45. The sense input (REGS) is referenced to 3.0V representing the lowest adjustable voltage level. An external resistor divider sets VREGF. VREGF = VREGS (R1 + R2)/R2 Table 2 provides example values for the regulator adjustment resistors. Table 2. Examples for the Resistor Values Setting the Regulator Voltage
VREGF (1) 3V 3.3V 5V 12.4V R1 0 3.3k 5.6k 27k R2 33k 8.2k 8.6k
The voltage at REGF is limited by the supply voltage. If the supply voltage drops close to the set voltage, the driver output saturates and follows the supply with a voltage drop of less than 1V (depending on load current and temperature). For good stability and transient response, use a load capacitance of 470nF or larger. The bias current into the sense input (REGS) is typically less than 1A. This current should be considered when selecting high resistance values for the voltage setting because it lowers the voltage and produces additional temperature dependence. The REGF output cannot sink current. In case of supply voltage loss, the output is protected against the discharge currents from load capacitors by internal protection diodes; the peak current should not exceed 25mA. If the voltage regulator output is not used, connect REGF to REGS (the 3V mode) loaded with a 2.2nF capacitor. Alternatively, overdrive the loop pulling REGS high (see Figure 45d).
3V
REGF
REGF
REGS
REG REGS
470nF 3V
R2 8.2kW 3V
(a) VSP
(b)
5V Source
REGS
REGS 3V
18
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
9 8 2 15W S G D Q1
5V C2 470nF R1 2kW
REGF
R2 3kW 3V
Q2 VG 3
10nF
Digital I/O
GND 10 7
Figure 46. Current Using 0V to 5V Input from a 12-Bit Digital-to-Analog Converter DAC7551
1 VSP
OD Current Mirror EF IS
9 8 2 15W S G D Q1
5V C2 470nF R1 2kW
REGF
REGS
(1)
R2 3kW 3V R3 2kW 6
Q2 VG 3
15W VIN
10nF
Digital I/O
SET R4 817.2kW 7
GND 10 Load CLOAD RLOAD 0mA to 20mA output for 10mV to 4096mV input or a code of 160b to 65536b
Figure 47. Precision Current Output with Signal from 16-Bit DAC. Input Offset Shifted (R4) by 10mV for Zero Adjustment Range
19
XTR111
SBOS375C NOVEMBER 2006 REVISED JUNE 2011 www.ti.com
1 VSP
OD Current Mirror EF IS
9 8 2 15W S G D Q1
REGF
REGS
(1)
Q2 VG 3V 3
10nF
GND 10 7
SET Load SW1 RSET 5kW Current (open) or Voltage (close) Output CLOAD RLOAD
When output disabled and SW1 is closed, pin 7 may generate an error signal.
(a)
(b)
R4 100W +24V
3V C2 470nF
REGS
6V C2 470nF R2 10kW
REGS
NOTE: (1) Resistor R4 can be calculated to protect Q2 from over current in fault conditions.
Figure 49. Voltage Regulator Current Boost Using a Standard NPN Transistor
20
XTR111
www.ti.com SBOS375C NOVEMBER 2006 REVISED JUNE 2011
NOTE: All thermal models have an accuracy variation of 20%. Component population, layout of traces, layers, and air flow strongly influence heat dissipation. Worst-case load conditions should be tested in the real environment to ensure proper thermal conditions. Minimize thermal stress for proper long-term operation with a junction temperature well below +125C.
LAYOUT GUIDELINES
The leadframe die pad should be soldered to a thermal pad on the PCB. A mechanical data sheet showing an example layout is attached at the end of this data sheet. Refinements to this layout may be required based on assembly process requirements. Mechanical drawings located at the end of this data sheet list the physical dimensions for the package and pad. The five holes in the landing pattern are optional, and are intended for use with thermal vias that connect the leadframe die pad to the heatsink area on the PCB. Soldering the exposed pad significantly improves board-level reliability during temperature cycling, key push, package shear, and similar board-level tests. Even with applications that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity and long-term reliability.
THERMAL PAD
The thermal pad must be connected to the same voltage potential as the device GND pin. Packages with an exposed thermal pad are specifically designed to provide excellent power dissipation, but board layout greatly influences overall heat dissipation. The thermal resistance from junction-to-ambient (TJA) is specified for the packages with the exposed thermal pad soldered to a normalized PCB, as described in Technical Brief SLMA002, PowerPAD Thermally-Enhanced Package. See also EIA/JEDEC Specifications JESD51-0 to 7, QFN/SON PCB Attachment (SLUA271), and Quad Flatpack No-Lead Logic Packages (SCBA017). These documents are available for download at www.ti.com.
space
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (June, 2010) to Revision C Page
Page
21
www.ti.com
24-May-2011
PACKAGING INFORMATION
Orderable Device XTR111AIDGQR XTR111AIDGQRG4 XTR111AIDGQT XTR111AIDGQTG4 XTR111AIDRCR XTR111AIDRCRG4 XTR111AIDRCT XTR111AIDRCTG4 Status
(1)
Package Type Package Drawing MSOPPowerPAD MSOPPowerPAD MSOPPowerPAD MSOPPowerPAD SON SON SON SON DGQ DGQ DGQ DGQ DRC DRC DRC DRC
Pins 10 10 10 10 10 10 10 10
Package Qty 2500 2500 250 250 3000 3000 250 250
Eco Plan
(2)
(3)
Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br) Green (RoHS & no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
www.ti.com
24-May-2011
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Device
Package Package Pins Type Drawing MSOPPower PAD MSOPPower PAD SON SON DGQ 10
SPQ
Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 5.3
B0 (mm) 3.3
K0 (mm) 1.3
P1 (mm) 8.0
XTR111AIDGQR
2500
XTR111AIDGQT
DGQ
10
250
180.0
12.4
5.3
3.3
1.3
8.0
12.0
Q1
XTR111AIDRCR XTR111AIDRCT
DRC DRC
10 10
3000 250
330.0 180.0
12.4 12.4
3.3 3.3
3.3 3.3
1.1 1.1
8.0 8.0
12.0 12.0
Q2 Q2
Pack Materials-Page 1
Pins 10 10 10 10
Pack Materials-Page 2
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