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Novel, Four-Switch, Z-Source Three-Phase Inverter

Róbert Antal 1 , Nicolae Muntean 1 , Ion Boldea 1 , Frede Blaabjerg 2

1 Politehnica University of Timisoara/Department of Electrical Engineering, Timisoara, Romania

2 Institute of Energy Technology, Aalborg University, DK – 9220 Aalborg East, Denmark e-mail:aroberrr@yahoo.com;

Abstract-This paper presents a new z-source three phase in- verter topology. The proposed topology combines the advan- tages of a traditional four-switch three-phase inverter with the advantages of the z impedance network (one front-end diode, two inductors and two X connected capacitors). This new topol- ogy, besides the self-boost property, has low switch count and it can operate as a buck-boost inverter. In contrast to standard four-switch three-phase inverter which operates at half dc input voltage the proposed four-switch z-source inverter, by self boost- ing, brings the output voltage at same (or higher) value as in six switch standard three-phase inverter. The article presents the derivation of the equations describing the operation of the con- verter based on space vector analysis, validation through digital simulations in PSIM and preliminary experimental results on a laboratory setup with a dsPIC30F3011 digital signal processor.

Index Terms-z-source three-phase inverter, four switch in- verter, shoot-through time ST, space voltage vector

I.

INTRODUCTION

Z-source three-phase converters (Fig. 1) with six power switches have been proposed recently [1] with different con- trol strategies [3-6]. In essence they are self-boosting unidirectional dc-ac con- verters with only six power switches (unless used in multi-

level topologies [7]), which are used with some PWM strate- gies to short-circuit (Fig. 2b) the z-source and thus produce dc voltage boosting. In between short-circuits the same six power switches produce the required output voltage wave- forms. It can be seen in Fig. 2a that during the shoot-through in-

. The average dc-link volt-

terval the dc-link voltage

age is equal with the voltage across the capacitors in the z

impedance network [1]

V in

= 0

V

=

V

=

V

=

V

=

1 D

ST

; D

=

t

ST

in

C

1

C

2

C

1

2 D

ST

ST

T

s

(1)

where D ST is the shoot – through duty ratio and T s is the switching frequency. The self-boosting attribute of Z converters is “paid for” by some voltage and current over rating. On the other hand lower count four switch three-phase inverters with split dc- link capacitor are characterized by half dc input voltage used for output voltage PWM and thus a 2/1 current overrating of switches is necessary. To alleviate this situation, while bring- ing back full dc-link voltage utilization, a novel, four-switch three-phase z-source converter topology is proposed in this

paper. This way the over current rating in comparison with the six switches three-phase inverter is small, though some notable voltage over rating remains. However this demerit should be justified by the additional voltage buck-boosting attributes that can be indispensable for voltage sags handling in safety critical applications. Among applications we enumerate here renewable dc-ac interfacing of photovoltaic panels, fuel cells, batteries and

electric drive with frequent voltage sags. This proposed novel

off-

inverter topology can be also used for small (1

grid wind energy-electrical energy generation systems with permanent magnet synchronous generators. The paper is organized as follows: first the equations de- scribing the operation of the inverter are derived, after that the shoot-through time generation and the gating signals are pre- sented and finally digital simulations and preliminary experi- mental results validate the theory.

10kW)

experi- mental results validate the theory. 10kW) Fig. 1. Z-source three-phase inverter with six switches. a)

Fig. 1. Z-source three-phase inverter with six switches.

Fig. 1. Z-source three-phase inverter with six switches. a) b) Fig. 2. Equivalent circuits of the

a)

Fig. 1. Z-source three-phase inverter with six switches. a) b) Fig. 2. Equivalent circuits of the

b)

Fig. 2. Equivalent circuits of the Z-source network in (a) shoot through state (b) non shoot-through state.

II. THE PROPOSED FOUR-SWITCH Z-SOURCE THREE-PHASE INVERTER

As we could see in case of a z-source inverter with six switches Fig. 1, 2 the voltage across the inverter bridge is zero when the voltage boost is applied by short-circuiting at least one of the three inverter legs. So the shoot-through state of the inverter limits the available maximum output voltage of the inverter [6]. Hence to fully utilize the voltage boost and to limit the voltage and current stresses of the inverter bridge without affecting the output voltage, the placing of shoot- through states during the zero voltage vector time intervals (no voltage seen by the load) seems to be a practical solution

[4,6].

A. Principle of Operation

to be a practical solution [4,6]. A. Principle of Operation Fig. 3. Four-switch z-source three-phase inverter.

Fig. 3. Four-switch z-source three-phase inverter.

The proposed four-switch z-source three-phase inverter is shown in fig. 3. In essence, the novel topology shows that one of the ca- pacitors in the Z network is split into two and the middle point is connected to one phase of the load. This 50% voltage drawback of conventional four-switch three-phase inverter is eliminated by the proposed four-switch Z-source inverter because the shoot-through state produces not only the voltage boost but it produces also an active volt- age vector, thus generating non-zero output voltage Fig 4. The equivalent scheme of the shoot-through state of the proposed inverter (when all four transistor are conducting) in Fig. 4 clearly shows that during the shoot-through state the voltage seen by the load is equal with the voltage across ca- pacitor C 2 .

load is equal with the voltage across ca- pacitor C 2 . Fig. 4. Shoot-through state

Fig. 4. Shoot-through state equivalent circuit of the 4-switch z-source three- phase inverter.

circuit of the 4-switch z-source three- phase inverter. Fig. 5. Phase terminal voltages referenced to ground

Fig. 5. Phase terminal voltages referenced to ground 0.

TABLE 1

SWITCHING PATTERN

V 1 V 2 V 3 V 4 V ST T 1 T 2 T

V

1

V

2

V

3

V

4

V

ST

V 1 V 2 V 3 V 4 V ST T 1 T 2 T 3
V 1 V 2 V 3 V 4 V ST T 1 T 2 T 3
V 1 V 2 V 3 V 4 V ST T 1 T 2 T 3

T 1

T 2

T 3

T 4

2 V 3 V 4 V ST T 1 T 2 T 3 T 4 0
2 V 3 V 4 V ST T 1 T 2 T 3 T 4 0
2 V 3 V 4 V ST T 1 T 2 T 3 T 4 0

0

1

0

1

1

0

0

1

1

0

1

0

0

1

1

0

1

1

1

1

0 1 0 1 1 0 0 1 1 0 1 0 0 1 1 0

By averaging the voltage across one inductor during one switching period in steady state the same relationship can be obtained between the input dc voltage V DC and the average dc- link voltage V in as in (1). The average dc-link voltage is equal

with the voltage across C 1 or across C 2 and C 3 as for a three- phase z-source inverter with six switches. Before we step further into the analysis of the proposed to- pology we make the following assumptions:

The average voltages across C 2 and C 3 are equal with each other.

The front-end diode D1 is always conducting when the converter is in the non-shoot through state, thus the pseudo-active state is avoided [4].

B. The Space Voltage Vectors of the Four-Switch Z-Source

Three-Phase Inverter For the three-phase load in Fig. 3 the voltage space vector can be defined as follows

⎛ 2 ⎜ v = s ⎜ 3 ⎜ ⎝
2 ⎜
v
=
s
3

v

UN

+

e

j

2 π

4 π

3 v

VN

+

e

3 v

j

WN

(2)

where v UN , v VN and v WN are the instantaneous phase voltages. With the four switches in Fig. 3 five voltage vectors can be obtained, as in Table 1. All voltage vectors are active voltage vectors as we will see in the following section. Although two more shoot-through states can be obtained by turning on T 1 and T 2 or T 3 and T 4 in the same time, these states were neglected because the maxi- mum current flowing through the inverter bridge would only flow through one leg of the inverter bridge which would lead to a bigger kVA transistor bridge. The wye connected three- phase load terminal voltages referenced to ground are shown, with respect to the switching pattern in Table 1, in Fig. 5.

In order to derive the phase voltages we will consider

V C V = V ; V = V = (3) C C 1 C
V
C
V
= V
; V
= V =
(3)
C
C
1
C
2
C
3
2
,
C 2 and C 3 capacitors. For a symmetrical balanced wye con-
nected three-phase load (Fig. 3) the phase voltages can be
written as
where
V
V
and
V
are the average voltages across C 1 ,
C1
C2
C3
2
1
=
v
(
v
+
v
)
v UN
U
0 −
0
W
0
3
3 V
2
=
v
1 )
(
v
+
v
(4)
v VN
V
0 −
W
0
U
0
3
3
2
1
=
v
( v
+
v
)
v WN
W
0
U
0
V
0
3
3
Substituting
u
,
u
and
, from fig. 5, into (4) and
U0
V 0
u W 0

using the expression of the space voltage vector (2) the five voltage vectors can be derived as

2 V = V − V 1 C DC 3 ⎛ 1 2 3 ⎞
2
V
=
V
V
1
C
DC
3
1
2
3
1
3
V
=
+
j
V
+
− −
j
2
C
3
3
3
3
1
V
=−
V
3
C
3
1
2
3
1
3
V
=
j
V
+
+
j
4
C
3
3
3
3
1
V
=−
V
ST
C
3


⎞ ⎟

⎟ ⎠

V

DC

V

DC

(5)

The relationship between the average capacitor voltage

V

C

and the input dc voltage

V

C

V

DC

can be expressed as

= k V

DC

k

=

1

D

ST

1

2 D

ST

;

k >

1

(6)

(7)

Rewriting (5) using (7) the voltage vectors can be derived as

(5) using (7) the voltage vectors can be derived as 1 V =− ST 3 kV

1

V =− ST 3
V
=−
ST
3

kV

DC

1

)

+ 1

V

DC

)

V

DC

(8)

DC 1 ⎤ ⎥ ⎥ ⎦ ) + 1 V DC ⎤ ⎥ ⎥ ⎦ )

Fig. 6. Locations of the voltage vectors in the complex plane.

Notice that in (8) the boost factor k influences the ampli- tude as well the direction of the six voltage vectors. For k=2 the six voltage vectors in the complex plane are il- lustrated in fig. 6.

The voltage vector generated by the shoot-through state V ST

has the same amplitude and direction as the V 3 voltage vector. The voltage space vector expressed in (2) can be rewritten in the complex plane as

(9)

v

s

= v

sα

+ jv

sβ

The average voltage space vector over one switching cycle should be equal with the sum of the five average voltage space vectors (V 1 …V 4 and V ST ) over one switching cycle T s

v

s

=

(

t V

1

1

+

t

2

V

2

+

t V

3

3

+

t

4

V

4

+

t

ST

V

ST

)

/T

s

(10)

 

t

1

+ t

2

+ t

3

+ t

4

+ t

ST

= T

s

 

(11)

 

v

sα

and

v

sβ

(9) the expres-

where

To obtain the expressions of

sions of the five voltage vectors (8) are introduced in (10)

V DC v = [ t 1 ( 3 k − 2 ) + (
V
DC
v
=
[
t
1 (
3
k
2
)
+
(
t
+
t
s
2
α 3 T
s
3
V
DC
v
(
t
t
)(2 1)
k
s
β =
2
4
3 T
s

4

)(

k

)

1

− −

(

t

3

+

t

ST

)

k

]

(12)

Given (1)-(12) in this section it is possible to derive several

algorithms that can be implemented in a digital signal proces- sor which, for a prescribed input space voltage vector,

v

s

=

v

sα

+

jv

sβ

(13)

calculate the duty ratios for the four transistors and generates the four gating pulses.

III. SHOOT-THROUGH PULSE IMPLEMENTATION AND PWM SIGNAL GENERATION

One easy way to generate the gating signals for the four transistors is to use three synchronized PWM units in com- plementary mode of a DSP with some additional circuitry.

plementary mode of a DSP with some additional circuitry. Fig. 7. Block diagram of the PWM

Fig. 7. Block diagram of the PWM signal generation implementation.

Two of the three PWM generation units yield the two com- plementary signals for the two phase legs of the inverter bridge based on the prescribed duty ratios D V and D W . The third PWM unit generates the ST signal from D ST . The four outputs from the two units are ORed with the ST signal thus obtaining the PWM signals for T 1 …T 4 .

thus obtaining the PWM signals for T 1 …T 4 . Fig. 8. PWM signal waveform

Fig. 8. PWM signal waveform generation for T 1 , T 2 , T 3 & T 4 .

IV. SIMULATION RESULTS

In the first step of the validation, the proposed four-switch

z-source three-phase inverter was simulated in PSIM. The circuit parameters were as follows

V

DC

C

2

∗ v s f s
v
s
f
s

=

=

=

mH C

90

=

C

3

60

L

470

k

V

=

;

V

;

1

=

L

2

F

μ

=

2;

R

;

f

=

L

1

6.4

=

R

L

2

=

50

Hz

;

=

=

0.9

1

10

kHz

235

Ω

uF

;

A three-phase wye connected RL load was used with the

following parameters

R

L

U

U

=

=

10 .5 ; R

Ω

V

20 .1mH ; L

V

=

10 .6 ; R

Ω

W

=

18 .4 mH ; L

=

W

10 .2 ;

Ω

=

17 .7 mH

Only open loop performance with imposed output voltage vector amplitude, to derive commutation sequences and the required shoot-through time for the dc-link voltage boost, was investigated both in simulations and experiments. The simulated waveforms are shown in Fig. 9-Fig. 13.

4 3 2 1 0 -1 -2 -3 -4 Current [A]
4
3
2
1
0
-1
-2
-3
-4
Current [A]
0 0.1 0.2 0.3 0.4 0.5 Time [s] Fig. 9.Simulated load currents at start-up. 5
0
0.1
0.2
0.3
0.4
0.5
Time [s]
Fig. 9.Simulated load currents at start-up.
5
I
I
I
4
U
V
W
3
2
1
0
-1
-2
-3
-4
-5
0.24
0.25
0.26
0.27
0.28
0.29
0.3
0.31
Current [A]

Time [s]

Fig. 10. Simulated load currents (zoom).

200 V C1 180 160 140 120 V C3 V DC 100 80 60 V
200
V
C1
180
160
140
120
V
C3
V
DC
100
80
60
V
C2
40
20
0
0.1
0.2
0.3
0.4
0.5
Voltage [V]

Time [s]

Fig. 11. Simulated voltage waveforms across C 1 , C 2 , C 3 and the input dc volt- age at start-up.

7 6.5 6 I 5.5 L2 I L1 5 4.5 4 3.5 3 2.5 2
7
6.5
6
I
5.5
L2
I
L1
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Current [A]
Time [s] Fig. 12. Simulated z-impedance inductor current waveforms I L1 and I L2 .
Time [s]
Fig. 12. Simulated z-impedance inductor current waveforms I L1 and I L2 .
300
250
200
150
100
50
0
0
0.1
0.2
0.3
0.4
0.5
Time [s]
Fig. 13. Simulated instantaneous dc-link voltage V i .
Voltage [V]

The shoot-through time was linearly increased from 0 to its nominal value in 0.120s to avoid the high inrush current Fig.

11. In Fig. 10 it can be seen that the load currents are not

perfectly symmetrical due to the connection of phase U to the

common node of capacitors C 2 and C 3 which causes the volt-

age potential at this terminal to vary around

The simulated inductor currents (which flow through both inverter legs during shoot-through states) are shown in Fig.

V C
V
C

2 Fig. 11.

12, and they are less than 150% the peak load currents (Fig.

The boost dc-link voltage is shown in Fig. 13 (input dc

10).

voltage is 90V dc).

V. EXPERIMENTAL WORK

A laboratory setup was built to experimentally validate the proposed four-switch Z-source three-phase inverter. The con- trol algorithm based on equations (1)-(12) was implemented

on a dsPIC30f3010 digital signal processor from Microchip

with a clock frequency of 120MHz. The experimental wave-

forms are shown in. Fig. 14-Fig.18.

The laboratory setup data are the same as for the digital simulations. The experimental load currents in Fig. 14 are close to those from digital simulations (in Fig. 10) though a bit more asym- metric. The inverter starting experimental transients of Fig. 15-17 are similar to those obtained for same transients by

digital simulations in Fig. 11 and 9 respectively.

The test and simulation load phase current transients (Fig.

17 and Fig. 9) fit rather well; the same observation is valid for

V C2 , V C3 which pulsate around input dc voltage of 90V dc.

The dc-link (boosted) voltage V C1 in experiments (Fig. 15)

pulsates around 160V while in simulation is around 180V dc,

while the experimental inductor currents (Fig. 18) are smaller

than the digital simulations (Fig. 12). These discrepancies

require further insight.

5 I I I U V W 4 3 2 1 0 -1 -2 -3
5
I
I
I
U
V
W
4
3
2
1
0
-1
-2
-3
-4
-5
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
Current [A]

Time [s]

Fig 14. Experimental load currents.

200 190 V 180 C1 170 160 150 140 130 120 110 V C3 100
200
190
V
180
C1
170
160
150
140
130
120
110
V
C3
100
90
80
70
60
50
40
30
20
10
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Voltage [V]

Time [s]

Fig. 15. Experimental voltages across C1 and C3 capacitors at start-up.

100 90 V C3 80 70 60 V C2 50 40 30 20 10 0
100
90
V
C3
80
70
60
V
C2
50
40
30
20
10
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Voltage [V]

Time [s]

Fig. 16. Experimental voltages across C2 and C3 capacitors at start-up.

4 I PhaseU 3 2 1 0 -1 -2 -3 -4 0 0.05 0.1 0.15
4
I
PhaseU
3
2
1
0
-1
-2
-3
-4
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Current [A]

Time [s]

Fig. 17. Experimental current waveform through phase U at start-up.

7 6.5 6 5.5 5 I L2 4.5 I 4 L1 3.5 3 2.5 2
7
6.5
6
5.5
5
I
L2
4.5
I
4
L1
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
Current [A]

Time [s]

Fig. 18. Experimental Z-impedance inductor current waveforms I L1 and I L2 .

VI. CONCLUSIONS

This paper has proposed a novel four switch z-source three

-phase inverter topology which links together the advantages

of a four switch inverter (low switch count) and a z-source

inverter (self-boost ability). The shoot-through state not only boosts the input dc voltage but also produces an active volt-

age as well, while in case of the z-source inverter with six

switches the shoot-through state only boosts the input dc volt-

age. By voltage-boost, the new four-switch z-source three-

phase inverter eliminates the need to redesign the electric

motor in terms of terminal voltage, as needed for conven- tional four-switch split capacitor three-phase inverters. The equations of the new converter were derived and the theory was verified through digital simulations and experiments.

ACKNOWLEDGEMENT

This work was partially supported by the European Eco-

nomic Area (EEA) project RO 018 “Improvement of the

Structures and Efficiency of Small Horizontal Axis Wind

Generators with Non-Regulated Blades”.

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