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entity my_ckt is
port (x, y :in bit;
z : out bit)
end entity my_ckt; simulation
architecture behavioral of
my_ckt is
begin
-- some code here
--
end architecture behavioral;
@15 ns
@10 ns
Head
0→1 1→0 0→1
@15ns @10ns @5ns
Event List
sum
carry
5 10 15 20 25 30 35 40
Time (ns)
a
sum
b
carry
Discrete Event Simulation: Data Structures:
simulator clock 5 ns
U →1 U→0 1→ 0
carry@5ns sum@5ns a@5ns
5 ns
0→1 1→ 0 0→1 1→ 0
sum@10ns carry@10ns a@10ns b@10ns
10 ns
1→ 0
a@15ns
Simulation Modeling
HDL
Description
Discrete event
simulator
Designer
Synthesis
Compiler
Target Primitives
A
A
B B
C C
B B
C
C
D
B
B C
ABC + BC + DB
C LB C LB C LB
C LB C LB C LB
G4 Logic
S/R
Function Control Bypass
of G1 –G4
G3 D IN YQ
F´ SD
G´ G´
D Q
G2 H´
G1 Logic
Function of F,́
G´ EC
G,́ and H1 RD
H´ H´
1
Y
F4 Logic
Function
S/R
of F1 –F4 Control
F3 D IN XQ
F´ SD
D Q
F´ G´
F2 H´
F1
EC
RD
K
(CLOCK) 1
H´
X
F´
Multiplexer Controlled by
Configuration Program
0 Output MUX
1 Flip-Flop
Output
Out D Q
Buffer
Pad
CE
I1
Flip-Flop/
Latch
I2 Delay Delay
Q D
Q D
Fast Latch
Clock Enable CE
Capture
Latch G
Input Clock
12 Quad
8 Single
4 Double
3 Long
Direct
CLB 2
Connect
3 Long
12 4 4 6 4 8 4 2
Specialized Resources
• Carry chains between columns of CLBs
• Configuration of CLB RAM as memories rather than lookup
tables
• Core generators
• optimized libraries of components
• vendor supplied
• What about editing the bit stream directly!
Chip Configuration (Xilinx)
• Configuration bits for CLBs
• bits for loading the LUTs
• bits for configuring the flip flops
• bits for setting multiplexors
• Configuration bits for the switch matrix
• connecting horizontal and vertical lines
• tristate devices within the CLBs
• Configuration bits for the IOBs
• IO clocks
• storage vs. direct “access” to the pin
• Equivalent concepts for all vendors
Design Flow
Model Development
Behavioral Simulation
Core Synthesis
Generation
Utilitites
Functional Simulation
Verification
Programming
Device Programming