DPU Systems

2006 Programmable Single Step Processors All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, ithout permission in riting from both the copyright o ner and the publisher. !e"uests for permission to ma#e copies of any part of this or# should be mailed to Permissions $epartment, %lumina Press, P& 'o( ))22*6, +oral Springs, ,% --0)).22*6 /S'N0 1.23226.*13.1 Printed in the 4nited States of America by %lumina Press %ibrary of +ongress +ontrol Number0 20063022*0

Table of Contents
/N5!&$4+5/&N in 1 Purpose and &vervie 1 1.1 /ncreasing +omple(ity and +oncentration 1 1.1.1 +entrali6ed Processing and +ontrol 2 1.1.2 5he 'ottlenec# 2 1.1.- 7ulnerability 1.1.* %imits * 1.2 $ecentrali6ation and /ntegration 2 1.2.1 8andling the +ode ) 1.2.2 Apportioning 9 1.2.- Simultaneous Processes 3 1.2.* 5he &perating System 10 1.2.2 'ooting, %oading, and 5ermination 11 2 PSSPs : ,unction, and $esign 12 2.1 Separation of +ode and $ata 16 2.1.1 Processing Section of PSSPs 1) 2.1.2 +ontrol Section of PSSPs 20 2.1.- $ata ,lo and Activation 22 2.2 PSSPs ith $edicated ,unctions -0 2.2.1 Se"uencing PSSPs -1 2.2.2 5he /;& <ate#eeper -2 2.2.- PSSPs for 'ooting -2.2.* &ther Possibilities -* - 5he Set of &perations -) -.1 5he =ovement of $ata *1 -.1.1 =&78 and =&75 /nstructions *1 -.1.2 =&7+ /nstruction ** -.1.- /NP and &45 /nstructions *) -.2 Arithmetic and %ogic &perations *9 -.2.1 &ne &perand /nstructions *3 -.2.2 5 o &perand /nstructions *3 -.- +ontrol &perations 20 -.-.1 <lobal +ontrol &perations 20

-.-.2 Se"uencing &perations 22 -.-.- %ocal +ontrol &perations 2) -.* Program ,lo &perations 66 -.*.1 >umps ithout a !eturn 66 -.*.2 >umps ith a !eturn 6) -.*.- !?5, N&P, and 8%5 69 -.2 +oding ?(ample 63 * 'uilding a System )1 *.1 'us Structures )1 *.1.1 Non.apportioned 'us Structures )2 *.1.2 Apportioned 'us Structures )) *.1.- 'ilateral +ontrol 'us 90 *.2 Apportioning 9*.2.1 S itches 9*.2.2 S itch +ontrol 92 *.- &perating System 96 *.-.1 +ontrol of the 'us Structures 9) *.-.2 'ooting, ?(ecution, and 5ermination 93 *.-.- /;& System 93 *.-.* Security and Stability 3) <lossary 101

INTRODUCTION
he purpose of this boo# is to outline a computer system unli#e any system you have #no n before. 5his system, referred to as a PSSP system, is capable of running numerous processes simultaneously and independently. A PSSP system accomplishes this feat through a ne design that casts off constraints that have been limiting factors since electronic computing machines ere first created. /nherent in the ne design is a high degree of integration and decentrali6ation of the computing elements, as ell as a means of splitting the resources of the system into sections that can be assigned to various individual processes. A traditional system has a +P4, storage, and /;& as separate entities ithin the system. A PSSP system does not. A PSSP system is populated ith a multitude of similar entities called PSSPs. All the elements of computing are integrated into the design of PSSPs. <roups of PSSPs, assigned to different processes, ill or# together to achieve their various goals. 5hese processes ill run ithin the system simultaneously ithout interference from one another. @henever a process needs to communicate ith another process, it ill ma#e use of the /;& bus that has been designed to handle all inter.process communications. Such a radically different design re"uires an operating system to match. 5he operating system for a PSSP system isnAt burdened ith controlling a +P4, e(ecuting the code of various processes, or handling /;& interrupts. 5he primary concern of the operating system is controlling all the buses ithin the system. /t uses a global control bus to control the system as a hole and it controls the /;& bus to ma#e sure every process get its fair share of time to input and output data. 5he rest of the bus system is apportioned out by the operating system, so that each process gets the resources it needs to function independently ithin the system. A PSSP system is much simpler than a conventional system, but it is also very different. =any old ays of thin#ing need to be changed hen learning a PSSP system. 5his ma#es the tas# of revealing the details of such a system challenging. /t is easy to present them, but to do so in a manner easy for the average reader to assimilate is not so simple. =any "uestions arise as efforts are made to optimi6e and organi6e the concepts underlying such a system. 5he readers are the best Budges of hether / have presented the concepts ade"uately. / apologi6e to those readers for hom my efforts fall short, and e(tend an invitation to them and anyone else to communicate to me their thoughts on matters contained ithin this boo#. Please send your

correspondence to csy#esCPSSPsystems.com. / tried to avoid unnecessary Bargon ithin the te(t and #ept the e(planations simple. 5here is a lot of repetition in the presentation of the concepts, especially hen the concepts occur ithin a different conte(t. 5his is done purposely, in an effort to tie all the concepts into a coherent hole. 5here is a glossary and an inde( at the rear to assist the reader.

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Purpose and Overview

ecentrali6ed processing units are the name given to the devices designed to replace the central processing units used in computers today. A multitude of decentrali6ed processing units are used to collectively handle the functions ithin a computer no handled by one or more central processing units ith associated memory. 8ereafter, these devices ill be referred to as PSSPs. 'efore e(plaining hat PSSPs are, and ho they or#, it is orth hile e(ploring some of the problems the computer industry is encountering in its attempts to design better computing machines. Attempts to find solutions for these problems led to the development of PSSPs. 1.1 Increasing Complexity and Concentration ?ver since the building of the earliest computers, the search has been on to find ays of increasing the throughputDthe amount of or# that can be done in a given amount of time. =ost efforts have succeeded to some degree, but the struggle continues as tas#s increase in si6e and comple(ity and demand ever greater computing po er. 5he future of computing machines re"uires an increasing vista of capability as humanity e(pands and see#s to use them as tools to understand and master the physical realm. 5his struggle to increase throughput is leading to systems of such comple(ity that understanding them is beyond the capacity of most people. @hy are computing systems becoming so comple(E =achines evolve to fill an ever.e(panding set of e(pectations. =any machines have evolved this ay. 5he first cars ere very simple devices compared to cars of today. So much more is e(pected no . +omfort, ease of use, safety, and lo environmental impact are features of todayAs cars, and the comple(ity has increased accordingly. 5here are many other e(amplesDtelephones, radios, refrigeration unitsDeven simple things, such as car #eys and cloc#s. /n the beginning, computers ere intended as calculating machines, but they have become capable of such a variety of functions that they are no ubi"uitous ithin our culture. <iven that e see# to have our machines become more functional, must they also become more complicatedE /t might seem so, but that may be because e are surrounded by machines built to be comple(, often for no other reason than a desire to have comple(ity built into them. =odern appliances have many added features that serve no useful function, other than impressing the users. /n other ords, e do not see# simplicity in our designs, and therefore, do not achieve it. /t might even go deeper. Perhaps it is in our nature as humans to desire comple(ity, despite tal#ing so often of yearning for simpler things. @hether it is music, foods, machines, or movie plots, e seem to prefer more complicated offerings. /n truth, the need for increasing comple(ity probably is real, to some degree. =ore comple(ity is often needed, but it is also true that the best designs are those that achieve their functions ith simple elegance. @ith computing machines, the problem of comple(ity seems to stem from the entrenchment of or#able solutions molded from original concepts. /n the beginning, as theory and concepts ere

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turned into or#able solutions, e came to accept these solutions as sacrosanct. @e may o e reverence to the original concepts and theories, but solutions need to bend to the technologies of the time and ma#e use of the capabilities ithin the industry. 1.1.1 Centralized Processing and Control %oo#ing bac# at the beginning, the original pioneers of computing machines correctly led us believe that these devices needed certain elements to function as computing machines. =any no refer to these elements as F7on Nuemann architecture,G even though others came for ard ith the same ideas. !egardless of ho deserves credit for it, the concept that all computing machines must have these essential elements has become so ingrained that e no longer even thin# about it. 5he original concepts are solidH nobody can find fla s in them. /t is ho e apply the concepts that e need to e(amine more closely. 5hat processing, control, and memory are essential elements of computing machines is idely accepted and understood. Some people believe that /;& elements belong ith the other three, but for this discussion, they ill be momentarily set aside and added later. +ost and manufacturing constraints, at the time the first machines ere built, led to compromises as to ho these elements ould be incorporated into the design. +ontrol and processing ere implemented ithin a control and processing unit, hich today is referred to as the central processing unit. =emory as #ept separate from control and processing e(cept for a small set of registers located close to processing. &ver the years, the +P4 became increasingly po erful and memory as e(panded to ever.greater "uantities to accommodate the processes the +P4s had to handle. 5oday, the machines are basically built the same. 5echnology and throughput have vastly improved, even as overall costs of the systems have decreased. Processing and control is still centrali6ed, and memory is treated as a resource to serve the needs of the +P4. ?fforts have been made to begin the decentrali6ation of processing and control, but this effort has not progressed far. 5remendous efforts are being made to build systems ith multiple +P4s. Some are designed so that each +P4 has its o n set of resources, hile others use cooperative methods to share resources amongst the multiple +P4s. All of these efforts are increasing comple(ity and yet failing to come up ith real solutions to the problems standing in the ay of all but modest increases in throughput. 1.1.2 The Bottleneck 5he difficulties preventing substantial increases in throughput have come to be #no n as the F7on Nuemann bottlenec#.G =emory has been #ept separate from processing and control, and conse"uently, the need remains for the data and code to transit bac# and forth over the bus structures. ?ven hen the +P4 #eeps fre"uently used code and data nearby for rapid access, a tremendous amount of system resources is needed to #eep it organi6ed and easily available. $irect memory access, caches, pipelining, virtual memory, !/S+ architecture, and other methods have all sought to overcome the problem of separating memory from processing and control. 5hey have succeeded in increasing throughput to some degree, but none has solved the problem presented by #eeping the memory separate from processing and control. Some attempts to overcome the bottlenec# have done so by moving portions of memory closer to the processing element. 5he solution definitely seems to lie in that direction, but for some reason e canAt overcome our bias against memory.

PSSP Systems @hy do e thin# memory is different from processing and controlE /ts function is different, Bust as the function of processing is different from the function of control, but is the value of memory less than processing and controlE =emory is treated as if it is merely a resource of processing and control, and yet the pioneers of computing clearly indicated that all three elements ere needed. Never did they indicate that memory as the lesser element of the three, or that it as there to serve the needs of

processing and control. @hat if processing and control as treated as a resource for memoryE @hat if, instead of trying to get memory closer to processing and control, an attempt as made to get processing and control closer to memoryE 5hese are serious "uestions, not hypothetical entertainment. @hat if control, processing, memory, and even /;& ere combined to achieve full integration of all the essential elements of computingE 1.1.3 Vulnera ility @ith the increasing comple(ity of the systems comes increasing vulnerability. System vulnerability comes in many forms, including susceptibility to malicious or inade"uately designed code, difficulty understanding the interactions bet een comple( components or code, possible system failures because of so many comple( interactions, and the difficulty of training personnel to handle the comple(ities of such systems. /t seems that as comple(ity increases, so does vulnerability. At odds ith this vulnerability is the need for reliability ithin systems as they handle increasingly important functions ithin our culture. 5he systems e design and implement should reach the highest plateau of reliability and robustness. ?(traordinary efforts are made to increase the reliability of systems, but it al ays comes at great e(pense. 5he trend is going in the rong direction. /f our efforts fail to increase system reliability ithout raising the cost, e need to rethin# hat e are doing. 5he need for reliability ill increase as computers are integrated into systems that are themselves increasingly comple(. System failure is becoming less tolerable, contrasting a reality that gives us the increasing possibility of failure hich e are e(pected to accept as normal. 5he cost of a system includes, among other things, the original cost associated ith the purchase, and the cost associated ith maintenance and recovery from system failure. @hile the original cost of systems is actually decreasing hen measured against throughput, this is not so for costs associated ith maintenance and failure recovery. 5hose costs are increasing rapidly as the comple(ity of systems increases. +omple(ity is a natural component of gro th. As products are refined to ma#e them more responsive to needs and more efficient, increased comple(ity is usually one of the results. 8o ever, at some point, comple(ity fails to meet our needs or provide greater efficiency. 5hat point is reached hen failure occurs too often, at too great a cost, or ith too great an impact. @hen systems fail, e usually revert to simpler methods, at least temporarily. Perhaps a balance is attainable bet een comple(ity and simplicity. Perhaps a desirable goal in our engineering efforts is simplicity of design, function, and use. 5he notion that any Bob can be reduced to a series of simple, repeatable steps that can be done by simple devices can be applied to computing machines. Perhaps computing machines can be reduced to simple redundant components, each doing a small part in getting the Bob done. 1.1.! "imits ,or many years, scientists and engineers have been pushing the limits of ho fast electronic circuits can change from one state to another state. Astonishing increases in throughput have been

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achieved, and still more are attainable, but ho much is it costing, and isnIt there a limitE +osts in material, research, and manufacturing techni"ues, as ell as the cost of system failure and even one personAs disgust hen their +P4 malfunctions, are all related, even though they are not comparably measurable in economic terms. 5hey are the results of the search for greater speed through comple(ity and centrali6ation. +urrent research, collectively costing our culture billions of dollars, see#s to have computations occurring at the speed of light. @hile interesting, even fascinating, is it practical as a goalE @hat is actually being sought is increased throughput, the ability to get more or# done in a given amount of time. $istributed computing, parallel designs, and other methods that spread the or#load seem to offer more promise in increasing throughput at a reasonable cost. Problems e(ist in synchroni6ing the efforts of multiple systems or +P4s or#ing on the same problem and many resources are e(pended in such efforts. Successful solutions usually come hen the problems are disassembled into a set of smaller, simpler problems that can be or#ed on independently. 5he concentration of processing and control into one or a fe places seems to have created a host of problems ithin our system designs. +P4s are so po erful and fast no that there is a problem

ith e(cess heat. 5his causes the need for special designs or cooling devices and the result is even more comple(ity and increased possibility of component failure. =emory is still separated from and is much slo er than processing, hich necessitates special system additionsDanother added comple(ity. /ncreased speed is sought at great e(pense and effort, and is usually achieved through greater comple(ity. 5he increasing comple(ity increases the rate of system failure and costs are rising as a result. Perhaps there is a better ay to thin# about the problems. Perhaps there is a need to rethin# the original design constraints to fit the manufacturing capabilities of modern times. 5he concentration of processing and control ithin hard are designs is mirrored in the approach used in the design of operating systems. /ncreasingly comple( operating systems are being designed to deal ith the hard are and the applications designed to run on it. 5rying to design soft are that ill control the systems and is capable of handling all situations that could arise has only led to even more comple(ity and a tremendous e(penditure of system resources. @hile the attempt has not completely failed, it has not been successful either, as system failure and vulnerability have not been eliminated. +oncentrating computing resources, hether through hard are or soft are, is the rong direction in hich to e(pend our efforts hile trying to design better systems to increase throughput. !eal orld systems, natural or man.made, that fail the least and achieve the most, seem to have plurality, or redundancy, in their design. ?(amples of this abound. &ne ant is easily ignored, but a nest of ants is not. &ne tree does little to affect the environment, but the effect of a forest is distinct. &ne s eep ith a broom barely leaves a trail, but repeated s eepings clean the floor. &ne man couldnAt build a pyramid in his lifetime, but a thousand men could. A Bourney on foot begins ith the first step and can only be completed by stepping repeatedly until the tas# is done. A nation ruled collectively prospers more than a nation ruled by one. +anIt these analogies also be applied to our system designsE /t is true that concentration of resources or po er has benefits hen applied to the right situation. 8o ever, there is an inherent vulnerability and ea#ness in such situations and there is usually multiplicity of some resource at the disposal of the concentration. A general is bac#ed up by his troops, but if he is disabled, the troops have no leader. A tree has a multiplicity of roots and branches,

PSSP Systems 2
but it is easily overcome hen an a( is ta#en to the trun#, the one point here they all converge. A net or# of client computers becomes useless if the server goes do n. 5hese analogies may seem silly, but the point is all too often overloo#ed hen systems are designed. =ust ne designs al ays see# to concentrate more speed, po er, and control into a central location instead of diffusing or distributing it throughout a systemE 5o design systems ithout the concentration of resources and po er is to ma#e them stronger and more robust. /f systems have multiplicity and redundancy ithin their design, then the failure of one part leaves the others still operating. !edundancy and multiplicity are more easily achieved ith simplicity, and all three attributes are steps in the right direction, leading a ay from the concentration of processing po er, and the vulnerabilities inherent in such an approach. 1.2 #ecentralization and Integration 5here are several system designs that are referred to as decentrali6ed. 5he term has been loosely applied to almost any system ith more than one +P4. &ne system that is tal#ed about, but not yet on the scene claims to have over one million +P4s spread out in the design. /t certainly sounds decentrali6edD but hat about integrationE Segregation is an accurate term to use hen referring to current systems. 'y this / mean that some of the computing elements are #ept separate from others. ,or e(ample, a system ith a +P4 contains the elements of processing and control in the +P4, and there ill be at least a fe registers close at hand. 8o ever, if the hole design is loo#ed at, it ill be seen that the main memory is separated from processing and control. %oo#ing at it from the point of vie of memory, the "uestion might be as#ed, F@hy isnAt there a potential for processing close at hand, here it is neededEG 5his point of vie has provided the impetus for the development of the design presented in the rest of this boo#. =emory consists of a multitude of addressable units, all connected to a common system of buses. /t is already decentrali6ed, as much as possible, e(cept for the fact that each memory

unit is concentrated into a series of bits, the basic data si6e ithin the system. %et us alter the design of a system by ma(imi6ing the decentrali6ation of the processing and control elements. At the same time, let us fully integrate these three elements so that they are spread throughout the design as small units, each capable of handling one basic data.si6ed chun# of bits, and each capable of handling one tas# related to processing or control. ,urthermore, let us ma#e these individual units programmable, so e can periodically change hich tas# they do. %et us also integrate the /;& into the design so that herever e have control, processing, and memory, e also have /;& capability. @hat e end up ith is hat / refer to hen / spea# of decentrali6ed processing units. A more e(act description of ho they might be constructed and used to build a system ill be given in the pages that follo . 'efore getting into those details, let us e(plore hat a system ould be li#e if it ere built of such devices and ho e might set things up so multiple processes could be run simultaneously ithin the system. 5ry to see the big picture before attempting to understand the small, but important, details. @e ill begin the e(ploration by giving a more precise definition of a PSSP. A PSSP is a combination of circuits that are separated into t o sections. &ne section is loaded, or programmed, ith an opcode that comes from a set of opcodes. 5he other section holds one related operand. 5he section holding the operand can also do some processing of that operand, alone, or in conBunction ith another operand. ?ach PSSP is connected to every bus in the system, but each bus has a different purpose, and the connection to each bus may be different. ?ach PSSP can be activated,

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hich means to be turned on for some purpose. 5he PSSP can be activated as a hole, or the section holding the operand can be activated separately. /f a PSSP is activated as a hole, its behavior ill be determined by the opcode it holds. /f Bust the section holding the operand is activated, its behavior ill be determined by the opcode held in some other PSSP. No let us imagine a process that has been implemented ith a series of instructions that follo an algorithm. 8ere e use a simple process to envision its implementation ith the PSSPs. At this point, donAt be concerned ith ho the opcodes accomplish their functions. /magine that there are PSSPs that can implement the functions as instructions to carry out the algorithm. No let us ta#e the data and instructions as listed belo and put them into a series of PSSPs, one after another. ?ach PSSP can hold one opcode and one operand. 5he opcode goes into one section of the PSSP, and the corresponding operand goes into the other section. 5he operand can be data or an address. /f more space is needed to hold e(tra data, or operands, use some of the PSSPs that precede the group of PSSPs holding the opcodes.
The Task 'egin ith t o numbers Add the t o numbers ?nd ith the t o numbers and a result The $lgorithm Storage for the first number Storage for the second number <et the first number <et the second number Add the t o numbers Store the result The Code Address Data Opcode 010 9 N&P 011 * N&P 012 .... N&P ... 110 010 =&78 111 .... A$$+ 112 011 N&P 11- 111 =&78 11* .... N&P 112 012 =&75

116 .... 8%5

The a o%e code is ho& it &ill look e'ore processing. $'ter processing addresses (12) 111) and 11! &ill contain the num er 12

@hen e are all set up, let us proceed to activate the PSSPs holding the instructions, or opcodes, one at a time, starting ith the first in the series, beginning at address 110. As each is activated, it ill perform one little part of the process, its part being the particular opcode that it holds. <radually, as

PSSP Systems )
each PSSP is activated, the process is implemented. @hen the last PSSP finishes its instruction, the tas# ill be done, and processing ill stop. 5his is a very simplified description of the implementation of a process, but it is a good place to start. 5here are many details needed to complete the picture, and "uestions that need to be ans ered before the reader ill be satisfied. 5he rest of the boo# is about giving those details and ans ering those "uestions. 1.2.1 *andling the Code 5he simple process implementation Bust given sho s several aspects of PSSP use that the reader should thoroughly grasp before delving deeper into their function and design. 5hey ill be repeated many times throughout the te(t because they are important attributes of possible PSSP designs and ill become essential elements in this type of system. 5he first point is that no +P4 is used to accomplish the processing. =any decentrali6ed processing units accomplish the tas#. 'oth +P4s and PSSPs are processing units, but they behave very differently. A +P4 does all the processing in a computer, or shares the tas# ith a fe other +P4s. A PSSP is intended to do only a small piece of the processing, and it may do only that same piece, again and again, until it is reprogrammed to do other ise. 5he ne(t important point is that there is no need to fetch instructions. 5he instructions are already here they ill be implemented. 5his is an important time saving aspect. 5he code is put here it is needed before the process is run. /n a system built of PSSPs, there ill never be a need for a process to move its o n code. /n fact, it is not even possible for a process, e(cept for the operating system process, to move its o n code. A moment is still needed for decoding the opcode as each PSSP is activated, but no bus is used to move code, nor is time used to fetch the instruction. 5he ne(t important point is that the operating system is not used to implement the process. 5here is an operating system, an &S, but it does not handle the time.sharing of a +P4 to implement this and other processes. 5he &S is in the bac#ground controlling the system, but is not actively involved in running the process. ?ach process runs itself and all processes run ithin the system simultaneously. 5he ne(t important point to reali6e is that the code is not moved e(cept during the programming of a process. / use the ord programming loosely here. @hen / say the PSSPs are programmed ith code, / mean that the &S loads the code into them. 5he actual soft are programming as done much earlier, along ith compilation. 5he &S ta#es the code from a secondary storage device, performs validity chec#s on it, adds a little code of its o n, and then puts it into the PSSPs. A final point to understand again relates to the code. 5he code is not moved around once the process has started. 5he code cannot be moved at any time by any process, e(cept the &S. &nly the &S has access to the instruction that moves code. =ore precisely, only the &S can put data into the section of PSSPs that holds the code. +ode and data are not mi(ed, e(cept hen in secondary storage or hen moved by the &S. 5his is a tremendous advantage hen it comes to system security and stability. 5hese five points are very important and should be #ept in mind hile trying to understand a system built of PSSPs. 5hey are important enough to be restated before going on to the ne(t section. 5he +P4 is replaced by a multitude of PSSPs that collectively perform all the functions of a +P4. +ode is not fetched for implementation from some here in memory hile a process is running. 5he &S is not being used to run the process. 5he &S loads a series of PSSPs ith the program code before

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letting the process run on its o n. 5he &S is the only process that can handle the code, and the code is al ays #ept separate from program data ithin the PSSPs.

1.2.2 $pportioning 5he t o preceding sections sho ed, ithout many details, ho a process ould be implemented ith a group of PSSPs. +omputers run processes in a sort of time.sharing arrangement. ?ach process ta#es a turn using the resources of the system hile all other processes ait their turn. 5he +P4 handles this time.sharing very "uic#ly, and to a user, it seems as if many things are happening at once, but this not so. Advanced systems, systems ith multiple processors, do run processes simultaneously. 8o ever, such arrangements are e(ceptions and do not represent normal computing. A system built of PSSPs ill run numerous processes simultaneously as an ordinary part of its operation. 5his is hy the system is designed as it isDto achieve a tremendous increase in throughput by spreading the or# among numerous processes, running simultaneously. &ne aspect of this increase in throughput is to decentrali6e the processing and control to the ma(imum e(tent, to spread it evenly throughout the entire system. Another aspect is the full integration of memory and /;& ith processing and control. 5hese t o aspects account for the development and use of PSSPs ithin the system. 5he third and final aspect is called apportioning. Apportioning is the act of dividing the resources of the system into small sections of the si6es needed for the various processes running ithin the system. ,or instance, suppose a system has a total resource base of 16 =egs of PSSPs, and has four different processes that need PSSP space. Process 1 needs - =egs of PSSP space, process 2 needs 200 #ilos of PSSP space, process - needs 1 =eg of PSSP space, and process * needs 100 #ilos of PSSP space. After apportioning, there ill be four sections of those si6es and a fifth space consisting of all the remaining PSSPsD11.* =egs. 5his seems straightfor ard and similar to ho memory is handled in systems that e already understand, but it is more concrete and a lot less comple( hen dealing ith a system built of PSSPs. Apportioning is accomplished by actually separating a section of PSSPs, both physically and logically, from all other sections of PSSPs. 5he separation is physical because there are apportioning s itches that actually sever the various buses, causing a section of PSSPs to become physically isolated. 5he section of PSSPs is logically separated from other sections because it cannot address any PSSP outside of the section that it is isolated in, nor can it send data along the data bus to any here outside its o n section. 5he isolation is physical, logical, and it is continued for as long as the process is running in that section. PSSPs in one apportioned section cannot affect the PSSPs in another section that is apportioned separately. A process in an apportioned section can only address PSSPs ithin the section that it is a part of and can only send data along the data bus to another PSSP ithin the same apportioned section. 5he &S is the only process that can set the apportioning s itches used to sever the buses, but the isolated processes cannot affect the &S either, because they are in different apportioned sections, isolated from each other. /f a programming error occurs, or a malicious attempt is made to influence the system, this isolation ill protect the system. ,ailure or corruption of a process can still occur, but the effects are isolated to that section of PSSPs. 5here is no possibility that the problem ill spread to the rest of the system. /n the preceding paragraph, / stated that a PSSP couldnAt affect a PSSP outside of its apportioned section. 5his is true, e(cept for PSSPs being used by the &S. 5he &S must be able to reach into any

PSSP Systems 3
part of the system, be able to ta#e control, if the need arises. 5herefore, several opcodes are privileged and only to be used by the &S. Part of the process of loading code into an apportioned section of PSSPs is to perform a validity chec# on the code being loaded. +hec#s verify that the code is a valid opcode and not a privileged instruction. 5he /;& system provides a means of communication bet een processes. 5he /;& system is much more e(tensive in a system built of PSSPs. ?very standard PSSP has the potential to access the /;& bus. ,urthermore, the /;& bus remains hole and undivided at all times, regardless of ho the &S sets the s itches used for apportioning. 5he /;& system is responsible for facilitating data flo bet een processes. A global control bus reaches every PSSP in the system, but it handles the global control signalsDnot data or addresses. ,or a process to reach another process it must use the /;& bus, there are no e(ceptions, e(cept for the &S and its control over the system. All data coming into or leaving a

process, an apportioned section, must do so via the /;& bus. @hen the &S is loading the process it ma#es use of the secondary address bus, the data bus, and the au(iliary data;control bus, but once the process begins se"uencing, communication bet een it and any other process, including the &S, is done via the /;& bus. 1.2.3 +imultaneous Processes @e have seen ho a process is run in a series of PSSPs, and ho a process can be isolated ithin the system. %et us complete this picture ith a fe more details, to sho ho a completed system can have multiple processes running simultaneously. @e ill begin ith a fe instructions that are uni"ue to this design. 5hen e ill tal# about the /;& system and the &S. ,inally, e ill go through boot.up to the loading of processes, and conclude this part of the boo# ith all these processes running simultaneously. @e are loo#ing for the big picture, the overall vie , so that e can better grasp the details as they come to us later. ?very process in an apportioned section ill have a series of PSSPs that handle the se"uencing of the program code in the PSSPs. 5hey are called sequencers or sequencing PSSPs. +ollectively, they are called the sequencing stack. 5hree opcodes are used by the PSSPs in the se"uencing stac#, but only one ill be presented at this time. 5he S?J instruction, an opcode, ill reside in the section of a se"uencing PSSP that holds the opcode. /n the other section of the same PSSP is the address of the ne(t PSSP to be activated. ?arlier in this chapter, during the e(ecution of the simple process, the PSSPs ere activated one at a time to accomplish the tas#. 5he se"uencer does the activating by se"uentially putting the address of each PSSP onto the primary address bus. 5he se"uencer, along ith the rest of the se"uencing stac#, behaves li#e the program counter in a conventional computer. ?very process has a se"uencer ithin its apportioned section to handle the activationDthe se"uencingDof its PSSPs. 'eginning the process, halting the process, Bumps, and returns are all handled by the se"uencing stac#. 5here is even a set of control lines dedicated to the function of se"uencing ithin each process. 5hey are called the sequence control lines, and they are local to the process. 5he &S uses a global control line to enable or disable the se"uencing in one or more processes. 4se of this control line, the sequence master control line, gives ultimate control over all se"uencing to the &S, but the &S does not do the se"uencing for any process e(cept itself. An opcode reserved for use by the &S is the =&7+ instruction. 5he mnemonic stands for Fmove code.G 5he &S uses this instruction to load a process into an apportioned section of PSSPs. 5he use of this opcode causes the contents of the processing section of a PSSP, that section that holds the program

10
data, to be put onto a set of data lines that ill deposit the data in the control section of a different PSSP. 5he control section of a PSSP is the section that holds the opcode, and the only ay to get the opcode into it is ith the =&7+ instruction. 5he code and data are not mi(ed. 5hey are #ept in different sections of a PSSP, but hen code and data are removed from a secondary storage device, it is all mi(ed together. As in a conventional system, it is stored as a series of bit values, and code is indistinguishable from data. 5he &S sorts out hich is data and hich is code, and then uses the =&7+ instruction to put the code into the control sections of the PSSPs that have been apportioned for that process. 5he only other opcodes that need to be e(amined at this time are the >&!? and >/!? instructions. >&!? is used to output data onto the /;& bus, and >/!? is used to input data from the /;& bus. %i#e the S?J instruction, these instructions are self.activating, meaning they automatically e(ecute their instruction ith each pulse of the cloc# signal. 5he >/!? instruction is slightly different from the S?J and >&!? instructionsDit is the only one of the three that cannot be disabled. 5he SJ= control line is the control line that can disable the S?J instruction. A different control line can enable or disable the >&!? instruction, but there is no similar control line for the >/!? instruction. 5hese t o instructions, >&!? and >/!?, are the gate#eepers bet een the /;& bus and a process. /n the processing section of the PSSP holding one of these instructions is a number that identifies the /;& process the gate#eeper is atching for. 5he PSSP serving as a gate#eeper atches the /;& bus for this number. @hen it sho s up and the gate#eeper also gets a signal that it is an /;& routine identification number, a Bump ill occur to an /;& routine that handles the input or output. 5he PSSP serving as the gate#eeper sends the address of the routine to the se"uencer and the se"uencer begins se"uencing at

the ne address. A return from the routine is e(ecuted at the end of the /;& routine. 5his e(planation leaves out many details of ho and hy it happens this ay. All of the details ill come later in the te(t. At this point, it is only necessary to reali6e that every process has PSSPs programmed ith these t o /;& instructions, Bust as every process has its o n se"uencing stac#. 'ecause each process is isolated in its o n apportioned section of PSSPs, it needs some ay to communicate ith the other processes. ?very process must send or receive data if it is a meaningful process, and it ill use the /;& bus for this purpose. Any data that enters or leaves the process must do so via the /;& bus, and these t o /;& instructions serve as the gate ay bet een the process and the /;& bus. 5here are many details to present to the readers ho are unfamiliar ith this system. 5he details sho a system very different from conventional systems. /t is not necessary to completely understand and memori6e all of these details at this time. All ill be repeated as they are needed, and your understanding of the system ill gro as you progress through the te(t. Ne(t, the &S ill be briefly discussed, and it ill become obvious that it is very different from most conventional operating systems. 1.2.! The ,perating +ystem 5he most noticeable thing about the &S in a PSSP.based system is hat it is not doing in comparison to a conventional &S. ,ull integration and decentrali6ation of the computing functions ithin the PSSPs of the system, along ith the ability to isolate processes ithin apportioned sections, frees the &S of the t o most burdensome tas#s of a conventional system. ,irst, the operating system is no longer in control of a +P4, so it no longer needs to ration every moment of the +P4As time. /t still rations the systems resources but this is done on a much higher level, and there is no +P4 involved. Secondly, the &S is not involved in e(ecuting the code of each process. ?ach process e(ecutes its o n

PSSP Systems 11
code ith its o n se"uencer and PSSPs. 5hese t o tas#s account for the bul# of the time used by a conventional operating system, and they are eliminated in a system built of PSSPs. At its highest level, the &S controls the bus system. Part of that tas# is configuring all of the apportioning s itches used to sever or unite the bus structures. 5his enables the &S to ration the apportioned sections among the processes. Another part of that tas#, the most important part, is ta#ing care of the /;& bus. 5he &S loads a process into an apportioned section and then releases the process to start se"uencing on its o n. 5here is no need for the &S to concern itself ith e(ecution of the process. ?ach process has the resources it needs, e(cept for the ability to communicate ith other processes. 5he only reason for the &S to interfere ith the se"uencing ithin the process is if it should need to halt the process temporarily so it can ma#e use of that portion of the bus system. All the isolated processes run simultaneously ithin the system and their greatest need ill be inter.process communication. 5his is the primary function of the &SDto facilitate and control all communications bet een processes via the /;& bus. 5o ma#e use of the /;& bus, a process needs to use the /;& gate#eeper instructions and the /;& routines that ere constructed by the &S. ?ach process, as it is loaded, informs the &S of its /;& needs. /nsofar as it is possible, the &S accommodates the process by constructing the necessary /;& routines and inserting them in the process, along ith the information necessary for the process to use them. /n this type of system, here the three basic elements of computing have been fully integrated and decentrali6ed by using PSSPs, the /;& system has also been fully integrated and decentrali6ed. /n a PSSP system, the /;& system is much more than an interface bet een the system and the outside orldDit is the interface bet een all processes ithin the system, including those that deal ith the outside orld. 5he /;& system is composed of the /;& bus, the soft are that controls it, and the capability of each PSSP to serve as an interface bet een a process and the /;& system. 5he /;& bus is connected to almost every PSSP in the system, and every PSSP connected to it has the potential for handling input and output. ,urthermore, the &S, relieved of the burden of controlling a +P4, ill spend most of its time

handling the /;& system, providing each output process time to use the /;& bus. / have spo#en of the &S and the /;& system as if they are t o different and separate processes, but this is not an accurate depiction of the situation. 5he need for speed ithin the /;& system is sufficient reason to have it run in an autonomous manner, but it ill still need to be closely integrated ith the &S. /t might even be more accurate to say that the /;& system is the &S, and that all other &S functions become secondary to the needs of handling the /;& bus. ,rom the moment the system begins operation, the /;& is given priority and is accounted for in the loading and operation of every process. @hile each process can run autonomously ithin their apportioned section, ithout /;& support they become meaningless. 5he /;& system literally binds everything together. 1.2.- Booting) "oading) and Termination 5he boot process for a PSSP system is similar to that of a traditional system, but there are some crucial differences. /n many respects, a PSSP is li#e a simplified +P4 in that it performs elements of processing and control. 4pon activation, a PSSP ill attempt to e(ecute the opcode contained ithin its control section, but this activation usually re"uires the address of the PSSP to occur on the primary address bus. 'ecause of this, one of the first things that must occur in the boot process is that the SJ= control line must go high to disable all possible se"uencing ithin the system, e(cept ithin the boot

12
process. 5he /&% control line must also go high to disable any possible activation of the /;& gate#eeper instructions. Along ith control over the control lines, control must be e(erted over the /;& bus and the apportioning s itches. 5his occurs hen po er is first applied, to prevent random occurrences of conflicting conditions that might interfere ith the boot process. PSSPs used for the boot process are li#e standard PSSPs, e(cept the opcodes ithin them are preprogrammed before system installation and unchangeable once installed. %i#e the !&= chips used for booting in a conventional system, these PSSPs contain the code that get the system started initially. %i#e a conventional system, a PSSP system needs to establish the /;& system and then begin loading its code from a secondary storage device. /n addition, many system components need chec#ing, and data structures need to be established for a fully functioning &S. &nce the components of the &S have been established other processes can be installed ithin the system. @hen the &S receives a call to assign resources to a process, it must establish the si6e of the process so it can apportion a section of PSSP resources for that process. ,or loading the process, the &S needs to configure the apportioning s itches so that the buses are temporarily available to send data to the ne ly apportioned section, and then reconfigure them to isolate the process ithin its section. 5his means the &S may need to stop se"uencing in one or more processes temporarily so that the bus sections apportioned for those processes can be used to move data to the section used for the ne process. After loading the process, the buses ill be surrendered bac# to the processes that needed them, and the ne process ill be isolated ithin its apportioned section. Part of the loading process is ascertaining hat is code and hat is data, and then chec#ing the code for instructions that are restricted for use by the &S. An analysis of the /;& needs of the process is also done, along ith construction of the /;& routines. /nformation about output routines is passed to the /;& system, and time allotments are made for these routines ithin the /;& systemAs time.sharing scheme. After the process is fully loaded and isolated ithin its apportioned section, the &S ill set the SJ= control line in that section lo . @hen this line goes lo , it permits se"uencing to commence ithin the process. 5he process is completely isolated and se"uences on its o n once this happens, and the only ay it can communicate ith anything outside itself is by sending messages via the /;& system. Similar to the loading of one process is the loading of all other processes, the only limitation being the resources of the system. Assuming there are enough apportionable sections of the si6e needed for FKG number of non.system processes, at the end of loading FKG number of processes, there ill be FKG number of processes, plus the &S processes, running simultaneously ithin the system. All processes ill be running independently of each other e(cept for the flo of messages and data bet een them, hich can only occur via the /;& system.

Process termination is normally accomplished ith the process running its termination routine. 5his routine sends a signal to the &S that the process is finished and can be terminated. After sending this message to the &S, the process ill go into a N&P loop hile it aits for the &S to set its section of the SJ= control line to the correct state to disable se"uencing ithin the process. &nce this is done, the &S ill then ta#e the necessary steps to recover the PSSPs used by the process and remove any references to it from the &S system. 5his is not the only ay a process can be terminated, but it is the normal, or preferred, method. 5his completes the overall vie of a system built around the use of PSSPs. 8opefully, the reader no has a good idea of hat the system is capable of, and ho it is accomplished. $etails ill follo

PSSP Systems 1in the rest of the boo#, beginning ith a more in.depth loo# at the PSSP, since its capabilities and design are at the core of the systemAs design. A thorough understanding of the PSSPs ill facilitate an understanding of the rest of the components ithin the system. 'ut before going on, a recapitulation of this chapter is provided. PSSPs enable a system to overcome the limitations and problems associated ith the increasing comple(ity and centrali6ation of current system designs. PSSPs are designed to integrate processing, control, memory, and /;& into individual units. A multitude of the individual units is used to collectively accomplish all computing functions ithin the system. @ithin these devices, the code and program data are #ept separate and only the &S can move the code. A bus system that can be divided into sections enables an apportioning process that allo s programs to run simultaneously and independently ithin the system. +ommunication bet een these simultaneously running programs is facilitated by an /;& system that reaches into every portion of the system. +ontrol of the /;& system is the primary function of the operating system, hich also handles the apportioning of system resources.

12

PSSPS Fun tion and Desi!n

ecentrali6ed processing units handle all of the processing, control, memory, and /;& functions needed ithin a computer. No single PSSP is more functional than any other PSSP, but they may have different functions. 5he PSSPs or# together to handle all the functions a central processing unit handles in a conventional system. @hile some PSSPs ithin the system are dedicated to one function, this is not so for the maBority. =ost are general purpose in design and are able to handle almost any of the functions needed ithin the system. 5hey are designed to have the same capabilities and the same connections to the buses. @ithin this te(t, e(cepting the modified PSSPs that are read.only and used for booting the system, there are three basic types of PSSPs. =ost abundant are the general purpose PSSPs referred to as standard PSSPs. 5his type can handle any operation e(cept se"uencing and /;& gate#eeper functions. 5he other t o types are speciali6ed PSSPs dedicated to particular functions that standard PSSPs cannot handle. &ne is used for the three se"uencing instructions, and the other is used for the t o /;& gate#eeper instructions. 5he PSSPs that are modified to be read.only and used for booting are Bust li#e the three basic types, e(cept that their code, data, or both may be in read.only form. ?ach PSSP is designed to hold one instruction from the set of instructions. 5he instruction is programmed into the PSSP ith soft are, hich means the operating system loads the code into the control section of the PSSP. A PSSP can handle only one instruction at a time. 5o handle a different instruction, it must be reprogrammed ith the ne instruction. ?ach instruction may have one operand, t o operands, or no operand at all. ?ach instruction ill also have a result. 5he result can be a piece of data that is held until it is needed, or it can be a control action, such as setting a control line high or lo . ?ach PSSP can hold one operand before the operation. After the operation, it may hold the

original operand or the result of the operation, if the result is a data obBect. ?ach PSSP is programmed to do its part ithin a process. Some are used to fully activate other PSSPs, hile others are used to perform an operation on one or t o operands. 5hey may move data around, cause a Bump in the se"uencing of the process, atch the /;& bus, or provide an element of control for the process or system. ?ach PSSP ill do its part, hen it is activated, to fulfill the tas# assigned to the group. &nly one standard PSSP is fully active at any particular moment ithin a process. 8o ever, the self.activating PSSPs, hich are used for dedicated tas#s, ill be fully active at the same time as the standard PSSP. /n addition to PSSPs that are fully active, other PSSPs may only be partially active. 5he differences bet een a fully and partially activated PSSP ill be e(plained in detail after PSSP design has been presented. /t is important to reali6e that in any particular group of PSSPs being used for a process, a tremendous amount of activity is going on. @ithin a system, here many processes are running simultaneously in different apportioned sections, many do6ens of PSSPs are active to some degree and participating in the or#load. 5his is a normal level of activity for a PSSP system.

D
16
2.1 +eparation o' Code and #ata ?ach PSSP is composed of t o sections, the processing section, and the control section. 5hese t o sections are different in structure and function, but they do share some common characteristics. ?ach section is dependent upon the other, but they can also act independently of each other at times. 5ogether, the t o sections ma#e up a PSSP that is capable of handling a predetermined "uantity of data during one e(ecution cycle. 5he processing section re"uires direction from its control section as to hat operation it should perform, but it can also be directed to read or rite data hen receiving control signals from the control section of a different PSSP. Similarly, the control section directs the processing section to ta#e an action, and then that processing section can directly influence the control section of a different PSSP. /n all cases, the control section of a PSSP initiates the action or series of actions. 5his is al ays true, regardless of the type of PSSP involved. PSSPs must have certain capabilities in order to function as they are e(pected ithin a system of PSSPs. 5hey must be capable of performing as memory and holding their data until it is needed. 5he processing section of every PSSP has a latch for each data bit it must hold, and its control section has a latch for each bit of opcode it must hold. ?ach PSSP must possess a minimal set of processing and control capabilities so it can manipulate the program data or perform control functions. &nly the processing section has processing capabilities, and only the control section has the capability to handle the various aspects of control needed ithin the system, process, or PSSP. All PSSPs are referenced ith a uni"ue address. All are logically organi6ed so that their addresses are linearly arranged. 5he first address is follo ed by the second, follo ed by third, all the ay up to the highest address. ?ach address refers to the entire PSSP, but it can be used to activate either of the t o sections of the PSSPDthe control section or the processing section. /f the address of a PSSP appears on the primary address bus, the control section of that PSSP is activated, hich in turn activates the entire PSSP. /f the address appears on the secondary address bus, only the processing section ill be activated for the reading or riting of data. /n addition, it is possible to activate the processing section of a PSSP ith any one of the four bilateral control lines of the bilateral control bus. ?ach PSSP can hold program data and program code. Program data and program code are #ept separate. Program data can be operands, addresses, or any other data obBect used by the program code. Program codes are the instructions that tell PSSPs hat actions to ta#e. &ne of the instructions enables a PSSP to handle program code as program data, but the instruction is restricted for use by the &S.

&nly the &S can use this instruction to move code into the control section of a PSSP. 4ntil code is put into a control section it is considered to be data and ill reside in the processing section of a PSSP, or in secondary storage. 5he program data is #ept in the processing section of a PSSP. 5he program code is #ept in the control section. No process, e(cept the &S, has access to the opcode bits of a control section, or is able to change an opcode once it is in a control section. 5his is one of the many advantages of this system in regards to system security and stability. 5here is a method that is used for output and se"uencing instructions, hich ill be discussed later, in hich an opcode can be enabled, or disabled, as needed, but the opcode is not really changed.

PSSP Systems 1)
2.1.1 Processing +ection o' P++Ps 5he processing section of a PSSP handles all processing and storage of data. 5his includes the input and output of data via the /;& bus. 5he processing section of a PSSP is under the direction of the control section of the same, or another, PSSP. /n a conventional system, all processing is done in the central

19
processing unit, each instruction decoded and e(ecuted as it is brought to the +P4. /n a PSSP system, the processing is spread out in the system, ith each process e(ecuting instructions as they occur ithin the PSSPs at its disposal. ?ach PSSP ith an instruction ill e(ecute the instruction each time that it is fully activated. /t ill not e(ecute any other instruction until it has been reprogrammed to do so. System memory is handled by the processing sections of the PSSPs ithin the system. 5here is no separate memory area, or memory devices, e(cept secondary mass storage devices, such as a hard dis#. 8o ever, it is possible to set aside portions of the PSSPs ithin a process, to be used solely as storage. $ata, in all its forms, is stored in the processing section of PSSPs. ?ach processing section can hold one set of bits that represent the basic data si6e of the system, hether it is bytes, ords, or some larger entity. @hile the code in the control section is static until the &S changes it, the data in the processing section can be changed by the instruction in the control section of any PSSP ithin the apportioned section of PSSPs. 5he processing section of a PSSP can be activated by the control section of the PSSP that it is a part of, or it can be activated by the control section of another PSSP. A processing section activated by its o n control section processes its data as directed by the opcode in the control section. 5his activation is referred to as full activation. A processing section activated by the control section of some other PSSP is only activated to read or rite data. 5his type of activation is referred to as partial activation. ,ull activation of a PSSP causes the activation of the control section, and the control section then causes activation of the processing section of the same PSSP. ,ull activation of a PSSP can only result from the se"uencer putting the PSSPAs address onto the primary address bus, or from the PSSP being self.activating. Secondary activation of a processing section occurs hen the opcode of a fully activated PSSP re"uires the processing section of another PSSP to read or rite data. /n this case, the data is read or ritten, but it is not processed in the partially activated PSSP. 8o ever, the data in the partially activated PSSP may be needed for processing ithin the fully activated PSSP that caused the partial activation. Partial activation is caused by the PSSPAs address appearing on the secondary address bus or by a control signal from one of the t o adBacent PSSPs via a bilateral control line. ,ull activation of a processing section occurs henever a PSSP is activated by its address appearing on the primary address bus, hich only occurs hen the se"uencer selects that address as the ne(t to receive full activation. 8o ever, in the case of the three self.activating instructions, full activation is constant and automatic for PSSPs containing them, if the instruction is enabled. Secondary activation occurs hen a PSSP receiving full activation by the primary address bus needs to retrieve or store an operand re"uired by the operation being performed in the processing section. /n other ords, if the fully activated PSSP needs to retrieve or store an operand, it ill cause partial activation of t o other PSSPs. &ne PSSP contains the address of here the operand is, or here it ill be put. 5he other contains the operand.

5he number of bit positions in the processing section, the basic data si6e in the system, is the same as the number of bit lines in the data bus, the /;& bus, and each address buses. ,or each bit position of the processing section there is an A%4, a one.bit latch, and a corresponding bit position in the data flo controller. 5he number of bits in the processing section is e"ual to or greater than the number of bits in the control section. $ata entering the processing section from the data bus or the /;& bus ill enter the A input or the ' input of the A%4. 5he A%4 for each bit position has these t o e(ternal inputs and an internal carry input for arithmetic operations. /t is also possible to re.input the data that is in the latches of the

PSSP Systems 13
processing section hen it is needed for instruction e(ecution. 5he output from each one.bit A%4 goes to the one.bit latch for that bit position. 5he latches for all of the bit positions in the processing section function as the memory for the PSSP, and the memory of all the PSSPs function as memory for the entire system. 5he latch of each bit position outputs into the data flo controller that serves to route the data to the correct location. @hen full activation of a PSSP occurs, the opcode in the control section directs the output from the data flo controller. /n partial activation caused by the secondary address bus, the signal on the !;@ control line directs data flo ith respect to the data bus. /n partial activation caused by a bilateral control line it is the control line that ill direct data flo ith the data flo controller. 5he signals on the bilateral control line are controlled by the fully activated PSSP that has caused partial activation of the other PSSP. 5he A input to each one.bit A%4 can enter from the data bus, the /;& bus, or internally, from the data flo controller. /f it comes from the data flo controller, either it is being re.input from the latch of that bit position, or it is coming from an adBacent bit position, as in the case of a shift instruction. $ata entering the A input from a move instruction ill go through the A%4 on its ay to the latch. /f an instruction re"uires a second operand, the second operand ill enter the A%4 via the ' input hile the operand already in the latches is re.input to the A input. @hen input is processed by the A%4, flag signals may be generated as the result of arithmetic and logical operations. 5hese signals ill go to the data flo controller, and then bac# to the control section. 5hen the control section ill set the flag control lines accordingly. 5he latch holds the output of the A%4, and there is a latch for each bit position of the processing section. @hen one or more operands are needed for an operation, the latches may hold one before the operation. /n operations that create a data result, the result of the operation ill be deposited into the latches of the PSSP that performed the operation. /f an operation does not generate a data result, as in situations here the opcode is a control function and the operand is a control value, the latches ill still hold the original operand at the end of the operation. 5he output of the latches goes to the data flo controller, hich ill also have bit positions corresponding to the rest of the processing section. 5he data flo controller routes the output of the latches to the correct destination. /t receives guidance from the control section, from the secondary address bus, in conBunction ith a signal on the !;@ control line, or from a bilateral control line. /nstructions may re"uire that the data in the latches be re.input, in hich case, the data flo controller ill route it bac# to the A input, possibly to be processed ith data from the ' input, of the A%4. /n the case of a shift instruction, data from a latch ill be sent to the A input of an adBacent bit position. An increment instruction ill cause the data flo controller to send a high signal to the ' input of the lo est bit position. 5his ill be added to the A input being re.input from the latches. 5he carry output for each bit position does not go through the data flo controller. /t goes directly to the carry input of the ne(t highest bit position. 5he carry output of the highest bit position ill go to the data flo controller, hich uses it to set the carry flag control line. 4nder normal circumstances, the output from the data flo controller can be put onto the data bus, the secondary address bus, or the /;& bus. ,or the se"uencing instruction, and only this instruction, the output from the data flo controller goes onto the primary address bus. A privileged instruction used by the operating system, =&7+, ill cause the data flo controller to output the data from the latches onto the au(iliary data;control bus. 5his ill cause the data to be

deposited into the opcode latches of the control section of the PSSP addressed by the secondary address bus. &utput from the latches to a bus does not cause any change in the contents of the

20
latches. ,lag signals, generated by A%4s, are sent to the data flo controller, hich ill use individual bit signals to generate a composite signal that is sent bac# to the control section of the PSSP via the internal signal flo bet een its t o sections. A PSSP designed for the se"uencing stac# has a processing section that is much less complicated than a standard PSSP. ,or se"uencing, the processing section only needs to hold an address that is incremented or replaced. 5he only operations needed ithin the A%4s of a se"uencing PSSP is to increment by one or t o. ,lag signals are not needed, and the ' input is only needed for the t o lo est bit values. 5he output from the latches can only be put onto the primary address bus, hile input can only come from the data bus. 5his greatly simplifies the design of the processing section of a se"uencing PSSP. 5here is a group of control lines that can influence the processing section of all PSSPs. 5hey are called the bilateral control lines, collectively #no n as the bilateral control bus. 5hese control lines ill be discussed thoroughly in the section detailing system bus structures, but a fe details about them ill be given at this time. 'et een every PSSP and the t o PSSPs logically adBacent to it, there are t o control lines. ,or each PSSP, there are t o control lines going to the address that precedes it and t o other control lines going to the address that follo s it. 5hese control lines are used by the fully activated PSSP to partially activate an adBacent PSSP. 5he partially activated PSSP ill read or rite data used by the fully activated PSSP that sent the signal on the bilateral control line. 5hese signals go from the control section of the fully activated PSSPs to the control section of the adBacent PSSPs, and pass to the processing section of that PSSP. 5his ill become clearer as more #no ledge is gained on ho PSSPs handle instructions that have an indirectly addressed operand. 2.1.2 Control +ection o' P++Ps 5he control section of a PSSP is used for all functions e(cept storage and processing of data. 5he control sections of the PSSPs must generate all the local and global control signals for the system, for every process, and each PSSP as it is activated. 5he only e(ceptions to this are the cloc# and po er signals, hich are autonomous. /n many instances, the processing section ill hold the control variable, such as the state a control line should ta#e, but it is the control section ta#es the action and sets the control line to the correct state. 5he processing section holds data and does data processing, but the control section initiates all actions. 5here are three types of control signalsDglobal, local, and internal. ?ach has their o n control bus, or control lines. <lobal control signals flo on the global control bus and are e"ually and constantly available to all PSSPs, regardless of the apportioned section to hich the PSSPs belong. %ocal control signals flo on the au(iliary data;control bus or the bilateral control bus, and are confined to a process isolated ithin an apportioned section of PSSPs. 5he local control signals are only available during the se"uencing of a process. $uring se"uencing, local signals may be under the control of one or more PSSPs. 5hey do not al ays emanate from the fully active PSSP. 5he PSSPs that have been activated have the capacity to behave much li#e a status register in relation to the control signals, maintaining the state of the signal even hen they are no longer actively e(ecuting their opcode. /nternal control signals flo bet een the control section and the processing section of a PSSP. 5hese signals are most active hen the PSSP is fully activated, but some internal signals are also present during partial activation, as hen a PSSP

PSSP Systems 21
sends a signal on a bilateral control line to partially activate an adBacent PSSP. 5he bilateral control signal ill go to the control section of the adBacent PSSP, and then on to the processing section via the internal signal flo . 5he t o basic structures ithin the control section are the opcode latches and the decoder circuits. 5he opcode latches hold the opcode programmed into the control section of the PSSP. 5he opcode

controls the actions of the entire PSSP in hich it resides. As a secondary matter, it may also influence an adBacent PSSP, or a PSSP else here in the apportioned section. /n the case of PSSPs used by the &S, the opcode may affect global control signals that can affect any part of the system. 5his influence can only be e(erted during full activation by the primary address bus. %ac#ing full activation, the control section of a PSSP can do nothing e(cept maintain the condition of a control line, or transmit the signal from a bilateral control line. /f the PSSP is fully activated, it can directly affect the processing section of an adBacent PSSP ith a bilateral control line. /t can also directly affect the processing section of another PSSP by causing an address to be put onto the secondary address bus in conBunction ith a signal on the !;@ control line. 5he opcode latches get their input from the au(iliary data;control bus, hich can only occur during the programming, or loading, of the PSSPs by the &S. $ata is not usually put onto the au(iliary data;control bus. 5he =&7+ instruction, a privileged instruction only used by the &S, provides the means to put the data onto this bus so it can be routed to the control section of a PSSP. 5his is the only ay the opcode latches can receive data. No other instruction has the capability of affecting these latches. 5he au(iliary data;control bus is used to put the code into the control section of a PSSP only hen the process is being loaded. @hen a process is running by itself, the au(iliary data;control bus is used for control signals local to that process. =ore details about this dual.purpose bus, and the other buses, ill be given later. ,or no , understand that this bus, the global control bus, and the bilateral control bus are the only three e(ternal buses ith connections to the control sections of the PSSPs. 5he au(iliary bus is the local control bus hen a process is se"uencing. 5he &S uses the global control bus for system control. 5he bilateral control bus carries signals bet een adBacent PSSPs for partial activation. 5he internal bus is the one that carries the control signals bet een the control section and the processing section of a PSSP. Normally, an opcode cannot change hile a process is running. 8o ever, in the se"uencing stac#, the PSSPs can s itch bet een an active and inactive state, but this is an e(ception. Also, the >&!? instruction can be enabled or disabled ith a local control line, but the opcode doesnAt really change. ?(cept for these t o instances, opcodes are unchanging once the &S has loaded them. ,or an opcode to be changed se"uencing of the process ould need to be stopped so that the &S can ma#e use of the au(iliary bus. 5he number of bit positions in the control section of a PSSP is e"ual to, or less than, the number of bit positions ithin the processing section of a PSSP. 5he number of bit positions ill also e"ual the number of bit lines of the au(iliary data;control bus. ,urthermore, since the bit positions represent the latches that hold the opcodes, there is a direct relationship bet een the number of bit positions in the control section and the number of instructions possible ithin the set of opcodes. 5he decoder circuits are the most comple( part of a PSSP. 5hey generate all the necessary control signals for the entire system, but this is not all done by one PSSP. =any different PSSPs, ithin different processes and different apportioned sections, or# to generate the correct control signals. $ecoder circuits must decode the incoming signals and generate the necessary combination of output signals. /nputs to the decoder come from the opcode latches, the au(iliary data;control bus, the global

22
control bus, the bilateral control lines, and the internal signal flo coming from the processing section. 8o ever, the number of inputs that need to be handled by any particular PSSP ill depend upon the opcode it is assigned to e(ecute.

PSSP Systems 25he input to the decoder from the opcode latchesDthe opcodeD ill control the basic functioning of the entire PSSP hen it is fully activated by the primary address bus. @ithin the opcode itself is the necessary information to provide control for the A%4s, the data latches, and the data flo controller of the processing section. 5he information in the opcode specifies hich function the A%4 should perform, from hich bus the data is received, to hich bus the data should output, hich flag control lines should be set, or a combination of these. /nformation from the opcode is used in conBunction ith other data entering the decoding circuits of the control section. ,or instance, a conditional Bump

instruction needs information pertaining to the condition of a particular flag control line. ,or the instruction to be e(ecuted, the state of the flag control line needs to be ascertained before the correct signals can be sent to the processing section. Also providing inputs to the decoding circuits are the local control signals that come in via the au(iliary data;control bus. 5his bus acts as a control bus once se"uencing has begun ithin the process, therefore, if the PSSP has been fully activated, the signals on this bus are control signals. 5hese signals are used as input to the decoder circuits and they ill change state hen the PSSP e(ecutes its opcode. 5hey include flag signals generated in the processing section of a PSSP, the !;@ signal used for data transfers, the /;& enable signal used to control the >&!? instruction, and the three local se"uence control lines. As each PSSP is fully activated, it ill influence, and may be influenced, by one or more of these signals. 5he global control bus also provides inputs to the decoder circuits, but these inputs only concern control signals that are global in scope. 5he local process only uses these signals hen it involves some aspect of shared system resources. ,or instance, a high signal on the /&! control line, hich is a global control signal, is a signal to all PSSPs actively using the >&!? instruction that the data on the /;& bus is the identification number of an /;& process. 5he signal is a global signal, dealing ith a shared resourceDthe /;& bus. 5hese global control signals are autonomous or generated by the &S and cannot be influenced by a local process. Some of these signals are set ith instructions that are privileged to the &S. /n addition to the /&! control line, the global control bus includes signals used by the operating system for apportioning the buses, the t o cloc# signals, the +@? control signal, and the SJ= control signal. 5he decoder circuits also get signals from the processing section of the same PSSP via the internal signal flo that e(ists bet een the t o sections of the PSSP. <oing from the control section to the processing section are the signals that provide control over the processing section. 5here may also be flag signals going from the processing section to the control section. 5he flag signals are generated ithin the data.flo controller of the processing section. /t combines all the bit signals from the bit positions of the processing section, and then a composite signal is sent bac# to the decoding circuits of the control section via the internal signal flo . 5he decoding circuits then sets the flag control line of the au(iliary data;control bus to the appropriate state. @ith the design outlined in this te(t, three possible flag signals are generated ithin the processing section and made available for Bump instructions. 5here is no flag register in this system, but a PSSP generating a status flag condition ill hold the state of that particular flag until it changes. 5he PSSP responsible for changing the state of the flag is also responsible for maintaining the ne state. An instruction using one of the signalsDsuch as a Bump instructionD ill cause it to be reset. /t can also change state hen another arithmetic or logical operation is e(ecuted. 5he signals are available on the flag control lines of the au(iliary data;control bus to all PSSPs ithin the local apportioned section.

2*
5he output from the decoding circuits goes to the global control bus, the local control bus, the processing section, a bilateral control line, or some combination of these. Signals are only put onto the global control bus if the process in "uestion is the &S. 5he &S is the only process that can use the privileged instructions that set the global control lines. Some signals of the global control bus, such as the cloc# signals, are constant and autonomous in nature, and cannot be influenced by any process. &ther signals on the global control bus must be set by the operating system and cannot be influenced or controlled by any other process. All of the local control bus signals are generated ithin the process of hich they are a part. /n ordinary use, they cannot be overridden or influenced by the &S, but at certain times the &S can send a signal on the SJ= control line that overrides the se"uencing signals of the process. 5his only occurs hen the process has failed in some manner, has signaled its termination to the &S, or the &S needs to ta#e control of the local bus sections to load a process. %ocal control lines include the three se"uence control signals, the /&% control signal, and the flag status control signals. 5he three se"uence control lines are not li#e other local control lines. A standard PSSP ill set these lines as an ordinary part of

opcode e(ecution, but a standard PSSP cannot be affected by the condition of the three se"uence control lines. 5he se"uencing PSSP cannot change or set these lines, but the lines ill have a direct influence on the behavior of the se"uencing PSSP. 5here are signals from the decoding circuits that go directly to the processing section of the same PSSP. 5hese signals affect the behavior of the A%4s, the data latches, and the data flo controller. @hen a PSSP is fully or partially activated, these signals can affect all parts of the processing section. Processing is never done during partial activation, but the A%4 must still be controlled for reading or riting data. $ata may need to be received into the latches through the A input of the A%4, or data may need to be output to the data bus, secondary address bus, or the au(iliary data;control bus. ,or instructions that re"uire indirect addressing of an operand, a control signal ill be sent to one of the t o adBacent PSSPs via one of the bilateral control lines. /n such cases, the signal is sent to the decoder circuits of the control section in the adBacent PSSP. ,rom there, the control section of the adBacent PSSP ill send the correct signals to its processing section. 4ltimately, this control signal ill cause partial activation of the affected PSSP. 5he processing section of the partially activated PSSP ill then read or rite data via the indicated bus. ,our different signals can occur on the bilateral control lines. ?ach signal ill result in a different action ithin one of the t o adBacent PSSPs. /t is not necessary for all global control signals go to every PSSP ithin the system. @hether or not they do depends on the intent behind the system design. &ne of the strengths of this system is its uniformity. &ne section of PSSPs is much li#e any other section. 5he degree of speciali6ation designed into a particular system ill greatly affect here the system process resides. ,or instance, if a group of PSSPs is speciali6ed to handle opcodes restricted for use by the &S, the &S must reside ithin that section of PSSPs and cannot be relocated. /f the design re"uired a system more tolerant of PSSP failure, these instructions ould be built into all PSSPs or multiple sections of PSSPs, so that the &S could be relocated, if necessary. @ithin a non.system process it is only the speciali6ed PSSPs, the se"uencers and /;& gate#eepers, that respond to any of the global control signals. 5herefore, ho e(tensively the global control bus is connected to the PSSPs ithin the system depends on the intent behind its design. A PSSP designed for se"uencing has a control section that differs from the control section of a regular PSSP. 'ecause they are specifically designed for se"uencing, they only need to be able to handle the three opcodes involved in the se"uencing stac#. 5hey do not generate any control signals, and only respond to the four se"uence control signals and the t o cloc# signals. ,ull details of the

PSSP Systems 22
se"uencing stac# ill be given later in the te(t. 8ere it is only necessary to reali6e that the se"uencing stac# functions are limited to those three instructions and this ill cause them to be designed differently from the standard PSSPs. 2.1.3 #ata .lo& and $cti%ation /t is orth hile to include this section to give details on ho data flo s ithin a PSSP system and ho the t o different levels of activation are achieved. 5he information has already been given in previous sections of the te(t, but in different conte(ts. /n this section, it ill be the focus, so that the reader can see it ith a completeness that isnAt provided else here. @ithin a PSSP system, there are t o different address buses, the primary address bus, and the secondary address bus. 5here is one data bus, one /;& bus, and one global control bus. 5here is also one other bus, the au(iliary data;control bus, that acts as a data bus part of the time and a control bus at other times. /n addition, there is the bilateral control bus , hich is not at all li#e a standard bus. All of these buses ill be discussed in detail in another section, but it is necessary to present them here, briefly, before discussing the flo of data ithin the system and ho PSSPs are activated. 5he global control bus, hich is used for system ide control signals that do not involve PSSP activation or data movement, and the t o address buses, along ith the bilateral control bus, hich are used for activation of PSSPs ill be set aside for the moment. 5he data bus and the /;& bus are never used for addressing, only for the flo of data, and these t o buses ill be loo#ed at after discussing the au(iliary data;control bus. 5his bus ill be dealt ith first because, unli#e other buses, it has uni"ue aspects ith hich most readers are not familiar. =uch has already been said about the au(iliary data;control bus that is often referred to as the au(iliary

bus. As its name implies, it has t o functionsDone is as a data bus, and the other is as a control bus. 5hese t o functions occur at different times, so there is no conflict ith the bus being used for both functions. &riginally there ere t o separate buses ithin this design, each ith its o n function. 5he reali6ation that these t o functions could coe(ist ithin one bus structure led to the dual.purpose bus. 5he bus is only used for data transfer hile a process is being loaded into an apportioned section of PSSPs. 5he input for this bus, hile it is being used as a data bus, can only come from the processing section of a PSSP being used by the &S to transfer data. 5his data is actually program code being moved from a secondary storage device to the control section of PSSPs being loaded ith code. 5he &S ill use the =&7+ instruction to load the code, and the section of PSSPs being loaded ill not have begun se"uencing yet. After the code has been loaded, the &S ill permit the process to begin se"uencing. At this point, the au(iliary data;control bus ill no longer be a data bus. &nce se"uencing begins it ill become the local control bus. 5he bus as only used for data transfer hile the process as inactive. &nce the process is active it ill be used for control signals confined to the process. 5he bus is used for control signals for as long as the process is actively se"uencing ithin the apportioned section. @hen the process terminates, the bus ill become inactive until the &S again loads a process into that section of PSSPs. &ther than that special use of the au(iliary bus for data transfer by the &S, all data transfers ithin the system occur on the data bus or the /;& bus. 5he /;& bus is used for data transfers bet een processes isolated from each other, hile data flo ithin a process al ays occurs on the data bus. 5echnically, it is not possible for a process to recover the same data from the /;& bus

26
that it is putting on the /;& bus, so it is not possible to use the /;& bus for data flo ithin a process. Similarly, the data bus is an apportioned bus, and it is not possible for it to be used for data flo bet een isolated processes. @ithin a process, the data bus is the only bus used for data flo bet een PSSPs. 5he data bus is one of the apportioned buses. 5his means it is divided into sections, ith each section being assigned to a process. @hen the data bus is mentioned in relation to a process, it should al ays be understood that only the section of the data bus assigned to that process is being referred to, not the entire data bus. 5his is important because many processes are running simultaneously, and each process ma#es its o n independent use of its assigned section of the data bus. 5his is not so for the /;& bus. 5he /;& bus is not apportioned or subdivided in any ay. /t is hole and complete throughout the system. /t has connections to every standard PSSP ithin the system, regardless of here the PSSP is or to hat process it is assigned. Putting data onto the /;& bus is done in a strictly controlled manner. /t is not possible for a process to use it for data transfer bet een processes, e(cept for hat has been planned. @hen a process is loaded, all of its input and output needs are ascertained by the &S and must be accounted for ith sections of code that the &S inserts into the code of the process. 5his is a very important point to #eep in mind. All /;&, in particular the output, is planned and controlled. 5his does not mean a process cannot decide hen it might ant to output data, but it does mean that it must as# permission to output data onto the /;& bus, and then ait for permission to be given. ?ven the &S has to follo the protocols set up for the use of the /;& bus. 5hat covers hat the reader needs to #no right no about the au(iliary bus, the data bus, and the /;& bus. Ne(t come details about the t o different address buses and the bilateral control bus. 5hese buses are used to activate the PSSPs, either fully or partially. &f the three buses, only the primary address bus can cause full activation. /t is referred to as the primary address bus because it is used to begin e(ecution of an instruction. 5he secondary address bus is not used ith every instruction, only ith instructions that have an indirect operand. 5he secondary address bus and the bilateral control lines can only cause partial activation. ,ull activation causes the control section of the PSSP being activated to e(ecute the opcode in its opcode latches. All opcodes need to be in the control section of a PSSP before they can be activated.

5here is no ay they can be e(ecuted else here. &nly hen data has been put into a control section does the data becomes code. &nce the code is in a control section, the PSSP of hich that control section is a part must be fully activated by the primary address bus for the code to be e(ecuted. 5his is the only ay an opcode can be e(ecuted, e(cept for the three self.activating, or self.enabling, opcodesDS?J, >&!?, and >/!?. 5hese three opcodes do not need activation by the primary address bus or any other bus, but there is a method to enable or disable the >&!? and S?J instructions. Partial activation refers to the processing section of a PSSP being activated for the reading or riting of data. 5he processing section cannot do any processing hen it is partially activated. /t can accept data from the data bus, or it can put data onto the data bus or the secondary address bus. /n the case of the =&7+ instruction, restricted for use by the &S, data can be put onto the au(iliary data;control bus. Partial activation can be achieved by the secondary address bus or by one of the control lines of the bilateral control bus. Partial activation by the secondary address bus is al ays accompanied by a signal on the !;@ control line, e(cept for the =&7+ instruction, in hich case it ill be accompanied

PSSP Systems 2)
by a signal on the +@? control line. Partial activation caused by a bilateral control line is al ays directed to ards one of the t o adBacent PSSPs. /t is not accompanied by any other control signal. 5here are four of these bilateral control lines to affect four possible actions by an adBacent PSSP. /n a conventional system, the address bus is used to select a memory address for reading or riting. 5he selection is al ays done by the system +P4 as part of an instruction e(ecution cycle, and the

29
+P4 is al ays in control of the address bus. /n a PSSP system, each PSSP is given temporary control of the secondary address bus. An e(ception to this is the se"uencing instruction that is given total control of the primary address bus. Not every instruction needs to use the secondary address bus, and in those cases, it ill remain idle until an instruction needs to use it. 'oth address buses are apportioned, so their use is local to the process involved. ?(cept for the three self.activating instructions, every instruction e(ecuted in a PSSP has been fully activated by the primary address bus. /f an e(ecuted instruction has an indirect reference to an operand, partial activation ill occur to t o other PSSPs. Partial activation ill occur to the processing section of one of the t o adBacent PSSPs via a bilateral control line, and partial activation of the processing section of the referenced PSSP ill occur ith the secondary address bus, in conBunction ith the !;@ control line. /f an e(ecuted instruction re"uires t o operands, the first ill be in the processing section of the PSSP ith the instruction, and the second ill be referred to indirectly ith an address in the processing section of the PSSP, follo ing the instruction. 5hat PSSP ill be partially activated ith a bilateral control line, and the processing section of the addressed PSSP ill be partially activated ith the secondary address bus and the !;@ control line. $cti%ation +e/uence 'or Instructions Includes all except the three sel'0acti%ating instructions 1hen the se/uencer puts an address on the primary address us) the P++P at that address is 'ully acti%ated 'or execution. 1hat 'ollo&s 'ull acti%ation depends on the num er and type o' operands that the instruction needs. 2ero ,perand 3 Partial acti%ation is not re/uired4 there is no operand. ,ne ,perand #irect 3 Partial acti%ation is not re/uired. The operand is in the processing section o' the 'ully acti%ated P++P. ,ne ,perand Indirect 3 The source or destination address is in the processing section o' the 'ully acti%ated P++P. Three di''erent situations can occur. 1. +ource o' the operand is the address in the processing section o' the P++P that is 'ully acti%ated. +ource is partially acti%ated y the secondary address us and the 561 control line. #estination o' the operand is the processing section o' the P++P that 'ollo&s the 'ully

acti%ated P++P. #estination is partially acti%ated y the $.#1 ilateral control line. 2. +ource o' the operand is the processing section o' the P++P that precedes the 'ully acti%ated P++P. +ource is partially acti%ated y the $P#5 ilateral control line. #estination o' the operand is the address in the processing section o' the 'ully acti%ated P++P. #estination is partially acti%ated y the secondary address us and the 561 control line.

PSSP Systems 23
3. +ource o' the operand is the processing section o' the P++P preceding the 'ully acti%ated P++P. +ource is partially acti%ated y the $P$5 ilateral control line. #estination o' the operand is the address in the processing section o' the 'ully acti%ated P++P. #estination is partially acti%ated &ith the secondary address us and the C17 control line. T&o ,perands 3 The 'irst operand is in the processing section o' the 'ully acti%ated P++P. The source o' the second operand is the address in the processing section o' the P++P 'ollo&ing the 'ully acti%ated P++P. The processing section holding the source address o' the second operand is partially acti%ated y the $.$5 ilateral control line. The source o' the second operand is partially acti%ated y the secondary address us and the 561 control line. The destination o' the second operand is the B input to the $"8. The 'irst operand is reinput into the $ input o' the $"8. ,ull activation is achieved by the primary address bus, hich is al ays controlled by the se"uencer once se"uencing has begun. 5he se"uencer has an address in its processing section. /nitially, the &S put this address there as it loaded the process. @hich address should be put there as decided by the &S, using information obtained from the process and then adBusted by the &S so that it fit the particular section of addresses apportioned for the process. As the process begins se"uencing, e(ecuting instructions, the address ill be adBusted as each PSSP is activated and its instruction is e(ecuted. =ost instructions ill cause the address to be incremented by one or t o. 5he three separate se"uence control lines that every instruction temporarily sets control this. ?ach instruction e(ecuted via the se"uencer ill set each of the three se"uence control lines either high or lo . 5he section on se"uencing PSSPs ill give all the details about se"uencing and the use of these control lines. As each instruction e(ecutes, it ill cause the address ithin the processing section of the se"uencing PSSP to increment by one or t o, so that the ne(t instruction to e(ecute is pointed to by the se"uencer. >umps, and returns from Bumps, can also cause adBustments of hich PSSP is the active se"uencer. /n Bumps that succeed the address may or may not be incremented, depending on the type of Bump instruction, but the se"uencer ill al ays end up ith the Bump address. /f an instruction re"uires that a Bump be made, the se"uencer ill need the ne address. 5he ne address ill al ays be in the processing section of the PSSP ith the Bump instruction, or in the processing section of the adBacent PSSP immediately follo ing the one ith the Bump instruction. /n either case, the address ill be put onto the data bus, and the se"uencing PSSP ill accept it from that bus. 5he signals on the three se"uence control lines ill signal the se"uencer that it needs to accept a ne address from the data bus. /n Bumps here the ne address resides in the processing section of the PSSP adBacent to the PSSP ith the Bump instruction, the PSSP ith the address ill be partially activated by a bilateral control line.

-0

$ata can ta#e many forms ithin the system. /n a conventional system code and data are mi(ed and only distinguished from each other at the time of e(ecution by virtue of their position in the program code being e(ecuted. As the +P4 decodes each instruction, it automatically adBusts the program counter to point to the ne(t instruction. 5he compiler is relied upon to put code and data in the correct position so the +P4 doesnAt ma#e an error. A PSSP system ill also have the code and data mi(ed ithin secondary storage, and in the PSSPs, until it is loaded into a set of PSSPs for e(ecution. 5he &S ill ascertain hich is code and hich is data as each piece is chec#ed before loading. ,urthermore, since the code and data are #ept separate ithin the PSSPs, there is no chance for the se"uencer to ma#e an error in its se"uencing. /t relies on the code being e(ecuted to automatically set the three se"uence control lines, providing the necessary information to the se"uencer as to here the ne(t instruction for e(ecution is located. @hile addresses can be moved as data bet een the processing sections of various PSSPs, hether they ill be treated as an address or data depends on the actions of the control section of the active PSSP as it e(ecutes its opcode. >ust as in a conventional system, if the programmer fails to #eep trac# of hat each piece of data represents, the result can be fatal to the process. /t should be remembered that ithin a PSSP system, an address that attempts to point outside the isolated section of a local process ill cause a logical error that may cause the process to fail, but it ill not affect the rest of the system. 2.2 P++Ps &ith #edicated .unctions 5he original concept leading to the development of this system envisioned only one type of PSSP throughout the entire system. Numerous small, redundant units ere thought to be the ideal method ith hich to implement full decentrali6ation and integration of processing, control, memory, and /;& functions. Practical considerations led to an alternative design more in line ith real orld constraints. /t as much less costly to create PSSPs ith speciali6ed functions ithin the system. ,or each function limited to a speciali6ed PSSP, it as no longer necessary to put that function into the standard PSSP design. 5he most li#ely possibilities for speciali6ation ere functions that didnAt directly relate to program code for applicationsDcontrol functions. Se"uencing is a speciali6ed tas# relating to control ithin an apportioned section. 5he se"uencer activates each PSSP as it is needed, but the algorithm dictates hen each instruction should be e(ecuted. 5he programmer implemented the algorithm ith code, the compiler generated the binary code, and the se"uencer is the tool used to se"uence the code as dictated by the program. ?ach process needs a se"uencer, and the need for Bumps ith subse"uent return instructions means some sort of stac# is needed for se"uencing. 5his led to a se"uencing stac#. After much thought, it still seems the stac# can best be implemented ith hard are. A se"uencing stac# involves a limited number of PSSPs ithin every apportioned section handling the se"uencing for the process assigned to that section. 5he stac# has to be large enough to handle a reasonable number of Bumps and returns. A Bump ith a return re"uires the return address to be saved ithin the stac#. Saving the return address ill cause the stac# to adBust for ard by one PSSP. @hen the return instruction is e(ecuted, it ill cause se"uencing to return to the prior se"uencing PSSP here the address as #ept. !ead more about this in the section dealing ith the se"uencing stac#. A ell.made program seldom causes a problem, but e(actly ho large to ma#e the se"uencing stac# needs to be carefully considered. Some programming, such as the use of recursive functions, could re"uire very large stac#s, perhaps of an unreasonable si6e.

PSSP Systems -1
5 o other instructions, or functions, that are speciali6ed and limited ithin each process are >&!? and >/!?, the /;& gate#eeper instructions. ?ach uses t o PSSPs to atch for an /;& routine identification number to sho up on the /;& bus and initiate a Bump hen the right conditions are met. ?ach process needs a limited number of these instructions. 5herefore, it ma#es sense to put this function in a speciali6ed PSSP that can handle both instructions. 5hese three functions are the obvious ones, but there may be more, especially those instructions privileged for use by the operating system. 5he t o additional speciali6ed PSSPs mentioned above led to a design ith three different PSSPs, one for se"uencing, another for monitoring the /;& bus, and one for general.purpose algorithm e(ecution. 5he reali6ation that code in a permanent read.only form as needed for the boot process

lead to another type of PSSP. 5his one is Bust li#e the general.purpose type, but the code in the control section, and possibly the data in the processing section, must be in a read.only form. /t is li#ely that other speciali6ed PSSPs ill be developed as opportunities to reali6e cost or performance benefits arise. 5he concepts embodied in the design of PSSP systems are ne . As engineers and designers in the industry see# to adapt the concepts to their needs, ne possibilities ill emerge. /t is also very li#ely that PSSP designs ill ta#e advantage of evolving production capabilities. 2.2.1 +e/uencing P++Ps /n this section, differences bet een se"uencing PSSPs and standard PSSPs are discussed. $etails on the operation of se"uencing PSSPs and their use ithin the se"uencing stac# ill be given later, but a very brief description is given here. PSSPs designed for se"uencing only need be able to handle the three se"uencing instructions used for se"uencing stac# operations. &ne of these instructions, S?J, as briefly presented to the reader earlier. 5he other t o are SS?J and S?JS%. 5he SS?J is the standby mode of the S?J instruction. 5here can only be one active se"uencer ith the S?J instruction at any particular moment ithin a process. 5he active se"uencer is the one in the process of e(ecuting an instruction, or has the address of the ne(t instruction to e(ecute and is about to e(ecute it. =ost other se"uencing PSSPs in the stac# stand ready to se"uence hen certain conditions occur. @hile they ait, they are in standby mode ith the instruction SS?J. 5he S?JS% instructions are at the beginning and end of the se"uencing stac#. 5hey handle error situations presented by breaching the se"uencing stac#As upper and lo er bounds. 'ecause these PSSPs only handle the three se"uencing instructions, their design is greatly simplified compared to standard PSSPs. 5hey do not need all the built.in functionality of a standard PSSP, but they also have additional capabilities that are uni"ue to them. 5he processing section of a se"uencing PSSP needs to be able to increment its address by one or t o, accept data from the data bus, and put an address onto the primary address bus. 5he processing section needs to have a latch in each bit position to hold the address of the PSSP that is to be fully activated by the primary address bus. 8o ever, it does not need much in the ay of an A%4, nor does it need all the bus connections common to standard PSSPs. A standard PSSP can only increment the contents of its processing section by one, but se"uencing PSSPs need to be able to increment by t o. 5he increment function is handled internally by adding a one or t o to the contents of the processing section. 5his is handled ith a high signal entering the ' input of one of the t o lo est order bits of an A%4 unit modified to perform the A$$+ instruction. 5he A input to the A%4 only needs an e(ternal connection to the data bus for ne addresses that come to the se"uencer over that bus, and an internal connection that allo s the latch contents to be re.input.

-2
5he data flo controller only needs to be able to cause the data from the latches to be re.input or the output to go to the primary address bus. +hanges ithin the control section also simplify the design of se"uencing PSSPs. ,rom the global control lines, only the SJ=, +%L1, and +%L2 control lines need to be monitored. 5he local control lines of the au(iliary control bus that need to be monitored are the three se"uence control lines, SJ1, SJ2, and SJ-. 5hese lines are used to influence the behavior of the se"uencer by signaling ho large an increment should be performed, hether a Bump or return should be initiated, or hether the normal flo of se"uencing should be interrupted for an /;& routine. 5he se"uencer does not set the three local se"uencing control lines as standard PSSPs do hen e(ecuting an instruction. 5he se"uencer needs to monitor these lines, ho ever, and react to them accordingly. 5he inputs to the decoder from the opcode latches are present, but there are only three instructions that need to be decoded. 5here is no need to deal ith the flag status control lines. Se"uencing PSSPs only need t o bilateral control linesDone to each adBacent PSSP. 5hey are referred to differently because their functions are different from the bilateral control lines used by standard PSSPs. @ith standard PSSPs bilateral control lines are used for partial activation. @ith se"uencing PSSPs they are used to cause a bac# ard or for ard shift of hich PSSP is the active se"uencer ithin the se"uencing stac#. 5his means that they ill cause a se"uencing PSSP that is in standby mode to become fully self.activated. 5hese matters are not as complicated as they may sound

at this point ithin the boo#. ,ull details ill be given later in the section dealing ith the se"uencing stac#. @hile the se"uencing PSSPs have the same overall design as standard PSSPs, their functions are different enough to Bustify the design of a speciali6ed PSSP. 5he se"uencing stac#, implemented ith speciali6ed PSSPs, is mostly a hard are stac#, hich ma#es it very different from stac#s implemented ith soft are. ?very apportionable section of PSSPs has a se"uencing stac# and they have certain limitations that are the result of the stac# being hard are implemented ith speciali6ed PSSPs. 2.2.2 The I6, 9atekeeper &ne of the speciali6ed designs mentioned above is for a PSSP referred to as the /;& gate#eeper hich ill contain a >&!? or >/!? instruction. >&!? is used to output data to the /;& bus, and >/!? is used to ta#e data from it. 5hese instructions atch the /;& bus for an /;& routine identification number to sho up in conBunction ith a signal on the /&! control line indicating that a particular output routine has permission to put data onto the /;& bus. @hen these conditions are met, the PSSP ith the >/!? or >&!? instruction ill send a signal to the se"uencer to initiate a Bump to an /;& routine. &nly one process ill put data onto the /;& bus at any particular moment, but several processes may be receiving a copy of the data as input. @hile the >/!? instruction can atch for the id number of any output process, the >&!? instruction can only atch for the id number of the output process of hich it is a part. <enerally, only a fe /;& gate#eepers are needed ithin each process, but there are e(ceptions. 5he >/!? instruction can atch for different processes simply by changing the /&! numberDthe /;& routine identification number in its processing section. 5herefore, there only needs to be one pair of PSSPs ith the >/!? instruction in each process. 5he >&!? instruction is different, in that there needs to be a pair of PSSPs assigned for each type of output a process has. 5he &S ill assign each output an /&! number. ,or instance, suppose a process has an output need for a printer and secondary storage. /t

PSSP Systems -ill be given an output routine for each of these needs and an /&! number to go ith each one. 5herefore, the number of /;& gate#eepers needed by each process is e"ual to the number of output needs, plus one for the input. ?ach gate#eeper consists of t o PSSPs, but this does not have to be so. As it ill be seen in the section that deals ith the /;&, hat is actually needed are one full PSSP and one additional processing section to hold the address of the /;& routine. A PSSP speciali6ed for this function ill be designed to have t o processing sections. 5he second control section is not needed. PSSPs designed to handle only the /;& gate#eeper function ithin an apportioned section must be able to perform a comparison of the data on the /;& bus against hat is in its processing section. /f the t o operands are e"ual, the PSSP must be able to set the se"uence control lines to the correct state and activate the second processing section to release its data onto the data bus at the proper moment. 5he se"uencer ill then ta#e the data as an address and begin se"uencing at that address. 5he address ill be the start of an /;& routine. /n addition to being able to compare the A and ' inputs of the A%4, these PSSPs need to be able to ait one or t o cloc# cycles hile the se"uencer finishes its current instruction. 5his ait is necessary because gate#eeper PSSPs, li#e se"uencers, are self.activating and ill find the Bump conditions met hile the se"uencer is e(ecuting another instruction. 5o avoid conflict ithin the process they must ait until the se"uencer is ready to respond to the Bump to the /;& routine. A PSSP, used as /;& gate#eeper for output, needs to be able to react to the /&% control line used by the process to enable and disable it. /t also needs to have the processing section be read.only during normal program e(ecution. /t is important that only the &S have the ability to change its contents. 5his is done for security reasons that are discussed in the section on the /;& system. Aside from these special needs, the speciali6ed PSSPs that function as /;& gate#eepers are much simpler in design than standard PSSPs. 2.2.3 P++Ps 'or Booting

5he PSSPs used for booting are Bust li#e standard and se"uencing PSSPs. 8o ever, the code, the data, or both, is unchangeable, even hen po er is lost. A conventional system ill have a '/&S !&= chip that holds the code and data needed to start the system and begin loading the &S. A PSSP system also needs the same basic service performed hen the system boots. 4nli#e a conventional system, ho ever, a PSSP system does not have a set of code, intermi(ed ith data, to be implemented by a +P4. /nstead, the full integration of all functions ithin the PSSPs re"uires that each PSSP have code and data ithin it and that it be activated by a se"uencer in the proper order. 5his ill re"uire that some PSSPs have data in their processing section that is read.only, hile other PSSPs need the fle(ibility of being able to rite data to the processing section. A similar situation needs to e(ist ith the control section of the PSSPs used for the initial boot. Some code in the control sections may need to change as the booting occurs. ,or instance, the se"uencing PSSPs need to be able to change state from the S?J instruction to the SS?J instruction, and bac#, as the se"uence of instructions is e(ecuted. /t is also necessary to be able to enable and disable the >&!? instruction as needed. All the resources needed for the initial boot process must be available ithin the apportioned section in hich the boot process resides. /t is possible that once the design of the boot code is fully tested and ma(imi6ed, it ill be implemented ith hard are. 5his could be ta#en to the e(treme of all,

-*
or portions, of the needed code being implemented, and replaced ith dedicated logic circuits. 5he need for se"uencing ill still e(ist, but this implementation promises the greatest possible efficiency. 2.2.! ,ther Possi ilities 5he desire to achieve cost reductions ithin the design of a PSSP system ill drive the choice to speciali6e the designs of PSSPs used ithin the system for various tas#s. Another area of potential speciali6ation is ithin the PSSPs used by the operating system. @ithin any system, the &S establishes itself first. As a result, the &S al ays resides in the same place, has the same functions, and in most cases, assigns the same tas#s to the same PSSPs. @hile this speciali6ation should not be ta#en too far, there is room for cost efficiency in such efforts. Several instructions are limited to &S use only, and ill never be used by any other process. /t is not unreasonable to ma#e speciali6ed PSSPs to handle Bust these instructions, and then dedicate those PSSPs to the &S as part of the boot process. 5his ould eliminate the need to design these instructions into the rest of the PSSPs in the system. 5here is a dra bac# to this approach, ho ever. &ne of the failings in current conventional systems is that certain locations in memory are dedicated to particular functions. 5his leaves access to these functions vulnerable to individuals ho might ish to influence the system, or are clumsy ith their code. 5his is less li#ely ithin a PSSP system because of the isolation afforded to each process resident ithin the system, but there is still a need for the high degree of stability provided a system hen outside forces cannot unduly influence its processes. /t may be that the isolation of the &S processes is sufficient to provide needed system security and stability, but there needs to be a balance bet een such concerns and the desire to achieve cost reductions. 5here should also be some redundancy or bac#up resources built into a design to avoid situations in hich the entire system becomes non.functional because one or more PSSPs fail. @hen systems designed around the use of PSSPs become commonplace, there are li#ely to be many innovations in PSSP design. 5here is vast potential ithin this design that ill only become apparent as professionals ta#e the time and effort to manipulate it to fit their needs. ,ull integration of computing elements into units that are distributed evenly throughout an entire system opens up ne territory for innovative design in computer systems, as ell as systems that use computers as the controlling element in their design. 5he only other possibility that ill be discussed here is one that involves the use of this type of system for operations on large arrays, or matrices, of data. 'ecause each PSSP holds its data, and can operate on this data, there is tremendous potential for parallel processing ithin an individual process. /f certain modifications to the design of the system are made it is possible to activate a group of PSSPs ithin a process simultaneously, allo ing them to perform their functions at the same time. 5here are

restrictions on hat functions they can perform because they cannot all use the same bus resources simultaneously, but many functions can be performed ithout bus resource conflicts occurring. Simultaneous e(ecution of processes already e(ist ithin the system, and some modifications to the addressing bus structures ould enable groups of PSSPs ith contiguous addresses ithin the same process to be activated simultaneously as a group. +urrently, the t o address buses need to be constructed ith enough bit lines to be able to address any PSSP ithin the system, or address the set of PSSPs in the ma(imum possible si6e of an apportioned section. ,or e(ample, if a system as designed to allo for a ma(imum grouping of

PSSP Systems -2
apportionable sections into one apportioned section of 6* =egs of PSSPs, then 26 address lines are needed. %et it be assumed that 26 address lines are used to construct the primary address bus, and that this bus is fully available throughout the system. !ecall also that the primary address bus is used to fully activate the PSSPs, normally one at a time. /f a 16.=eg section of PSSPs is then apportioned from the rest of the system, there ill be t o address lines not needed for addressing of the PSSPs ithin the apportioned section. 5hese unused address linesD ith changes or additions to the address decoding circuitsDcan provide an alternate mode of addressing. 5his alternate mode of addressing can provide a means of activating a group of PSSPs simultaneously. 5here are other issues involved in implementing this idea, and it is not as simple as Bust described, but the potential is there to effect simultaneous processing of multiple PSSPs.

-)

"

T#e Set of Operations

very computer system is a combination of hard are and soft are. 5he hard are design provides the system ith its potential, and the soft are, designed for use on that hard are, becomes the manifestation of that potential. 5he set of instructions is the bridge bet een the t o. 5he instruction set, designed to ma(imi6e the potential inherent in a particular design, is used to turn the potential into a reality. So it is for this system, also. As ill be sho n in the rest of the boo#, the system design presented ithin this te(t can provide a system that is able to run multiple processes simultaneously. 8o many processes the system is able to handle becomes a function of ho many apportionable sections are available, and ho many processes can be handled by the /;& system before it slo s do n from overloading. 5his is very different from a conventional system, here the primary limiting factor is the speed and capacity of the +P4. /n a conventional system, the primary consideration is al ays ho to get more speed to achieve a greater throughput ithin the system. /n a PSSP based system, the considerations ill be the amount of apportionable PSSP space, and hether the /;& system can handle more traffic. Since speed is not the primary consideration in this type of system, less emphasis is put on the efficiency of the instruction set. 8o ever, cost issues still re"uire a minimal number of instructions, so that the number of bits ithin the control section and other circuitry is #ept to a minimum. 5his ould seem to indicate that the instruction set be !/S+ in nature, but the reason for it is not the same as in a machine built around !/S+ architecture. 8ere, a reduced instruction set is used to #eep costs do n, hile !/S+ architecture as implemented to increase the speed of a system. 5he instructions included here are more than the minimum necessary for programming the system and applications that ill run on it. No claim is made as to hether a particular opcode should or should not be in this set, but it should become obvious that several of them could be eliminated ithout harm. %i#e ise, it might be beneficial to add other instructions to provide enhancements in design utili6ation. 5his instruction set is Bust one of several possible sets and seemed sufficient hen it as created. 5he number of instructions influences the number of bits needed to implement them, the comple(ity of the decoding and A%4 circuits, and the cost of the system.

/t cannot be over.stressed that the opcodes are a reflection of the capabilities built into the hard are. 5hese opcodes are a reflection of the design used for the PSSPs and the rest of the system. Slight alterations in PSSP design or other aspects of the system can result in a different set of opcodes. /n particular, the opcodes dealing ith local or global control are intimately connected to hard are design.

$
-9

Instruction +et
PSSP Systems -3
5here is no addressing fle(ibility ithin the set of opcodes. 5here is only one ay each opcode can be implemented. 5he t o addressing modes, direct and indirect, are not used selectively, but are an inherent property of the system design. 5hese t o addressing modes should not be interpreted as meaning the same things as they do in a conventional system. $irect addressing refers to an operand that is in the processing section of the fully activated PSSP, hile indirect addressing refers to all situations here an address is used to move an operand. 5he lac# of other addressing modes may at first seem constricting hen trying to design soft are. 8o ever, once a programmer becomes accustomed to the situation, it actually becomes easier to implement an algorithm because the number of possible paths to the goal is greatly reduced, and the correct path stands out more clearly. 5he result is simplicity in the program code. 5he direct address mode is used henever possible. /t is used for all instructions having one operand, e(cept the three used for moving data and code. /ndirect addressing is used for the move instructions and instructions that have t o operands. @hen a second operand is needed for an instruction, it ill be indirectly addressed, ith the address being in one of the t o adBacent PSSPs.

*0
5his inherent restriction on addressing saves bits in the development of opcodes and greatly reduces comple(ity. /t is also a direct result of the system design. 5here are five instruction formats for the set of instructions. ?ach instruction has a specific format. 5he first three formats deal ith instructions that have 6ero or one operand. An instruction ith no operand uses format ,1. 5he opcode is put in the control section and it ill not be affected by hatever is in the processing section. /nstructions ith only one operand, e(cluding the ones used for moving data or code, #eep the operand in the processing section of the PSSP using it for instruction e(ecution. 5he operand is put there before the instruction is e(ecuted. 5hese instructions use format ,2. 5here are t o different formats for instructions ith one operand that use an address to deal ith the operandDthe instructions that move data and code. 5hese instructions use format ,- and ,*. ,ormat ,- has the source address in the PSSP ith the opcode. 5he operand destination ill be the processing section of the PSSP follo ing the one ith the opcode. ,ormat ,* has the destination address for the operand in the processing section of the PSSP holding the opcode, and the operand source is the processing section of the preceding PSSP. /nstructions that have t o operands use format ,2 and ill have one operand in the processing section of the PSSP ith the opcode. 5he address of the other operand is in the processing section of the PSSP follo ing the PSSP ith the opcode. 5here is a particularly interesting aspect regarding the use of operands ithin the code in this type of system. A close study of the coding e(amples that follo ill sho that the operands, or the addresses referring to them, are in the proper place hen the instructions are e(ecuted. 'ut loo# closely at hen these operands are put here they are needed. @hen process e(ecution begins, many processing sections contain null or non.relevant data. ,ollo ing the code closely ill reveal that data, an operand for e(ample, ill be operated on in one instruction, and then a copy is moved for ard to

here it ill be needed ne(t. 5here is still a place here the data is given e(clusive space, but ithin the section of PSSPs used for the code, the same variable may have several different values in various different processing sections. /n a sense, the processing sections of the PSSPs holding the code act li#e a large linear array of registers, ith the values in the registers changing as the instructions are e(ecuted. 'ecause of the large number of these registers, the values stored in them are often left untouched for e(tended periods. 5here is still a need to move data around, but it is moved to here it is needed ne(t instead of being shuffled bac# and forth bet een memory and registers, as in a conventional system. &f the thirty.four possible opcodes, three deal ith se"uencing. 5hey are only used in PSSPs designed for se"uencing, and their use is automatic from the programmersA point of vie . &f the remaining thirty.one opcodes, nine are for arithmetic and logical operations. @hile their use is a little different because of the systemAs design, they still have the same function as in a conventional system. Another ten opcodes deal ith program flo , and these also have the same functions as in a conventional system, but their operation is different. 5hat leaves t elve opcodes that have not been mentioned yet. 5hese t elve deal ith various other functions, such as moving data, /;&, local control, and global control. =ost are difficult to classify, as they deal ith multiple functions. ,or e(ample, the =&7+ instruction is used to move code into the control section of a PSSP, but it is also used to give the &S sole control over the movement of code ithin the system. Another e(ample is the instructions used for /;&. 5hey are used for /;&, the movement of data, and also have control functions.

PSSP Systems *1
An application programmer ill never use many of the opcodes and only systemsA programmers ill use several others. /nstructions dealing ith global control and the movement of code are reserved for the &S, and ill only be used by someone programming the system. 5he &S, in setting up /;& routines ithin each process, uses the t o /;& gate#eeper instructions and the three instructions for input and output. ,inally, the three se"uencing instructions are also not used by programmers. 5he &S sets up these three instructions in the se"uencing PSSPs during the loading process. &f the thirty.four instructions included here, the systemsA programmer and the &S reserve t elve of them for use. After a programmer becomes comfortable using this type of system, he or she ill find that their ideas on ho to program, or implement algorithms ill change. 5he reali6ation that multiple processes can run independently and simultaneously ithin the system ill ultimately lead to different soft are design techni"ues. A less linear approach to programming ill become commonplace as large tas#s are bro#en into smaller processes that can be run concurrently ithin the system hile communicating ith each other via the /;& bus. 3.1 The :o%ement o' #ata 5here are five instructions used for moving data ithin the system. &ne of those is actually used by the operating system for moving code. Another t o are used for the movement of data to and from the /;& bus. 5hat leaves t o instructions dealing specifically ith the movement of data ithin a process. @ith these t o instructions, the data is either moved from some here to the processing section of the ne(t PSSP, or it is moved from the processing section of the previous PSSP to some place else. 5here are no other choices for the programmer. 5he lac# of normal registers ithin this system and the integration of memory, processing, and the /;& re"uires the use of a different point of vie by the programmer ishing to ma#e efficient use of these t o instructions. 5he lac# of other addressing modes presents no real problems. 5he simplicity of having only t o methods of moving data e(tends itself to the code used to implement an algorithm. 5he efficient use of these t o instructions ill minimi6e the number of instructions used and still provide the fle(ibility needed by programmers. Programmers ine(perienced ith programming this type of system may find the instructions difficult and clumsy to use during their first attempts, but they ill rapidly become accustomed to the different rhythm, and ill come to appreciate the simplicity these t o instructions engender ithin the code. 5he timing of data movement and the placement of

instructions ithin the code become an important issue as the programmer becomes s#illed in the use of these t o instructions. $isplacement addressing is dealt ith by ta#ing a fe e(tra instructions to modify the address as desired before using it. /t may seem to slo everything do n, but this is not a problem. Leep in mind that the processes ill be running continuously and concurrently ithin the system. As ne programming techni"ues are developed to ma(imi6e utili6ation of this type of system the applications designed for it ill be split into multiple process that ill also run concurrently ithin the system. 3.1.1 :,V* and :,VT Instructions 5hese are the only t o instructions available for the movement of data from place to place ithin a process. =&7+ is available for moving code as data bet een the &S and an apportioned section, but

*2
that instruction is dealt ith separately, immediately follo ing these t o instructions. /NP and &45 are available for moving data bet een processes via the /;& bus, and they ill be presented follo ing the =&7+ instruction. %et me state this in another ay to ma#e it clear for the reader. 5here is one instruction for moving code, there are t o instructions for moving data bet een isolated processes, and there are t o instructions for moving data ithin a process. 5he t o instructions for moving data ithin a process are =&78 and =&75. =&78 is used for moving data from the processing section of some other PSSP to the processing section of the PSSP immediately follo ing the PSSP ith the =&78 instruction. 5he =&75 instruction is almost the reverse of that. /t moves data from the processing section of the PSSP immediately preceding the PSSP ith the =&75 instruction to the processing section of some other PSSP. 'oth instructions have an address in the processing section of the PSSP ith the instruction, and they both use t o cloc# cycles to complete. 5he =&78 instruction uses a bilateral control line to activate the processing section of the follo ing PSSP to receive data from the data bus. 5he address in the processing section of the PSSP ith the =&78 opcode is put onto the secondary address bus, and the !;@ control line carries the signal causing the PSSP addressed by the secondary address bus to release its data onto the data bus. 5his data is then accepted into the processing section of the PSSP follo ing the one ith the =&78 opcode. 5his destination processing section is partially activated by the A,$@ bilateral control line to receive the data from the data bus. 5he =&78 instruction uses the ,- format. 5he =&75 instruction moves data from the processing section of the PSSP that immediately precedes the PSSP ith the instruction, to the processing section of some other PSSP. 5he instruction ill partially activate the destination ith the secondary address bus and !;@ control line. 5he operand in the processing section of the previous PSSP is released onto the data bus by a signal on the APA! bilateral control line, hich comes from the PSSP ith the =&75 instruction. 5he =&75 instruction uses the ,* instruction format.
The .3 .ormat &ith the :,V* Instruction $##57++ P5,C7++I;9 +7CTI,; C,;T5," +7CTI,; n 5he address of the operand =&78 opcode n M 1 5he operand is put here The .! .ormat &ith the :,VT instruction $##57++ P5,C7++I;9 C,;T5," C,;T5," +7CTI,; n : 1 5he operand is here Another opcode n 5he address of here to put the operand =&75 opcode

Notice that the =&78 and =&75 opcodes are in the control section of address n, and that address nM1 or n.1 has some other opcode. ?very PSSP ithin an apportioned section should have an opcode, even if that instruction is only the N&P instruction. ?ach instruction ill affect the three se"uence control lines that provide guidance to the se"uencer as to hich instruction should be ne(t. 5he compiler or &S ill insure that there is an opcode for the control section of every PSSP hen constructing the code. /n the case of the =&78 and =&75 instructions, the opcode at address nM1 or n.1 ill most li#ely be some arithmetic or logical operation. 4sually, a variable is moved to a location

PSSP Systems *ith a =&78 instruction so that the variable can be manipulated for some purpose. 5he instruction doing the manipulating ill be in the control section of the PSSP immediately follo ing the =&78 instruction. 5he instruction follo ing the manipulating instruction ill often be =&75. 5his pattern is very common in the codeDfirst a =&78 instruction, then arithmetic or logical instruction, and then the =&75 instruction. =ove the data here, operate on it, and then move it some here else. /n many ays, code e(amples can sho ho instructions are used more clearly than ords. @ith that in mind, e(amples ill be given for many of the instructions as they are presented. A short e(planation may be given before each e(ample to help the reader understand the intent of the code. ?(ample0 At address 0900 is a data obBect, the number 93, that e ant to add to another data obBect, the number 2, at address 1000. 5hey ill be added, and the result ill be put bac# at address 1000.
$##57++ P5,C7++I;9 +7CTI,; C,;T5," +7CTI,; 1A00 0900 =&781A01 ..... A$$+ 1A02 1000 =&75

5he processing section of 1A00 holds the address of the data to bring to the processing section of 1A01. After the =&78 instruction is e(ecuted, the processing section of 1A01 ill contain the first operandD93. 5he ne(t instruction, A$$+, ill bring in the second operand from address 1000 and add it to the contents of its o n processing section that contained 93 prior to e(ecution of the A$$+ instruction. After the A$$+ instruction is e(ecuted, that processing section ill contain the resultD 9?. 5he ne(t instruction puts the result bac# to the location from hich the second operand of the A$$+ instruction as brought. After completion of the =&75 instruction, addresses 1000 and 1A01 ill both have 9? in their processing section. 4se the follo ing diagram to compare instruction formats for these three instructions ith ho the code is arranged. 5he =&78 instruction uses the ,- format, the A$$+ instruction uses the ,2 format, and the =&75 instruction uses the ,* format. Notice ho all three of the instructions end up actually overlapping each other. ,or e(ample, the =&78 instruction uses the processing sections of addresses 1A00 and 1A01, the A$$+ instruction uses the processing sections of addresses 1A01 and 1A02, and the =&75 instruction uses the same processing sections as the A$$+ instruction. &f course, the code doesnAt al ays mesh as elegantly as this e(ample, but it often does. &nce programmers become accustomed to programming ithin a PSSP system, they ill find it no more difficult than programming in a conventional system, and as ith most programming languages, there is elegance to good code. 5he lac# of many different addressing options ill cause no difficulties, but ill lead to a more uniform and consistent method of accomplishing certain tas#s.

**
3.1.2 :,VC Instruction =uch has already been said about =&7+, the instruction for moving code ithin the system. &nly the &S is able to use the =&7+ instruction. 5his is done to increase system security and stability. +ode and data are #ept separate ithin the system, and by restricting movement of code to the &S, that separation is maintained. 5he value of #eeping the code and data separate cannot be overstated. =any people believe that the =&7+ instruction does not belong in a section dealing ith the movement of data. 5he instruction is used for moving code instead of data, and there are aspects to the instruction that ma#e it unli#e the other t o move instructions. A good argument can be made against it being included here, but to do so leaves a person trying to understand the system and its differences ith too many "uestions. 5he instruction is used to move data from the processing section of one PSSP to the control section of another PSSP. 4ntil code has been put into the control section of a PSSP, it is Bust data, and hile it is Bust data, it cannot be e(ecuted. &nce it has been deposited into the control section of a PSSP, it

becomes e(ecutable code. Since the &S is the only process to ma#e use of the instruction the potential for corruption of code ithin the system is eliminated.

PSSP Systems *2
+onfusion over hat is, or is not code, is very unli#ely. Part of the process of loading code is to perform several chec#s on every piece of code put into the control sections. +hec#s are made to ensure that it is a valid opcode, and not one of the restricted opcodes going into an unauthori6ed process. ,urthermore, the pattern of code and data stored on the secondary storage device is different from the program code found in a traditional system. 5raditional code is stored as a series of bytes ithout a regular, repeating pattern. &n a PSSP system, a repeating pattern is easily detected. ?very PSSP has data and an opcode that must be put into the PSSP before the process is e(ecuted. 5here are no blan# spaces left ithin the PSSPs after they are loaded. Processing sections that do not need a specific piece of data ill at least be filled ith null data. +ontrol sections al ays have an opcode, even if it is only the N&P instruction. Secondary storage ill reflect this pattern of data, code, data, and code in an alternating series of data segments of consistent si6e. 5herefore, it becomes easy to discern hich is data, and hich is code. 5hese chec#s are made by the &S to ensure system security and stability. /f they ere not made, ho serious could the result beE 5here are t o different chec#s made that are of concern. &ne is to differentiate code from data, to ma#e sure that only valid opcodes are deposited into the control sections, and the other is for restricted opcodes to hich a non.system process should not have access. 5he chec# for valid opcodes deals ith the stability of the system and the processes ithin the system. 5he chec#s are easy to accomplish by comparing the data to a list that represents all valid and restricted opcodes. /f an invalid opcode gets into the control section of a PSSP, the process ill simply fail, unless the process happens to be a system process. ,ailure may be a slo degradation of the ability of the process to carry out its function, or it may be an abrupt failure ith dramatic affects. /f the failure is ithin a non.system process, the effects ill be limited to the process. /f it is a system process, the result could be complete system failure. /f a non.system process gets a valid opcode, but the code is one of the opcodes restricted for use by the &S, the entire system becomes vulnerable to the actions of that process. 5here are four restricted opcodes, and all of them are used to handle critical system functions. =isappropriation of the /;& bus, uncontrolled apportioning of PSSP sections, and unrestricted access to code and control sections are all possibilities hen a process other than the &S gets access to restricted opcodes. /n a conventional system, the +P4 chec#s for restricted opcodes before they are e(ecuted. 8ere, the code is chec#ed before it is allo ed into a control section. A conventional +P4, discovering a restricted or false, opcode ill generate a fault and hopefully conclude the process safely. /n a PSSP system, the process never gets started. 5he loading process ill abort as the &S tries to load the process into an apportioned section and discovers the bad code. 5he loading ill be terminated and an appropriate error message generated and sent to the screen via the /;& bus. 5he &S chec#s the code before it uses the =&7+ instruction for moving it to an apportioned section. 5he =&7+ instruction or#s very much li#e the =&75 instruction, e(cept that the data is routed onto the au(iliary data;control bus, instead of the data bus. !ecall that part of the processing section of a PSSP is the data flo controller that accepts outputs from all the bit data latches in the processing section and routes those outputs to the correct place, depending on hich opcode is in the control section. 5he =&7+ instruction causes those bits to be output onto the au(iliary data;control bus. 5he processing section of the PSSP holding the =&7+ instruction holds the destination address for the data that ill become code. 5his address ill be put onto the secondary address bus to cause partial activation of the addressed PSSP. /n addition to these actions, the =&7+ opcode ill cause an appropriate signal to be put onto the +@? global control line.

*6
5he +@? control line ill enable a PSSP that is receiving partial activation by the secondary address bus to have its code section enabled to receive bits into the opcode latches from the au(iliary data;control bus. 5he +@? control line is part of the global control bus, and its signal is an integral

part of the =&7+ instruction. 5he signal is automatically generated hen the instruction is e(ecuted. 5he =&7+ instruction is used to move data located ithin a buffer of the &S process to a ne ly apportioned section of PSSPs some here ithin the system. 5he loading of code into an apportioned section of PSSPs is one of the processes used by the &S for controlling the system. /t is li#ely there ill only be a fe PSSPs ith this opcode. 5heir use ill be one event in a chain of events that gets a process up and running. @hile this chain of events ill be discussed in detail in the section dealing ith the &S, a brief description is given here. Assuming that the &S is up and running, it ill get a message from another process that a particular process should be installed ithin the system. 5he &S then sends a message, via the /;& bus, to the process controlling the secondary storage device, that a process is sought by the system. 5he secondary storage device locates it and retrieves a header from the file holding the process. /t sends this bac# to the &S via the /;& system. 5he &S ta#es this information and ascertains hether it has sufficient resources for the process. /f it does, it assigns an apportioned section to the process. 5hen it starts or#ing ith the process controlling the secondary storage device to load the code into a temporary buffer ithin the &S space. /t distinguishes code from data and ma#es chec#s on the code. /t also chec#s the /;& needs of the process and inserts the necessary /;& routines. 5hen, #no ing it is safe to load the code, it ill use the =&7+ instruction to move the code to the PSSPs of the apportioned section. 5here may be some reconfiguring of the apportioned buses needed to reach the apportioned section, but it is only temporary. 5his process ill continue until the code and data for the ne process are fully loaded in their apportioned space. 5hen the &S isolates that process ithin its section of PSSPs, its apportioned section, and finally releases that process to begin se"uencing on its o n. ?(ample0 Address 0900 is the starting address of the buffer holding the code and data for a process to be loaded into an apportioned section. 5he &S has determined that every odd.numbered address in the buffer has valid code, and that every even address has data. ?very se"uential pair of PSSPs in the buffer, starting ith the first and second PSSPs, contains the code and data for a PSSP in the apportioned section. 5he first address to be loaded ithin the apportioned section is ,,00.
P5,C7++I;9 $##57++ C,;T5," +7CTI,; +7CTI,; 0900 $A5A N&P 0901 +&$? N&P ... ... ... A000 0900 =&78 A001 .... N&P A002 ,,00 =&75 A00- 0901 =&78 A00* .... N&P A002 ,,00 =&7+
;o& a check 'or the end o' the u''er is made) and i' not the end o' the u''er) update the addresses and go ack to the eginning o' the loop.

PSSP Systems *)
.. .. .. ,,&& .... ....
7ach time) through the loop) the data is rought to address $((1) and the code is rought to address $((!. $'ter the loop is executed the 'irst time) address ..(( &ill ha%e data in the processing section) and code in the control section. ;ote that the code is mo%ed into the control section using the :,VC instruction) &hile the data is mo%ed into the processing section using a :,VT instruction.

3.1.3 I;P and ,8T Instructions %i#e the =&7+ instruction, many people ill feel that this is not the appropriate place for input and output instructions. 5hey are here because they deal ith the movement of data, specifically the movement of data into and out of a process, or onto and off the /;& bus. /n a PSSP system, the only ay for data to move bet een isolated processes is via the /;& bus. 5o move data to another process using the /;& bus re"uires that the data be put on the bus and then ta#en off the bus. 5hat is hat these

t o instructions are used forH it is their only purpose. 5he >&!? and >/!? instructions, the /;& gate#eeper instructions, ill be covered later in this section. No ports or addresses are directly involved in the use of these instructions. 5he only operand is the data put onto the bus, or the data copied off the bus. 5his operand resides in the processing section of the PSSP ith the &45 opcode before its e(ecution, and ill reside in the processing section of the PSSP ith the /NP opcode after that instruction is e(ecuted. Since there is no address involved, one of these instructions is needed for each unit of data that is output to, or copied from, the /;& bus in each /;& routine. ,or e(ample, if four units of data are to be copied from the /;& bus then there must be four /NP instructions in the input routine. ?ach /NP instruction can only be used one time for each run through the input routine. Notice that / specifically refer to data coming from the /;& bus as Fcopied.G 5his reflects the true state of the situation. 4nli#e a traditional system, here an interrupt may be used to gather a specific piece of data from a device, a PSSP system re"uires that data going onto the /;& bus be broadcast to the entire system. Any process may be atching for that data to sho up. Any process may receive it into a PSSP ith the /NP instruction. /f a process periodically re"uires four units of data from a mouse status routine, then some here in that process there ill be a routine ith four /NP instructions meant to ta#e this data from the /;& bus hen it is available. %i#e ise, if a process is to broadcast four units of data onto the /;& bus, it ill have a routine ith a series of four &45 instructions to put data onto the /;& bus. 5hese t o instructions are al ays used in an /;& routine. 'oth the /NP and &45 instructions are restricted to routines built and inserted by the &S. /f they are detected in program code during the loading process, the loading process ill be aborted. Neither of these opcodes are instructions restricted for use by the &S, but only the &S is able to insert them into a process. 5he &S actually constructs, or controls the construction of, all /;& routines needed by processes ithin the system. 5here is a special aspect to the &45 instruction the reader should be a are of. /t must be enabled in order for the instruction to function. As stated earlier, the &S must control the output of data onto the /;& bus for security reasons. /t is imperative that no process be able to output onto the /;& bus ithout first getting permission from the &S. 5hat is the purpose of the >&!? instruction, but the >&!? instruction is not the only instruction that can cause a Bump to the output routine. Any Bump instruction ith the address of the output routine in its processing section can cause the Bump. 5o insure that the routine as entered only via the >&!? instruction, the &45 instructions are disabled

*9
unless they receive an enabling signal from the >&!? instruction. 5his signal comes via the !;@ control line. 5he first process to e(ist in a PSSP system is the '/&S routine used to begin the boot process. 5he '/&S contains input and output routines for a secondary storage device that is part of the system. 5hese routines are part of the &S. Starting ith these t o /;& processes, the &S ill build a data structure that #eeps information and code about each /;& process resident ithin the system. ?ach ne process ill have its outputs analy6ed, and possibly modified, to fit the needs of the system. ,or every output routine, there is a corresponding input routine. 5he &S #eeps all this data and then inserts the necessary routines into each process as the process is loaded. 5his is here the /NP and &45 instructions originate, not ithin the program code built by the programmer. 5he programmer specifies the /;& needs of the process being designed, and the &S analy6es those needs, and then inserts the code into the process as the process is loaded into an apportioned section. 5his is very different from ho the /;& is handled in a conventional system. /n this system, everything is #no n and planned, and any deviation from the plan is considered a threat to the system. 5he &S has total authority in regards to use of the /;& bus. ?very process must see# /;& services from the &S, and then ait for permission to use the /;& bus hen it ishes to output data onto the bus. An e(ample of these t o instructions ill not be presented here. /nstead, they ill be used in the e(ample for use of the >&!? and >/!? instructions. 5he /NP and &45 instructions are very simple and easy to use. 8o ever, the /;& routines, in particular the output routines, are not so simple. ,or this

reason, e(amples ill be deferred until an e(planation of the se"uencing stac# and the t o /;& gate#eeper instructions are given to the reader. 3.2 $rithmetic and "ogic ,perations 5he arithmetic and logic operations used in this system ill be familiar to most readers. 5heir use ithin this system is different, ho ever, so details ill be presented here, along ith an e(ample of their use. 5 o formats are used for these instructions. ,ormat ,2 is used for operations involving only one operand, and format ,2 is used for operations needing t o operands. /nstructions ith one operand ill al ays have the operand in the processing section of the PSSP e(ecuting the instruction before the instruction is e(ecuted. /nstructions needing t o operands ill al ays have one operand in the processing section. 5he other operand needs to be brought into the ' input of the A%4 via the data bus. 5he operand is located at the address that is in the processing section of the PSSP that follo s the PSSP ith the instruction. All of these instructions, e(cept the compare operation, create a result that is left in the processing section of the PSSP that e(ecuted the instruction. 5herefore, the operand in the PSSP ith the opcode ill be lost as the instruction is e(ecuted. 5he compare operation ill only set the e"ual flag control line and the original operand ill remain in the processing section after the operation is finished. 5he arithmetic and logical instructions cause the flag control lines to reflect the results of the operation. &nce set, the flag control lines remain set until affected by another operation. Another arithmetic or logical operation ill cause them to be set to reflect the results of that operation. A Bump instruction ill cause a reset of the particular line that is tested.

PSSP Systems *3
3.2.1 ,ne ,perand Instructions /nstructions re"uiring only one operand include several that handle logical operations, and a fe others that include the control functions. 5he control functions are used to set a control line high or lo , and they ill be covered in the section dealing ith local and global control instructions. 5he logical operations re"uiring one operand include /N+, N&5, S%, and S!. 5he increment instruction is an increment of one, hile the t o shift instructions only shift one place to the right or left. 5hese instructions use format ,2. 5hey only re"uire the use of one PSSP. 5he operand is in the processing section of the PSSP ith the opcode, and it must be there before the instruction is e(ecuted. /t is very common for one of these instructions to be nested bet een the t o move instructions. 3.2.2 T&o ,perand Instructions 5he t o operand instructions include A$$+, AN$, &!, K&!, and +=P. All of these instructions re"uire one operand to be in the processing section before instruction e(ecution. 5he A$$+ instruction is the only arithmetic operation and it handles addition ith a carry. 5he AN$, K&!, and &! instructions all perform as in a conventional system. K&! and +=P perform the same operation, but +=P does not create a result or change the operand in the processing section. /t is used to compare t o operands for e"uality, not to compare one operand to 6ero. 5here is no need to give e(amples for each of these instructions, as most readers are familiar ith them. 5he most interesting point about their use is ho data is moved in relation to their use, and ho the flag lines are set and then used for Bumps. See the bubble sort e(ample at the end of this section for e(amples of such situations. ?(ample0 A logical operation ith one operand is presented here ith an arithmetic operation re"uiring t o operands. 5he results ill not be used for Bump decisions. An e(ample of that ill be presented later ith the Bump instructions.
$##57++ P5,C7++I;9 +7CTI,; C,;T5," +7CTI,; 0900 0010 N&P 0901 000, N&P 0902 0001 N&P A000 0900 =&78 A001 .... N&5 A002 0900 =&75 A00- 0901 =&78

A00* .... A$$+ A00* 0902 =&75

20
As seen in the e(ample, the logical and arithmetic operations are simple. Notice the use of the move instructions. /n an actual program, the movement of data is the most often performed operation, Bust as in conventional systems. 3.3 Control ,perations +ontrol operations provide the means of controlling the system and the processes running ithin it. <lobal control operations deal ith the entire system and are e(ecuted by the operating system. 5here are also local control operations, hich deal ith control in a local process isolated in an apportioned section. A process ill al ays handle its o n local control operations hile the &S handles all global control operations. Se"uencing operations are mostly local, but control of the se"uence master control line is a global control operation and handled by the &S. Se"uencing instructions, along ith details about the se"uencing stac#, ill be presented after global control instructions. +ontrol instructions are presented before Bump instructions because doing so ill help the reader understand ho all the Bump instructions are accomplished in this type of system. 'efore control instructions are e(plained, it is a good idea to again mention several aspects of a PSSP system. /n a PSSP system, the &S rigidly controls the use of the /;& bus, but it does not use a system of interrupts. /;& happens continuously ithin the system, and a system of interrupts ould only slo do n operations. /t is far better to enable /;& to occur on a continuous basis, Bust as processing is done. 5he primary responsibility of the &S is to facilitate the smooth operation of the /;& bus, so that every process is given the ma(imum opportunity to use it. 5he &S uses global control operations to control use of the /;& system, and each process uses local control operations to enable its o n use of the /;& bus. A function found in conventional systems, but not present in this type of system is a memory protection scheme implemented ith soft are. /n a PSSP system, memory protection is an inherent physical property of the system. ?ach process, isolated ithin its o n apportioned section, has no access to PSSPs used for memory or instructions, e(cept those that have been assigned to it by the &S. Any attempt to reference an address outside its assigned area may cause a process to fail, but it ill not affect any PSSP outside its o n apportioned section. /t is the responsibility of each process, as designed by a programmer, to handle its input in a safe and logical fashion. 5his is as true ithin a PSSP system as it is in a conventional system. @hen the process is loaded, it is given all the input routines it needs. 5hese input routines, established by the &S, are used to copy data from the /;& bus hen that data appears on the bus. @hat the process does ith the input is not the responsibility of the &S, and ho the data is used once it is received is up to the programmer of the process. 3.3.1 9lo al Control ,perations 5here are four global control instructions used in this design, and only three of them ill be presented here. A fourth instruction that is considered global is the =&7+ instruction, but it as presented earlier ith the other t o instructions used for moving data. 5here is no need to present it again, but some aspects of its use relate to global control. /t is used to move code into the PSSPs, but it also provides distinct benefits to the &S in its efforts to maintain control over system security and stability. &f the three other instructions used for global control, t o are used for apportioning, and one

PSSP Systems 21
is used for control over output to the /;& bus. All three are used to set the high or lo state of the three corresponding global control lines. 5he t o instructions used for controlling the apportioning s itches are 'ASSS, and 'AS/S. 5he /;& bus is also used in the apportioning process, and the &S is in control of the entire process. =any details of the apportioning process ill be given here, but a complete picture of apportioning ill be presented later, in a section dealing ith that specific aspect of the system. @henever an apportioning s itch is mentioned ithin the te(t, it refers to one or more s itches that all have the same logical

address and are s itched to the same state simultaneously. 5here are single s itches used for apportioning, but it is more common to find ban#s of s itches, hich ill all change state simultaneously. Such is the case for an apportioned bus. Never ill Bust one line of a bus structure, such as the data bus, be severed by itself. 5he entire set of bus lines in the bus ill be severed at the same time. So hen an apportioning s itch is mentioned, it may refer to one s itch on one line, or multiple s itches on multiple lines. /n each case, the single s itch or the set of s itches ill all be set to the same state at the same time on the same bus structure, and they are all at the same logical point ithin the system. 'ASSS is the mnemonic for bus apportioning switch state set. 5he 'ASSS instruction sets the high or lo state of the 'ASS global control line, hich reflects the state that a particular apportioning s itch should ta#e. A high or lo on this line indicates that the referenced s itch should be set either open or closed. 5his instruction and its corresponding signal on the 'ASS global control line are used in conBunction ith the 'AS/$ control line and a s itch identification number on the /;& bus to set a s itch open or closed. 'AS/S is the mnemonic for bus apportioning switch identification set. 5he high or lo signal on the 'AS/$ line, controlled ith the 'AS/S instruction, is used to signal all apportioning s itches that the data on the /;& bus is a s itch identification number. 5his is similar to an /;& routine identification number, e(cept the identification number refers to a s itch, instead of an /;& process. 5he &S puts /;& routine identification numbers and s itch identification numbers onto the /;& bus for control purposes. 'oth numbers are accompanied by corresponding signals on their respective control lines. 5he signals are not directly related to one another, but both are used for different aspects of global control and signaling that the data on the /;& bus is an identification number. ?ach s itch has an address decoder circuit used to identify it. All s itches ill receive a high on the 'AS/$ control line at the same time that the address of one of the s itches is on the /;& bus. 5his ill occur at the same time as the state that the identified s itch should ta#e is on the 'ASS control line. 5he s itch activated in this manner ill then set its s itch to the state indicated by the signal on the 'ASS control line. 5he &S sets the 'ASS control line ith the 'ASSS instruction. 5he 'AS/$ control line is set ith the 'AS/S instruction. 'oth instructions have an operand in the processing section of the PSSP ith the instruction. 5he operand is a one or 6ero, and is used to set the control line high or lo . 'oth instructions are restricted to use by the &S only. /f the reader desires to #no more about this process, loo# at the section of te(t dealing ith apportioning. ?(ample0 5his is a simple routine sho ing the use of the t o global control instructions used for apportioning. 5his routine is part of a much larger process #eeping trac# of hich processes are in hich apportioned sections and ho all the apportioning s itches are set.

22
$##57++ P5,C7++I;9 C,;T5," C,;T5," +7CTI,; ... A000 0001 'ASSS A001 0001 'AS/S A002 00A1 &45 A00- 0000 'AS/S

/n this code, s itch A1 is set to the state represented by a one. ,irst, the 'ASS control line is made high to represent the open state for the s itch. No action occurs ithin any s itch yet. Second, the 'AS/$ control line is made high to indicate that the data on the /;& bus is a s itch identification number, but the /;& bus has no data on it yet, or is all 6eros, so still no action occurs. ,inally, hile these t o lines are high, the address of the s itch is put onto the /;& bus. No an action ill occur. &nly one apportioning s itch ill recogni6e the address, and since the 'AS/$ control line is high, the s itch state latch in that s itch ill accept hatever value is on the 'ASS control line. 5hen the 'AS/$ control line is set lo again so that another process can use the /;& bus. 5he third instruction used for global control is /&!%S, hich is the mnemonic for I/O routine line set. 5his instruction uses instruction format ,2. 5he /&!%S instruction is used to set the /&! control line either high or lo . 5he /&! control line is used to signal all /;& gate#eeper instructions that the

data on the /;& bus is an /;& routine /$ number. 5he /;& routine /$ number is similar to a bus apportioning s itch /$ number e(cept that it is used to identify an /;& routine. /&!%S is a restricted instruction that is only used by the /;& system. 5he /;& system sets the /&! control line high ith the /&!%S instruction, and then puts the /;& routine /$ number on the /;& bus. /n effect, hen the /;& system sets this line high it is telling the output process identified by the number on the /;& bus that it has permission to run its output routine. 5he high state on the /&! control line is a signal to all PSSPs actively using the >&!? or >/!? instructions that an /;& routine /$ number is on the bus. 5he high signal on the /&! control line must be detected in conBunction ith the /;& routine identification number that is in the processing section of a PSSP ith the >&!? instruction before that PSSP can initiate a Bump to its output routine. 5he same must occur for a PSSP ith the >/!? instruction. /&!%S is a global control instruction, and the t o /;& gate#eeper instructions, >&!? and >/!?, are local control instructions. =ore details on the t o /;& gate#eeper instructions and their use in relation to this control instruction ill follo in the section dealing ith local control instructions. 3.3.2 +e/uencing ,perations /n a conventional system, the +P4 uses the program counter in conBunction ith the system stac# to #eep trac# of hich memory address to get instructions from ne(t. 5his is combined ith a timesharing plan to give a portion of time to each active process in the system. 5he &S does all of this, and is in complete control, to the e(tent that the code is valid and the intent of the programmer is not malicious. 'ad code can foil this operation very easily though, and such instances can easily cause system failure re"uiring remedial action. A system built of PSSPs does not have this problem. A PSSP system has each process installed in an isolated section of PSSPs. 5here is no +P4 timesharing plan, and the &S is not involved in controlling program e(ecution by using a system stac# and

PSSP Systems 2program counter. ?ach process has its o n se"uencing stac# used to control the se"uencing. Programmers do not use the se"uencing stac# or the three se"uencing instructions. 5he &S sets up the se"uencing stac# for each program prior to program e(ecution, and it is only used for se"uencing that particular program. 5he only data in the processing sections of the se"uencing stac# PSSPs are the addresses of various points ithin the program or null data, and the only opcodes in the control sections are the three se"uencing instructions. 5echnically, a programmer can influence the addresses in the processing sections of the se"uencing stac#. 5hey can even move data into them, but they cannot affect the opcodes in the control sections e(cept indirectly, ith the use of Bump and return instructions. Some of the Bump instructions, and the return instruction, ill cause an adBustment ithin the se"uencing stac#. 5his adBustment changes hich of the se"uencing PSSPs is the active se"uencer. 'ecause the PSSPs used for the se"uencing stac# are dedicated to that purpose, their design is different from the design used for standard PSSPs. 5he only three instructions they need to e(ecute are S?J, SS?J, and S?JS%. 5his ma#es them much simpler than standard PSSPs, but in another ay they are a bit more comple( because they need to respond to the signals on the three local se"uence control lines and the se"uence master control line hich is part of the global control bus. 5he three local se"uence control lines and the se"uence master control line ill be discussed here in relation to their use for se"uencing. 5he three local se"uence control lines are part of the apportioned bus structures. 5herefore, the signals on them are local to the process they are a part of, and cannot affect any other process. 5he se"uence master control line is not apportioned, but there is a section of the bus used e(clusively for each apportioned process ithin the system. 8o the SJ= line is configured ithin the system ill be presented in detail in the section of te(t that deals ith the bus structures in the system. 5he purpose of the se"uence master control line, the SJ= control line, is to give the &S ultimate control over all se"uencing ithin the system or any individual process. 5he SJ= control line is used to enable or disable se"uencing in all processes ithin the system. A se"uencing PSSP ill stop se"uencing hen this control line goes high, and ill not start se"uencing again until it goes lo . Standard PSSPs are not affected by the state of the SJ= control line or any of the other se"uence

control lines. 5he &S sets the SJ= control line, and the three local se"uence control lines are set ithin the local process by each standard PSSP as it is fully activated. 5he /;& gate#eeper PSSPs can also influence the three local se"uence control lines, but only se"uencing PSSPs are affected by ho the four control lines are set. 5he &S uses the apportioning s itches to set the SJ= signal on various sections of the SJ= control line hile the standard PSSPs and the PSSPs used as /;& gate#eepers automatically set the three local se"uencing lines as a normal part of instruction e(ecution. 5he operating system is in control of the SJ= control line. @hile a process is being loaded, the SJ= control line ill be high in the section of PSSPs into hich the code is being loaded. 5his high signal prevents all se"uencing ithin that section of PSSPs during the loading process. After the process has been loaded and fully isolated ithin its apportioned section, the &S ill cause the SJ= line to go lo in that section of PSSPs. 5his ill cause the active se"uencer to begin se"uencing that process. /t is important to remember that every process in its o n apportioned section has its o n se"uencing stac#. 5he signals on the three local se"uence control lines only affect, and are affected by, the process of hich they are a part. 5he SJ= control line is global and it may have a high or lo signal on various sections of the line. 5his permits the &S to enable or disable se"uencing ithin the

2*
various processes that reside in the system. 5he &S is not doing the se"uencing for the processes, it is merely permitting them to se"uence or not. 5he last actions of a process terminating in an orderly fashion are to send a message to the &S, via the /;& bus, telling the &S it is terminating. 5he process ill then perform a 8%5 instruction causing the active se"uencer to become inactive as it slips into standby mode. 4pon receiving the termination message from the process, the &S ill set the SJ= signal high in that apportioned section to disable all possible se"uencing. 5he 8%5 instruction ill eliminate the only active S?J instruction, and the high signal on the SJ= control line ill disable se"uencing. 5he S?J instruction is the only se"uencing instruction that permits active se"uencing, and there is only one active se"uencer at any moment. 5he SS?J instruction is the standby se"uencer instruction. 5his instruction is in all other PSSPs in the se"uencing stac#, e(cept the t o PSSPs that begin and end the stac#. 5hese t o PSSPs have the SJS% instruction. 5his instruction causes a Bump to an error routine that generates a stac# limit message and then terminates the process. /f a person loo#s at a list of the PSSP instructions in the se"uencing stac# at any particular moment during the se"uencing of an active process, the first and last PSSPs ill have the SJS% instruction. Some here bet een the first and last PSSPs ill be one, and only one, PSSP containing the S?J instruction. All other PSSPs bet een the first and last ill contain the SS?J instructions. Se"uencing PSSPs are self.activating. 5here are no other PSSPs causing the PSSPs in the se"uencing stac# to be active. 5he se"uencing PSSP, the only PSSP ith the S?J instruction, ill activate each standard PSSP for e(ecution as long as it is the active se"uencer. As it e(ecutes each

PSSP Systems 22
instruction, the address in its processing section ill change. /t may be incremented by one or t o so that it points to the ne(t PSSP to be activated. A Bump ith no return ill cause the address to be replaced ith another address. A Bump ith a return ill cause the address to be incremented and that se"uencing PSSP to become inactive, hile the ne(t se"uencing PSSP becomes the active se"uencer. 5he ne active se"uencer ill accept an address off the data bus and begin se"uencing at the ne address. A return instruction ill cause the active se"uencer to become inactive and the prior PSSP to become the active se"uencer again. /t still has the old address at hich to recommence se"uencing. Se"uencing involves the use of the se"uencing stac#, the three se"uencing instructions, and the se"uence control lines. 5here are also t o bilateral control lines in use bet een adBacent se"uencing PSSPs. As mentioned already, the SJ= control line is a global control line that permits the &S to enable or disable se"uencing ithin any process. 8o ever, the &S is not able to affect the se"uencing in any process, other than itself, e(cept for its ability to enable or disable the se"uencing. 5he three local se"uence control lines are used to control se"uencing ithin a process. 5hese three control lines are part of the au(iliary data;control bus. 5hey are not global, li#e the

SJ= control line, but local to the process. @hen a section is apportioned for a process, the au(iliary data;control bus is one of the buses apportioned to achieve the isolation needed for the process. 5he apportioning that isolates the process also causes the control signals on the apportioned buses to be isolated to that section. ,or this reason, the three local se"uence control lines can only influence the se"uencing ithin the apportioned section of hich they are a part. 5he three local se"uence control lines are called SJ1, SJ2, and SJ-. 5hese three control lines provide for eight possible states, or conditions, to hich the se"uencing stac# must react. 5he eight possible states are enumerated belo . &nly si( of these conditions are used at this time. ?ach instruction, e(cept the three se"uencing instructions, ill set the three control lines as a normal part of instruction e(ecution. 5hey provide the necessary directions to the se"uencer as to ho to prepare for the ne(t instruction to e(ecute. /n the follo ing list, the three digits represent the three se"uence control lines SJ1, SJ2, and SJ-. 5he 6ero or one for each digit represents a high or lo signal on the corresponding control line. 5he statement follo ing the digits e(plains hat that the se"uencer needs to do to prepare for the ne(t instruction e(ecution. 000 . Not used at this time. 001 . 5he se"uencer needs to increment its address by one. 5his state is sent by all operations ith 6ero or one operand, e(cept for the Bump and return instructions. 010 . 5he se"uencer needs to accept a ne address into its processing section and commence se"uencing there. 5his state is for a Bump operation ith no return. 011 . 5he se"uencer needs to stop se"uencing and go into standby mode. 5his state is the result of the 8%5 instruction. 100 . 5he se"uencer needs to increment its address by one, and then set itself to standby mode and activate the ne(t PSSP in line to become the se"uencer. An address is then loaded into the ne se"uencer. 5his is for a Bump ith a return instruction.

26
101 . Not used at this time. 110 . 5he se"uencer needs to set itself to standby mode and activate the previous se"uencer. 5he previous se"uencer already has an address and se"uencing begins again at that address. 5his is the result of a return instruction. 111 . 5he se"uencer needs to finish the current instruction, set itself into standby mode, and activate the ne(t PSSP in line to become the se"uencer. An address is then loaded into the ne se"uencer. 5his is for the >&!? or >/!? instructions. 5 o bilateral control lines are also needed for se"uencing stac# operations. &nly one line is needed bet een every adBacent pair of PSSPs. 5hey are al ays referred to, from the point of vie of the active se"uencer, as the SSA' and SSA, bilateral control lines. 5he SSA' line goes to the PSSP that logical precedes the active se"uencer, hile the SSA, goes to the PSSP that follo s it. 4nli#e the bilateral control lines used ith the standard PSSPs for partial activation, these control lines are used to cause full activation of an adBacent PSSP as the active se"uencer goes into a standby state. 5his action is needed for se"uencing instructions that adBust hich PSSP in the se"uencing stac# is the active se"uencer. /n the follo ing set of e(amples, each of the si( used states of the three local se"uence control lines is represented by an instruction that ill cause that state. Some of the instructions are not yet familiar to the reader, and they can return to these e(amples later, if they feel the need.
$##57++ P5,C7++I;9 +7CTI,; C,;T5," +7CTI,; +T$T7 ((1 0900 0000 N&5 'efore the operation, the se"uencer is at address 0100 and contains address 0900. After the instruction, the se"uencer is at address 0100 and contains address 0901. +T$T7 (1( 0900 09A0 >=P? 'efore the operation, the se"uencer is at address 0100 and contains address 0900. After the instruction, if the Bump succeeds, the se"uencer is at address 0100 and contains address 09A0. +T$T7 (11

09000 .... 8%5 'efore the operation, the se"uencer is at address 0100 and contains address 0900. After the instruction, the se"uencer has become inactive, and there is no PSSP ith the S?J instruction. +T$T7 1(( 0900 09A0 >=P?! 'efore the operation, the se"uencer is at address 0100 and contains address 0900. After the instruction, if the Bump succeeds, the se"uencer is at address 0101 and contains address 09A0. 5he se"uencing PSSP at address 0100 is inactive for the time being and contains address 0901. +T$T7 11( 0900 0000 !?5 'efore the operation, the se"uencer is at address 0100 and contains address 0900. 5he se"uencing PSSP at address 00,, is inactive and contains address 0)00. After the instruction, the se"uencer is at address 00,, and contains address 0)00. 5he se"uencing PSSP at 0100 is inactive and contains address 0901.

PSSP Systems 2)
+T$T7 111 0900 0000 /N+ ... A000 0010 >&!? A001 0A11 N&P 'efore the operation at address 0900, the se"uencer is at address 0100 and contains address 0900. $uring the e(ecution of the /N+ instruction, a >&!? instruction, hich is self.activating, initiates a Bump to an output routine. 5he se"uencer ill finish its current instruction. @hen finished, it ill be at address 0100 and contain address 0901. 5hen it ill respond to the >&!? instruction re"uest for a Bump ith later return. /t ill become inactive, and the ne(t se"uencer in the stac# ill become the active se"uencer. 5he output routine at address 0A11 ill become the ne(t code to be se"uenced. After responding to the >&!? instruction, the se"uencer ill be at address 0101 and contain address 0A11. 5he se"uencing PSSP at address 0100 is inactive and contains address 0901.

3.3.3 "ocal Control ,perations No that you have a good idea of ho the global control instructions are used, and ho the se"uencing stac# functions ithin a process, you are prepared for an e(planation of the local control instructions. 5hese instructions include the /&%S, >&!?, >/!?, and ?&45 instructions. All four instructions are used for /;& control ithin a local process. After these are presented, it ill be easy to understand ho program flo instructions are implemented. 5he reader as introduced to >&!? and >/!? instructions earlier in the te(t. 5hese t o instructions are for conditional Bumps, but more importantly, they function as /;& gate#eepers for each process. !egardless of hether they are implemented ith speciali6ed PSSPs or the standard PSSPs, their functions remain the same. ?ssentially, they provide a method of interacting ith the /;& system and the /;& system must be used for all inter.process communications. 5he /&%S and ?&45 instructions are implemented using standard PSSPs. 5hey interact ith the gate#eeper PSSPs to provide additional elements of control that are needed for /;& operations ithin a process. /t is best to begin ith the /&%S instruction. /t is the most simple and straight for ard of the local control instructions. 5his instruction is also the only local control instruction that applicationsA programmers actually use in programming. All other local control instructions, including the three se"uencing instructions previously covered, are used by a systemsA programmer or the &S. 5he /&%S instruction is used to enable or disable the >&!? instruction. /t uses format ,2 and provides a programmer ith the ability to control hether or not a process is actively aiting for an opportunity to use its time slot to output to the /;& bus. 5he PSSP holding this instruction has a one or 6ero in its processing section. 5he one or 6ero corresponds to a high or lo state for the /&% control line. ?(ecution of the /&%S instruction causes the /&% control line to go high or lo in accordance ith the data in the processing section of the PSSP. Setting the /&% control line high or lo enables or disables the >&!? instruction. 5he PSSP ith the /&%S instruction re"uires full activation by the se"uencer and its use enables or disables the selfactivating >&!? instruction. !ecall that a self.activating instruction does not need the full activation that comes from the se"uencer via the primary address bus.

5he >&!? instruction is used for controlling output to the /;& bus, hile the >/!? instruction is used for controlling input from the /;& bus. 5he >/!? instruction does not need to be enabled or

29
disabled ith a control line. 5hese t o /;& gate#eeper instructions are both self.activating but different methods are used to enable them. 5he >&!? can be disabled ith a control line by using the /&%S instruction, hile the >/!? can be controlled simply by putting a certain value in its processing section. /t is important that a process be able to disable the >&!? instruction. /t allo s the process to control hen output to the /;& bus occurs. 'ecause the >&!? instruction is self.activating it is normally atching for its chance to output to the /;& bus. 'y using the /&%S instruction, the process can turn the >&!? instruction off hen output is not desired. 5his is not a problem ith the >/!? instruction because the process can change the value in the processing section of the PSSP ith the >/!? instruction. /t cannot do this ith the >&!? instruction. A security feature of the system is that the contents of the processing section of the PSSP ith the >&!? instruction cannot be altered, e(cept by the &S. 5he processing section holds the identification number of the output routine to hich it belongs. /f a process could alter that number, it ould be possible for the process to claim that it as another process, and ma#e illegal use of the /;& bus. 5o avoid this, the &S puts /;& routine identification numbers into the processing section of a PSSP ith the >&!? instruction, and the >&!? instruction prevents its processing section from being altered by the process. No that a brief overvie of the first three instructions has been presented more details ill be given on the >/!? and >&!? instructions. 5he special relationship that e(ists bet een the >&!?, /&%S and ?&45 instructions ill also be detailed. >/!? is the mnemonic for jump to input routine if equal. 5he >/!? instruction is self.activating, and every cloc# cycle ill see it perform its function, regardless of hat else is going on in the process. /ts function is to atch for a particular /;& routine identification number, the /&! number, to sho up on the /;& bus in conBunction ith a signal on the /;& routine control line. 5he /;& routine control line is used to indicate that the data on the /;& bus is an /;& routine identification number. /f the /&! number sho s up in conBunction ith the correct signal on the /&! control line, a Bump to an input routine ill be initiated by the >/!? instruction that is atching for that particular /&! number. /n the processing section of the PSSP ith the >/!? instruction, is an /;& routine identification number. &n each instruction cycle, this number is compared ith hatever data is on the /;& bus at that moment. /f the numbers match, and the /& routine control line signal is high, then the Bump conditions have been met and a Bump ill be initiated. 5he >/!? instruction is self.activating, so the Bump is al ays initiated in the middle of a processing cycle in hich the se"uencer is e(ecuting some other instruction. 5o handle this situation, the se"uencer completes its current e(ecution cycle, and then permits the Bump to proceed, hich is hy the >/!? and >&!? instructions re"uire four cloc# cycles to complete instead of the normal t o cycles common to most other instructions. 5o disable the >/!? instruction, the process loads a dummy /;& routine /$ number into the processing section. Since the number is not a real /;& routine, it is not possible for the number to occur on the /;& bus in conBunction ith a high signal on the /&! control line. 5his effectively disables the >/!? from initiating a Bump to an input routine. @hen the process ants more input, it puts the identification number of the desired input into the processing section of the >/!? instruction. ?ach type of input needed by a process has its o n input routine. 5he &S installed the input routines as part of the loading process. 5he &S provides the process ith the id number, the input routine, and the starting address of the routine for each type of input the process needs. /f a process needs three different inputs, it receives three /;& routine id numbers, three input routines, and a corresponding start address for each input routine.

PSSP Systems 23
?ven though there may be several input routines, there only needs to be one /;& gate#eeper PSSP ith the >/!? instruction. @hen a particular type of input is desired, the /$ number is put into the processing section of the PSSP ith the >/!? instruction. 5he processing section of the follo ing PSSP receives the address of the input routine. &nce the data is put here it belongs, the PSSP ith the >/!? instruction chec#s for that particular /;& routine /$ number in every e(ecution cycle. @hen Bump conditions are met and the se"uencer is ready to initiate the Bump, a bilateral control line partially activates the processing section holding the address. 5his causes the address to be put on the data bus so the se"uencer can accept the address into its processing section. 5hen the se"uencer can begin instruction e(ecution at the ne address, the address of the input routine. $ata copied from the /;& bus cannot harm the system or interfere ith another process, so there are no safeguards about hen it may or may not occur. Any process is free to gather data from the /;& bus at any time. 8o ever, output to the /;& bus is a completely different matter. /t is strictly controlled, and there must be no possibility of a process interfering ith that control. 5he differences bet een the >/!? and >&!? instructions are accounted for by the need of the &S to maintain strict control over output onto the /;& bus. >&!? is the mnemonic for jump to output routine if equal. 5he >&!? instruction is different from the >/!? instruction in that it can be enabled or disabled, but it does not permit its /&! number, or the associated routine starting address to change. ,or each type of output needed by the process a separate >&!? instruction is re"uired. 5here is one other security feature built into this instruction that ma#es it different, and it ill be presented after the instruction. Aside from these differences, the >&!? instruction functions Bust li#e the >/!? instruction. %i#e the >/!? instruction, it atches for a particular /$ number to sho up on the /;& bus in conBunction ith a signal on the /&! control line so it can initiate a Bump to an output routine. 5he process can enabled or disabled the >&!? instruction by using the /&%S instruction to set the /&% control line high or lo . &ther than this ability to enable or disable the instruction the process has no influence over it once se"uencing has commenced. @hen the process is loaded the &S inserts the >&!? instruction, the /&! number, the starting address of its routine, and the code for the routine. 5he process cannot change any of these items and an entire set of them is needed for each type of output that the process must put onto the /;& bus. 5he instruction set sho s no format for the >&!? and >/!? instructions because a programmer does not use them in programming and they ould also re"uire a special format of their o n. 5he format of the instructions is very similar to ,-. 5he opcode goes in the first PSSP control section. 5he second PSSP control section has a N&P instruction. 5he processing section of the first PSSP ill have the /&! number that ill be compared against the ' input that enters from the /;& bus. 5he processing section of the second PSSP contains the starting address of the output routine associated ith that /&! number. 5he comparison bet een the data on the /;& bus and the /&! number in the processing section is accomplished ith the K&! operation, but the instruction does not ma#e use of the e"ual flag control line. 5he e"ual condition is generated and used internally ithout use of flag control lines. 5his avoids possible conflict ith other PSSPs that are being fully activated by the se"uencer. 'oth instructions set the three se"uence control lines to the same state, but only hen Bump conditions are met. 5he timing of sub.operations ithin these instructions is an important issue to consider. 5here must be no interference ith other fully activated PSSPs ithin the process.

60
@hen the >&!? instruction finds that its Bump conditions are met, it begins initiating a Bump. 5he

process of Bumping ith the >/!? and >&!? instructions is rather comple( because of the selfactivating nature of the instructions. 5hese PSSPs must not interfere ith normal se"uencing occurring ithin the process. 5he >&!? instruction is more comple( than the >/!? instruction because of security features built into the instruction. &ne of these security features has already been mentioned. 5he &S sets up the contents of the PSSPs used for the >&!? instruction hen they are loaded. 5hereafter they cannot be altered. 5he other security feature built into the instruction deals ith the relationship bet een the >&!? and the &45 instruction. /n the earlier presentation of the &45 instruction, / mentioned that the !;@ line must be in the correct state for the &45 instruction to output to the /;& bus. =ost instructions set the !;@ line as needed during the e(ecution of the instructionDnot so ith the &45 instruction. 5he >&!? instruction sets and holds this line to the correct state after it has initiated its Bump and the se"uencer has been set up ith the address of the output routine. Put another ay, only the >&!? instruction can enable the &45 instruction to release data onto the /;& bus by holding the !;@ control line in the correct state. 5his prevents accidental or malicious attempts to improperly output onto the /;& bus. ,or instance, suppose an output routine as set up, and someho a Bump as made to the routine ithout going through the >&!? instruction, the gate#eeper for the output routine. /f the &45 instructions ere enabled, it ould put data onto the /;& bus at an improper time, ithout receiving permission from the &S to do so. 5o overcome this potential for disruption of the /;& bus the >&!? instruction must enable the &45 instruction via the !;@ control line. 5his insures that the &45 instruction cannot function unless the >&!? instruction has first performed its function as the /;& gate#eeper. 5he ?&45 instruction is used to terminate the signal on the !;@ control line. /t uses format ,1 and causes the >&!? instruction to release the !;@ line bac# to its normal state. 5he ?&45 instruction is the second from the last instruction in the output routine. 5he ne(t to the last instruction is the /&%S instruction. /t is used to set the /&% control line to the proper state to disable the >&!? instruction. 5he last instruction is the !?5 instruction, hich ends the routine and returns to here the program left off before being interrupted for the output routine. /t is important to remember that the programmer has no influence over the output routines or their construction e(cept for the information that is passed to the &S during the loading process. 5he programmer supplies the &S ith information that indicates hat the /;& needs of the process are. 5hen the &S safely installs and controls the /;& routines. @e revie the instructions and code here only to understand the system, not to gain #no ledge of ho to use these four instructions. /f the programmer ere to try to include such code or instructions in a process, the &S ould reBect it. 5he one /;& instruction that the programmer does use is the /&%S instruction that is used to enable or disable the >&!? instruction. 5he Bumps to an input or output routine must al ays include a return. A return from a Bump assumes that the old address as saved for use ith the return instruction. 8o this and other program flo instructions are accomplished ith the se"uencing stac# is the subBect of the ne(t section. ,ollo ing is an e(ample of hat happens during an output routine. 5he e(ample is a small portion of a mouse routine that constantly receives input from a physical device, a mouse, and must translate that input into a form used by all other processes ithin the system. 5his data must be put onto the /;& bus hen the process has permission to do so.

PSSP Systems 61
5he mouse routine has /&! number 0002, and the mouse output routine to the /;& bus begins at address 0A00. 5he output routine needs to put t o data units onto the /;& bus. 5he output is not intended for any particular process, so no receiver /$ number is needed. @ith the preceding information, the output data cycle for the process is constructed as sho n in the diagram. 5he output data cycle starts the moment the &S puts the /&! number onto the /;& bus hile setting the /&!

control line high so that the process #no s its turn to output to the /;& bus has arrived. 5he output data cycle ends hen the last data pac#et is put onto the /;& bus. 5he output cycle used for this e(ample is five cycles of +%L2. ,or this e(ample, assume the data has already been put into the output buffer, hich is the series of &45 instructions in the output routine. Also assumed is that the process has set the /&% control line high, so that the >&!? instruction is enabled. 5he code for the process is as follo s.
$##57++ P5,C7++I;9 C,;T5," C,;T5," +7CTI,; ... 0A00 0000 &45 /$ number of receiver. 0A01 .... &45 ,irst unit of mouse data. 0A02 .... &45 Second unit of mouse data. 0A0- .... ?&45 $isable &45 instructions. 0A0* 0000 /&%S $isable the >&!? instruction. 0A02 .... !?5 !eturn from the output routine. ... 0'00 0002 >&!? /;& gate#eeper set for 0'01 0A00 N&P &utput of mouse data .

62
.. 1000 .... ..... 'eginning of main code for 1001 .... ...... 5he mouse routine receiving input from the mouse, and putting it onto the %& bus. ... 1100 0001 /&% /&% control line is set high to enable >&!? instruction at address 0'00. ... 110A .... 110' ....

@ith the code as sho n, let it be assumed that hile the se"uencer is e(ecuting the instruction at address 110A it receives a signal on the three se"uence control lines. 5his signal indicates that the >&!? instruction at address 0'00 needs to interrupt the main process to output data onto the /;& bus. 5his situation implies that the >&!? instruction has detected 0002 on the /;& bus in conBunction ith a high signal on the /&! control line. A trace of the order of events ill no be sho n using cloc# cycles as the measure. ?ach change in the se"uencing stac# is sho n, as ell as each event. 5he se"uencer uses the +%L2 signal to begin an instruction cycle. 5he +%L1 signal is t ice the rate of +%L2, and it is used for sub.operations ithin the instruction cycle. !ecall that the active se"uencer has the S?J instruction used for se"uencing PSSPs in the standby mode. @here an un#no n opcode e(ists ithin the code, at addresses 110A, 110', it is assumed that the instruction only re"uires one +%L2 cycle to e(ecute. <$t this point go = separate diagrams that ha%e no la els or captions and all look %ery similar. To order them) or put them in the correct se/uence) please look care'ully at the le'tmost ox o' each diagram. ;otice the la el in each that is >C"? 2@. Then notice the num er in each >C"? 2@ ox in each o' the nine diagrams. The num ers indicate the ordering o' the diagrams. .irst C"? 2 >1@) then C"?2 >2@) etc.A

PSSP Systems 66* PSSP Systems 62

66
5he only instructions left to discuss are those that involve program flo . 5hese instructions are similar to those found in a conventional system, but their implementation is a bit different in this design. 5here are more Bumps in this instruction set than necessary for programming. ,or each of the three condition flags that can be used for Bump decisions, there is a Bump ithout a return and a Bump ith a return. /n addition, there is an unconditional Bump, a !?5, a 8%5, and a N&P instruction. 5hat ma#es ten instructions to be covered in this section. 5he three flag signalsDcarry, negative, and e"ualDare automatically generated for arithmetic or logical operations. 5he e"ual flag signal can also be generated ith the +=P instruction. 5he >&!? and >/!? instructions do a comparison of data to generate an e"ual signal, but they do not use the e"ual flag control line. 5heir signals are internal to the PSSPs holding the instructions. 5he e"ual flag does not affect the >&!? or >/!? instructions, nor do these t o instructions affect the e"ual flag. 5he /;& gate#eeper instructions are not considered Bump instructions because their purpose has more to do ith control. 5he format for all seven of these Bump instructions is ,2. ,ormat ,2 has the opcode in the control section and the address to Bump to in the processing section. All of the conditional Bump instructions cause a reset of the flag control line used for testing the condition. 5he other three instructions, 8%5, N&P, and !?5, all use the ,1 format. 5he ,1 format has the opcode in the control section of a PSSP, but there is no operand involved in the instruction. 5he seven Bump instructions can generate t o different states in regards to the se"uence control lines depending on hether or not a return is needed. Se"uence control lines are set to 010 if no return from the Bump is needed, or 100, if a return is needed. 5hese t o states for the se"uence control lines represent different sets of action in relation to the Bump instructions. ,or a Bump ithout a return, the se"uencer accepts a ne address into its processing section and no adBustment in the se"uencing stac# is needed. ,or a Bump that needs a return, the se"uencing stac# must adBust for ard one PSSP, so that the return address is saved. 5hen it accepts the ne address, the address to Bump to, into the processing section of the ne se"uencing PSSP. 3.!.1 Bumps &ithout a 5eturn ,our Bumps in the instruction set are not follo ed by a return. 5hree involve flag conditions, and one is the unconditional Bump. All four of them use only one PSSP that ill hold the address in the processing section and the opcode in the control section. All cause the se"uencer to increment itself by one unless the Bump succeeds. /f the Bump succeeds, the address in the processing section of the se"uencing PSSP ill be replaced by the address in the processing section of the PSSP ith the Bump opcode. 'ecause the address in the processing section of the se"uencing PSSP is replaced, it is permanently lost. ?(ample0 5his is a simple routine sho ing the use of t o Bumps ithout a return. 5he first is an unconditional Bump, and the ne(t a Bump on carry. /t is important to understand ho the se"uencing stac# reacts to the Bumps, so stac# information ill be given for each Bump. "%& Pro!ra' Flow Operations

PSSP Systems 6)
$##57++ P5,C7++I;9 +7CTI,; C,;T5," +7CTI,; ... ... ... 0900 0300 >P= 0901 1111 N&N

/n this first Bump, the se"uencer at address 0100 contains the address 0900 before the Bump. After the
Bump, it is still at 0100, but it contains address 0300.

...

... ... 0300 0100 A$$+ 0301 0600 N&P 030- A000 >=P+ ... ... ... A000 .... .... 5he second Bump, at address 030-, is conditioned on herther a carry e(isted after the A$$+ instruction e(ecuted. /f true, then after the Bump the se"uencer ill still be at address 0100, but it ill contain address A000. /f the Bump did not succeed, the se"uencer ill still be at address 0100, but it ill contain address 030*.

3.!.2 Bumps &ith a 5eturn &nly three Bumps in the instruction set must be follo ed by a return. All three are conditional Bumps and use format ,2 ith the address in the processing section and the opcode in the control section. All cause the se"uencer to increment itself by one regardless of hether or not the Bump succeeds. /f the Bump fails the se"uencer remains at the same address, and because it as incremented by one, it ill activate the ne(t PSSP in line on the ne(t cloc# cycle. /f the Bump succeeds, several actions ill occur. 5he se"uencer has already been incremented, so it already points at the ne(t PSSP in line. 5he Bump has succeeded, ho ever, and there is a return from the Bump at some later point, so the address in the se"uencer needs to be saved for the return instruction. 5he se"uencing PSSP ill put itself in standby mode and activate the ne(t PSSP in line to be the se"uencer. As the ne(t se"uencing PSSP becomes the se"uencer, it ill accept an address into its latches from the data bus. 5he PSSP ith the Bump instruction has already put the address onto the data bus, and after accepting it into its latches, the se"uencer ill be ready to activate the correct PSSP on the ne(t cloc# cycle. 5he previous se"uencer is no in standby mode and the address in its processing section has not been replaced, so it remains ready for use hen a return instruction is e(ecuted. ?(ecution of the !?5 instruction ill cause the three se"uence control lines to signal the current se"uencer that it must go into standby mode and the previous se"uencer must again become active. 5he previous se"uencer still holds the ne(t address that as to e(ecute before the Bump occurred.

69
?(ample0 5his is a simple section of code sho ing the use of a Bump that has a return. 5he reader should reali6e by no that if a Bump does not succeed, there ould be no change in hich PSSP is doing the se"uencing. /n addition, the address in the se"uencer ill be incremented to point to the ne(t PSSP in line. 5herefore, the follo ing e(ample assumes the Bump succeeds, and the notes on the se"uencer ill only refer to that situation.
$##57++ P5,C7++I;9 C,;T5," C,;T5," +7CTI,; 0300 0100 A$$+ 0301 0600 N&P 030- A000 >=P+! ... ... ..

A000 .... .... ... ... ..

.
A0A0 .... !?5 'efore the Bump at address 030-, the se"uencer ill be at address 0100 and contain address 030-. After the Bump ;return, the se"uencer ill be at address 0101 and contain address A000. 'efore the !?5 instruction at address A0A0, the se"uencer ill be at address 0101 and contain address A0A0. After the !?5 is e(ecuted, the se"uencer ill again be at address 0100 and contain address 030*.

3.!.3 57T) ;,P) and *"T ?(cept for the 8%5 instruction, these instructions have already been used in some of the coding e(amples. All three are very similar to instructions in a traditional system. All use the ,1 format, re"uiring the opcode in the control section, hile the contents of the processing section are not important as far as the operation is concerned. 5he !?5 instruction is used to implement the return from a Bump. /t causes the stac# to adBust bac# one PSSP and to resume se"uencing here it left off before the Bump. 5he !?5 instruction needs no operand because the old address is still in the PSSP that as the se"uencer before the Bump occurred. 5his instruction sets the se"uence control lines to 110, hich causes the current se"uencer to become inactive and the previous se"uencing PSSP to become active again. 5he address of the ne(t instruction to e(ecute is still in the processing section of that PSSP. 5he N&P instruction is used in the PSSP control sections that must have an opcode, but here no action is desired. 5he operand in the processing section of the PSSP ith the N&P instruction is either data being stored or an operand for one of the adBacent instructions. /t is also possible to use the N&P instruction for timing. 5he 8%5 instruction stops se"uencing ithin a process. /t is al ays the last instruction in the main program, or part of an error routine that ends ith the termination of the process. &nce the 8%5 instruction is e(ecuted the process cannot restart e(cept through the intervention of the &S.

PSSP Systems 63
3.- Coding 7xample =any short e(amples of using the code have been given, and more ill come at various points ithin the te(t. 8ere is Bust one e(ample of an entire algorithm implemented ith these opcodes. <oing through the e(ample systematically is a good ay to become familiar ith ho the instructions are used. =ost readers have used a programming language to implement a bubble sort routine at some point in the past, so the algorithm ill be familiar.
B8BB"7C+,5T <1()(D((A $##57++ P5,C7++I;9 +7CTI,; C,;T5," +7CTI,; 0900 .... N&P Start of the array to sort. 0901 .... N&P Second item in the array.
... ... ...

0903 .... N&P %ast item in the array 090A ,,,, N&P Negative 1 used to decrement.

090' 000A N&P Number of elements in the array. 090+ 0900 N&P 'eginning address of the array.
... ... ...

0300 000A N&P 0301 0900 N&P

?nter the routine ith the address of the array and the number of elements in it.

0302 0300 =&78 030- .... A$$+ 030* 090A N&P <et the array si6e and adBust it for the number of times necessary to go through the outer loop. 0302 030- =&78 0306 .... N&P 030) 0329 =&75 <et the si6e of the outer loop and put a copy here it is needed for use by the inner loop. 0309 0000 +=P 0303 030- N&P 030A 03-* >=P? +hec# the outer loop control variable, and if it is e"ual to 6ero, then sorting is done. >ump out of the loop. 030' 0301 =&78 030+ .... N&P 030$ 0312 =&75 &ther ise, there is more sorting to do. 5o do the inner loop again, get the start of array and put it in the inner loop. 030? 0301 =&78 030, .... /N+ 0310 0311 =&75 <et the starting address of the array again. /ncrement it by one to get address of the second item. Put a copy in the inner loop. 0311 .... =&78 0312 .... N&5 031- 0312 =&78 031* .... /N+
5he address of the second item as put here earlier. No , get the contents of that address and negate it by using the N&5 and /N+ instructions.

)0
0312 .... =&78 0316 .... N&P 031) 0319 =&75 5he address of the first item to test as put here earlier. <et the contents of that location, and put it at address.

0319 .... A$$+ 0313 031* N&P 031A 0329 >=PN No , add the first t o items together, and if the result is negative, they do not need to be s itched. 031' 0312 =&78 031+ .... N&P 031$ 0321 =&75 &ther ise, they need to be s itched. <et the address of the first item to s itch, and put it at address 0321. 031? 031+ =&78 031, .... =&78 0320 .... N&P 0321 .... =&75 <et the address of the second item. 5hen get the contents of that address. No put the contents of the second address at the address of the first item. 0322 0311 =&78 032- .... N&P 032* 032) =&75 No get the second address again, to use for storing the first item. Put the address here its needed at 032). 0322 0316 =&78 0326 .... N&P 032) .... =&75 <et the contents of the first address and put it here the second item as previously. 0329 .... A$$+ 0323 090A N&P 032A 0000 +=P 032' 0329 N&P 5he number of times to do the inner loop as put at address 0329. $ecrement it, and then compare it to 6ero. /f it is 6ero, Bump out of inner loop. 032+ 030- >=P? 032$ 0311 =&78 032? .... N&P 032, 0312 =&75 03-0 0311 =&78 03-1 .... /N+ 03-2 0311 =&75 /f not 6ero, adBust the addresses of the t o items to chec# for the nest time. 5he second item no becomes the first item, and the ne second item is the ne first item, plus one. 03-- 0311 >=P4 <o bac# and do the inner loop again. 03-* .... !?5 All the sorting is doneH leave the

routine.

PSSP Systems )1
! Building a +ystem 4p to this point, the te(t has presented many details on the design and capabilities of PSSPs, and on the code that can be used ithin a system built of PSSPs. @hile details have been presented on other aspects of a system built around the use of PSSPs, they have not sho n ho everything functions as a total system. 5he PSSPs are the heart of the system, and it is logical to present them first, considering ho their use enables this system to function. No it is time to sho ho such a system can be implemented, and ho all the pieces or# to furnish a functional system. Several aspects need to be coveredDthe operating system, ho apportioning is accomplished, and the bus structure design hich serves to unite the PSSPs hile also serving as a means of apportioning groups of PSSPs for various processes. 5he bus structures and apportioning are covered ne(t. 5hen, after the last of the hard are is presented, the &S ill be e(plained. @hile apportioning divides the PSSPs into isolated sections that can be assigned as an e(clusive resource to each process, it is actually the buses that are split into sections or apportioned. 5here is a direct relationship bet een apportioning and the design used for the bus structures. /magine a long, continuous bus ith PSSPs attached to it in a long, continuous line. No , divide that bus into sections, and you ill see that each section of the bus has a group of PSSPs isolated to that section of the bus. 5his is a very simplified picture, but it sho s that it is actually the bus structures that are split into sections to achieve the apportionment of the PSSPs. !.1 Bus +tructures Several of the bus structures ithin this type of system are not found in a traditional system. 5here are t o different address buses and an au(iliary bus that is used for different purposes at different times. 5he /;& bus in this system is more e(tensive than hat is found in a traditional system. /n addition to e(tra bus structures, there are several uni"ue aspects to the design of several buses. As noted already, some can be divided into sections, hile others cannot, and one particular control line of the global control bus is built ith a tree.li#e structure. 5hese different bus structures provide a means of apportioning the system into isolated groups of PSSPs, a means of inter.process communications, and a means of providing control over the individual processes as ell as the entire system. 5he bus structures ithin this system are not Bust a passive set of lines used for various purposes. 5hey are comple( obBects ith active control elements that serve as dynamic structures ithin the system. Some aspects of the bus structures are actually more comple( than the PSSPs they serve to unite. @hile all the bus structures unite the system as a hole, they are also the means of dividing the system into sections. 5he PSSPs have different functions, but they donAt change from moment to moment as the system handles its processing load. 5he configuration of the buses ill change from moment to moment, depending on the needs of the &S and the processes resident ithin the system. +onsider the data bus in a system apportioned among ten different processes. 5here ill be ten or more different sections of the data bus, each of hich carries its o n set of signals for the process using that particular section of the bus. /f the &S loads one more process, a comple( set of operations ill occur, resulting in eleven or more separate sections of the data bus. Some of the processes may have been temporarily stopped hile the &S used its portion of the data bus and restarted after the &S

)2
no longer needed the bus. 5his is never done to the data bus alone, but it involves similar actions on the au(iliary data;control bus and secondary address bus. 4nderstanding the bus structures ithin this system is easier if they are divided into t o basic groups, bus structures that are apportioned and those that are not. 5he apportionable bus structures are those that can be divided into sections to accomplish the isolation of groups of PSSPs. 5he nonapportionable bus structures are those to hich this is not done. 5he t o different groupings provide for different needs ithin the system. 5he apportioned bus structures serve to isolate groups of PSSPs and provide the necessary interconnections ithin an isolated group that becomes the e(clusive

resource of a process. 5he non.apportioned bus structures serve to interconnect all the PSSPs ithin the system, regardless of hich isolated group they belong to, providing a means of system control and communications bet een the other ise isolated groups. @hile a lot of emphasis is placed on hat is accomplished by the various actions surrounding the buses it should be remembered, that at the highest level the &S is controlling the bus structures. @hether it is control over the /;& bus, apportioning of resources, or controlling here se"uencing may occur, it all comes bac# to a similar type of action. /n all cases, hat the &S is actually controlling are the bus structures in the system. As as stated in the beginning of this section, the bus structures in this system are a vital and dynamic part of the system. /t is the principle tas# of the &S to control them. !.1.1 ;on0apportioned Bus +tructures 5he non.apportioned bus structures connect all the isolated sections of PSSPs ithin the system. 5his does not mean every bus line from every non.apportioned bus goes to every single PSSP, but that the signals on the non.apportioned bust structures are available e"ually to every isolated process ithin the system. All PSSPs connected to these bus structures receive the same signals at the same time. 5here is one e(ception to this in the SJ= control line of the global control bus that ill be discussed in detail further on in this section. 5he global control bus and the /;& bus are the only t o bus structures not apportioned. 5he /;& bus has been mentioned several times ithin the te(t. /t serves as the means of communication bet een all the isolated processes. 5his bus is linear in design and never divided into sections. /t is available and connected to every standard PSSP ithin the system and every /;& gate#eeper PSSP. ?very standard PSSP has the potential to receive input from the /;& bus, as ell as put data onto the /;& bus. Putting data onto the /;& bus is strictly controlled, but every standard PSSP has the potential to be used for the &45 or /NP instructions. 5he /;& bus is strictly a data busDno part of it carries a control signalDbut the data may be used for control purposes. ,or e(ample, the /;& routine identification numbers and apportioning s itch identification numbers are both carried on the /;& bus. 5hese numbers are used for control purposes, but hen the numbers are on the /;& bus, they are Bust data, not a control signal. 5he /;& bus is used to carry all data flo bet een isolated processes. /t also is used in the traditional sense of an /;& bus, for the flo of data bet een /;& devices connected to the system. 8o ever, in this system is serves a much larger purpose. All data coming into or leaving an isolated process is considered to be /;& in relation to the process. /t can only enter or leave the process via the /;& bus. 5he number of bit lines in the /;& bus is e"ual to the number of bit positions in the processing sections of PSSPs. 7arious processes can use the data carried on the /;& bus for different purposes. /t is

PSSP Systems )carried on the bus as a set of parallel bits put onto the bus by the processing section of a PSSP as the result of an &45 instruction. 5hat is the only ay for data to get onto the /;& bus. 5he only ay for data to be copied from the /;& bus is ith an /NP instruction. /n all cases a gate#eeper PSSP is used to control hen the /NP and &45 instructions may e(ecute and the gate#eepers are only permitted to e(ecute their Bumps to an /;& routine hen allo ed by the &S. ?ven in the case of an /;& hard are device, such as a mouse or #eyboard, the device must output to the system via a set of PSSPs in an apportioned section. 5hese PSSPs, and the process associated ith them, receive the input from the hard are device before it can be put onto the /;& bus. No device is connected directly to the /;& bus, and a process al ays e(ists bet een the device and the bus. /t is possible that the apportioned section of PSSPs assigned to the device does no more than serve as a gate ay to put the data onto the bus, but it must al ays be there as an intermediary bet een the device and the /;& system. %i#e ise, the /;& system acts as an intermediary bet een the isolated processes ithin the system.

All data flo and messages bet een processes, including system process that are isolated in different apportioned sections, must flo bet een source process and destination process via the /;& bus. ,urthermore, /;& routines can only access the /;& bus via use of the PSSPs used for the /;& gate#eeper instructions. 5here are no e(ceptions, /;& ithin this system is a strictly controlled process. 5he /;& system, or the &S, strictly controls use of the /;& bus. An in.depth e(planation of the /;& system is given in the section dealing ith the &S later in the te(t. 8ere, it is important that the reader see the /;& bus for the integral part of the system that it is. Almost every PSSP in the system is connected to the /;& bus and the primary duty of the &S is to handle the /;& system. All data flo bet een the isolated processes can only occur via the /;& bus and data used to control various aspect of the system must also flo via the /;& bus. /t should be apparent that the /;& bus is such an important part of the system that ithout it, there is no system. 'ecause the /;& bus occupies such an important position ithin the system, its use must be rigidly controlled. /t is necessary to insure e"uable use of the /;& bus by all processes, and to maintain the security and integrity of the system. Since all processes are isolated ithin their apportioned sections, the only ay for a process to influence another process, or the system, is through the /;& system and its bus. ?ven a rouge process, see#ing to usurp system or process resources, ill need to ma#e use of the /;& bus. >ust as the /;& bus is under control of the &S, so is the global control bus. 'oth the /;& bus and the global control bus remain undivided, global in design and use, and controlled by the &S. No local control signals are carried on the global control bus. +ontrol local to a process is handled ith the au(iliary data;control bus. 5he primary process, the operating system, uses the global control bus to control system resources. 5he global control bus carries global control signals that are e"ually distributed to all processes, but it is not used for data flo , nor does it handle interactions bet een isolated sections. 5his statement needs to be "ualified some hat because the &S does interact ith the system and individual processes as needed, via signals on the global control bus, but non.system processes are unable to use it for this purpose. 5he &S uses privileged instructions to control all non.autonomous signals on the global control bus. 5he global control bus carries global control signals that go to every process ithin the system. Some signals go to every PSSP, others go only to the se"uencing PSSPs, and still others are used to control the apportioning s itches. 5here are seven control signals carried by the global control bus.

)*
5hey include the t o cloc# signals, the t o signals used to control the apportioning s itches, one signal used for /;&, one used for riting code into control sections, and the SJ= signal that is used to enable or disable se"uencing ithin apportioned sections of the system. 5he t o cloc# signals, +%L1 and +%L2, are autonomous and similar to the cloc# signals in conventional systems. +%L1 is the signal used to control individual actions ithin an operation. =ost instructions re"uire more than one cycle of +%L1. /t serves as the timer for sub.operations, hile +%L2 serves as the cloc# signal for se"uencing. 5he +%L1 signal pulses t ice for every pulse of the +%L2 signal. 5hese signals are not controlled by the &S, and are hard are.generated to serve as the timing constant for the system. 5he 'ASS and the 'AS/$ signals are used to control the apportioning s itches. 5he 'ASS signal, bus apportioning switch state signal, represents the state a particular apportioning s itch should ta#e. An open or closed s itch state is indicated by a high or lo signal on this control line. 5his signal is used in conBunction ith the 'AS/$ apportioning control signal, and a s itch identification number. 'AS/$ stands for bus apportioning switch identification and it is used to inform all apportioning s itches that the data on the /;& bus is the identification number for an

apportioning s itch. >ust as the /&! control line is used to signal that a number on the /;& bus is an /;& routine identification number, the 'AS/$ control line is used to signal that a number on the /;& bus is a s itch identification number. 5hese t o control signals, 'AS/$ and 'ASS, are used in conBunction ith an identification number on the /;& bus to cause a particular apportioning s itch to be set open or closed. 'oth of the signals are set on their corresponding control line ith privileged instructions belonging to the &S. 5he control signal used for input and output is the /&! control line. /&! stands for I/O routine and it is used to inform all PSSPs ith active >&!? or >/!? instructions that the data on the /;& bus is an /;& routine identification number. 5his allo s the /;& gate#eeper instructions to distinguish the identification numbers of /;& routines from the other data on the /;& bus. 5he /&!%S instruction is used to set the /&! control line high or lo . 5his is done by the /;& system as it controls the use of the /;& bus. 5he /;& system ill put an /;& routine number on the /;& bus at the same time as it sets this control line high. 5his ill create the conditions needed by a PSSP being used as an /;& gate#eeper to initiate a Bump to an /;& routine. +@? stands for code write enable and is used by the &S in conBunction ith the =&7+ instruction to rite code into the control section of PSSPs. 5he signal is generated by the PSSP using the =&7+ instruction. =&7+ is a privileged instruction, available only to the &S. &rdinarily, the data output from a processing section goes onto the data bus, /;& bus, or an address bus. 5he data flo controller in the processing section of a PSSP selects the output channel. 5he control section of a PSSP, in response to its opcode or other control signals, directs the data flo controller. 5he au(iliary data;control bus is the only bus that can input data into the control section. 5he =&7+ instruction causes the data flo controller to direct output onto this bus. 5he data put on the au(iliary bus ill be deposited into the PSSP selected by the secondary address bus. 5his transfer of data is enabled by the +@? control signal on the global control bus. 5here is no instruction to set this signalH it is automatically generated ithin the PSSP e(ecuting the =&7+ instruction. 5he only remaining global control line to discuss is the SJ= control line. 5he acronym stands for the sequence master control line. 5his line as briefly discussed earlier in the te(t, but no / ill give a full e(planation of this control line and its use. 5here are several uni"ue aspects to this control line. ,irst, and most important, this control line gives the &S the ability to enable or disable the se"uencing

PSSP Systems )2
ithin any process or group of processes. Second, the structure of this control line is uni"ue ithin the system. ,inally, the method the &S uses to control the signal on this line is also uni"ue. 5he reader ill recall that the au(iliary bus carries three se"uencing control signals local to a process. 5he SJ1, SJ2, and SJ- control signals provide guidance for se"uencing the process ithin an apportioned section. @hile these three lines ta#e care of se"uencing ithin a process, there needs to be a ay for the operating system to suppress, or disable, the se"uencing ithin a process. 5hat is the function of the SJ= control line.

)6
/n a PSSP system, each process runs simultaneously ith other processes, each in its o n apportioned section. /t is the control the &S has over the SJ= control line that tells a process hen, and if, it can se"uence its instructions. 5he &S can enable or disable the se"uencing in a process, but it cannot affect the se"uencing ithin a process in any other ay. 5he physical layout of the SJ= control line enables it to reach any single process, or combination of processes, ithin the system ithout interference to other processes. 5he linear nature of the apportioned buses creates situations in hich the &S must temporarily borro portions of the buses to load a process into a ne ly apportioned section. /f the &S is going to temporarily use a particular section of bus, some process may need to temporarily surrender its use of it. 5o do that, the process must stop se"uencing. 5he correct signal on the SJ= line ill accomplish this for the &S, but never hile a process is running an /;& routine, and it may be necessary for the &S to ta#e this action for multiple process at the same time. 'orro ing the bus sections involves manipulation of the apportioning s itches for the buses involvedDthe au(iliary, data, and secondary

address buses. 5he primary address bus is also an apportioned bus, but it is not used in the loading process 5he SJ= control line is the only bus line in the system ith a tree.li#e structure. At each ne branch, or node, in the tree.li#e structure is a s itchH at the end of all the branching structures are the sections of the SJ= control line that belong to each apportioned section of PSSPs. A diagram of this structure is included above. 5his structure is necessary so that any single, or group, of apportioned sections can be reached ithout interfering ith the others. 5o enable a process, the signal in that section of the SJ= control line must be lo , and to disable it the signal must be high. 5he signal for the line is normally high to suppress, or disable, se"uencing. 5here is no instruction that sets the SJ= signal high or lo , nor is each section of the control line addressable as a uni"ue section. 8o ever, every s itch used to divide the line into sections is addressable. 'y setting each s itch or group of s itches open or closed, it is possible to control the SJ= signal on the various sections of the control line. /t may seem that this control line is an anomaly ithin the system bus structure. &n the one hand, it is placed in the global control bus because it gives control to the &S over various parts of the system, but the global control bus is not apportioned. 8o ever, the global control bus includes the SJ= line that is divided into sections, similar to the apportioned buses. /ts function as a global control line is the more important aspect of its uni"ueness, hich is hy it as placed in the non.apportioned global control bus. A close loo# at its structure reveals that it is not divided in the same ay as the apportioned bus structures, ma#ing it very different from them. 5here is some controversy about hether it is a necessary part of the system. 5he ability to enable or disable se"uencing is a necessary function ithin the system, but there may be another ay to accomplish the same thing. /f the cloc# control lines ere configured the same ay, couldnAt they accomplish the same function ithout the added cost of another control line +ontrolling and configuring the s itches on the SJ= control line is the tas# of the &S, and is second in importance only to control of the /;& system. 5he s itches of the SJ= control line are handled in the same manner as the apportioning s itches. 5he 'ASS signal and the 'AS/$ signal are used in conBunction ith a s itch /$ number on the /;& bus to select and set a s itch.

PSSP Systems ))
!.1.2 $pportioned Bus +tructures 5he apportioned bus structures are purposely divided into sections so as to create isolated groups of PSSPs. ?ach isolated group of PSSPS has a section of the apportioned bus structures that is isolated ith it. 5he apportioned bus structures are the primary address bus, the secondary address bus, the data bus, the bilateral control bus, and the au(iliary data;control bus. 5he bus structures that are not apportioned, the /;& bus and the global control bus, still interconnect the PSSP groupings that are other ise isolated from each other. ?ach isolated group of PSSPs is able to run a separate process, and all the separate processes run simultaneously ithin the system. Apportioning s itches are used along the length of the apportionable buses to create the divisions. +onsider the data bus, hich ithout any divisions, is a long, continuous bus consisting of a predetermined number of bit lines. Suppose all the PSSPs ere evenly spread along the length of the data bus, and the midpoint as chosen as the place to insert a simple s itch on each of the bit lines. ,lip all the s itches to the open position. 5he effect ould be to split the data bus into separate halves, ith no signal on one half interfering ith the signal on the other half. Since the PSSPs ere spread evenly along the length of the original bus, then they must have also been split into t o separate and e"ual groups hen the bus as divided, completely isolated from each other ith respect to the data bus. 5hat as a simplified e(ample of apportioning. /n a comple( system, it is much more involved, but the result is the same. Apportioning causes groups of PSSPs to become isolated from each other so that a process can be run ithout interfering ith, or receiving interference from, processes running in other groups of PSSPs. 'us structures divided into sections are called apportionable bus structures. All of the apportionable buses are divided into sections at the same logical points, so that the apportioned sections of each serves the same set of addresses. /n practice, the s itches for a logical

point on all the apportionable buses are activated at the same time by the same set of instructions. 5he address for the ban# of s itches at that logical point represents the same logical location on the bit lines of all the apportionable bus structures. 'y putting the address for that point onto the /;& bus and setting the 'AS/$ and 'ASS control lines to the desired states, the &S sets all the s itches at that logical point either open or closed at the same moment. 5he t o address buses, the primary address bus and the secondary address bus, have different purposes, but their basic structure is the same. 'oth are used to address the PSSPs, but they address them for different reasons, and ho the PSSPs react to being addressed by each one is different. 5he se"uencer puts an address on the primary address bus to cause full activation of a PSSP. ,ull activation means the entire PSSP is activated so that it can e(ecute the instruction held in its control section. 5he secondary address bus is used for partial activation of a PSSP. Partial activation refers to the processing section of a PSSP being activated to read or rite data. No processing is done in a partially activated PSSP. A close loo# at ho these t o buses attach to the PSSPs reveals differences. Assuming that speciali6ed PSSPs are used for the se"uencing function, only they output data to the primary address bus. Since the primary address bus is only used for full activation by the se"uencer, there is no need for other PSSPs to output an address to it. /n addition, the primary address bus is never used to transfer data to a processing section, so it is never used as an input bus to the PSSPs. 5he only connection the primary address bus has to a standard PSSP is hat is necessary to fully activate the addressed PSSP.

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5he secondary address bus needs to be able to partially activate the processing section of any standard PSSP ithin the system. Any standard PSSP can put an address onto the secondary address bus, but the speciali6ed PSSPs cannot. A standard PSSP ill put an address onto the secondary address bus in response a signal received from a fully activated PSSP that is adBacent to it, or in response to the control section of the PSSP of hich it is a part. 'oth address buses have the same number of bit lines, e"ual to the number of bit positions in the processing section of a PSSP. All PSSPs must be able to hold any address that is put onto one of the address buses. A situation common to both address buses, hich is not obvious until a person becomes familiar ith this type of system, is the effect that apportioning has upon the number of address lines used ithin an apportioned section. 5his as mentioned briefly earlier in the te(t, and should be mentioned again at this point because it represent a potential future resource for system designers or others trying to ma(imi6e the systemsA potential. @ithin any given system, there is a minimum and ma(imum si6e for apportionable sections. +urrently, the t o address buses need to be constructed ith enough bit lines to be able to address any PSSP ithin the system, or address the entire set of PSSPs in the ma(imum possible si6e of an apportioned section. ,or e(ample, if a system is designed to allo a ma(imum grouping of apportionable sections into one apportioned section of 6* =egs of PSSPs, then 26 address lines are needed. %et it be assumed, for this discussion, that 26 address lines are used to construct both address buses, and that these buses are fully available throughout the system. /f a 16.=eg section of PSSPs is then apportioned from the 6* =egs of PSSPs, t o of the address lines ill not be needed for addressing. 5hese t o unused address lines, combined ith changes in the address decoding circuits, can provide an alternate mode of addressing, hich can be designed to simultaneously activate a group of PSSPs ithin the apportioned section. 5here are other issues involved and it is not as simple as Bust described, but the potential is there to concurrently operate on a large "uantity of data ithin a contiguous group of PSSPs. %i#e the address buses, the data bus is also apportioned. /t has the same number of bit lines as the address buses, and it is only used for the transfer of program data from one processing section to another ithin an apportioned section. @ithin an apportioned section it cannot be used to move code into a control section or onto the /;& bus. /t is used to move addresses to the se"uencing PSSPs, but the se"uencing PSSPs cannot put data onto the data bus. 5he data bus can be used to input data into the A or ' inputs of the A%4s that are a part of the processing sections. 5he control section, in response to its opcode, directs hich input channel is used to receive input from the data bus. A PSSP activated by

the primary address bus can receive data from the data bus or the /;& bus, or put data onto these buses, but only one of these actions can occur ith any particular instruction. Similarly, a PSSP partially activated ith the secondary address bus can receive data from or put data onto the data bus, but cannot do both in the same instruction. 5he bilateral control bus is also apportioned. 5his bus is not really a bus in the ordinary sense of the ord. /t is actually a pair of control lines that go bet een every pair of logically adBacent PSSPs. ?very standard PSSP ill have t o bilateral control lines going to the PSSP that logically precedes it, and t o more that go to the PSSP that logically follo s it. 5hese control lines cause partial activation of the processing section of one of the PSSPs adBacent to the PSSP receiving full activation from the se"uencer. 5hese control lines are Bust short sections going bet een adBacent PSSPs, so their structure is very different from the other apportioned buses. Still, they need to be severed hen a section is apportioned. /f the first address in an apportioned section is address n, then the PSSP at address n has

PSSP Systems )3
t o bilateral control lines going to the PSSP at address n.1. 5hese lines need to be severed during apportioning of that section of PSSPs. 5he same action needs to be ta#en bet een address ( and address (M1, here address ( is the highest address in the apportioned section. 5echnically, these control lines are only used in a pair of PSSPs that carry an operand or address related to the instruction in the fully activated PSSP. 5he &S is not going to apportion a section of PSSPs to a process and then straddle an instruction across the border bet een t o apportioned sections. /f ade"uate safeguards are used in the &S soft are, these control lines do not need to be physically severed as the other apportioned buses are. 8o ever, hether the lines are physically apportioned or not, it is important to reali6e that logically they are part of the apportioned bus structures. 5he last apportioned bus is the au(iliary data;control bus. 5his bus is the very unli#e any other bus structure ithin the system. /t provides additional functions for t o other busesDthe data bus and the control bus. /t does not provide these functions simultaneously, ho ever, but at different times. At times, it serves as a speciali6ed data bus for the movement of code on a global scale. At other times, it serves as a local control bus for an active process. @hen it serves as a local control bus, its functions are local to the process in the apportioned section of hich it is a part. 5hroughout the te(t, numerous references have been made to the fact that code and data are #ept separate as much as possible. @hile code is a form of data at some levels of system operation, such as secondary storage, it is purely code once it has been put into the control section of a PSSP. @hen it is in the control section of a PSSP, it must be treated as code to maintain system security and stability. 5he au(iliary bus comes into use hen data changes status and becomes code. Anything held in the latches of the processing section of a PSSP is data, hile anything held in the opcode latches of the control section is code. 5he &S uses the au(iliary bus to facilitate the transition of data into code. /t uses the =&7+ instruction to move the data from a processing section over the au(iliary bus and into a control section. &nce it is in a control section, it is code and no longer data. @hile several buses can provide input and output in respect to the bit positions of the processing section, only one bus can do so ith respect to the bit positions of the control sectionDthe au(iliary bus. 5he number of bit lines in the au(iliary bus matches the number of bit positions in the control section of a PSSP. 4sing the =&7+ instruction, the &S can move data out of the processing section of a PSSP onto the au(iliary bus and into the opcode latches of a control section. $uring this process the au(iliary bus is used as a data bus. &nly hile a process is being loaded into an apportioned section of PSSPs is the au(iliary bus used for the movement of data. &nce the process has been loaded and is completely isolated ithin its apportioned section, it is ready to commence se"uencing on its o n. At this point, the au(iliary bus changes function from that of a data bus to that of the local control bus for that process. 5he au(iliary bus is connected to the input of every opcode latch, and once a process has begun se"uencing, it is connected as input into the decoding circuits as the local control bus. 5his is an important point in understanding the use of the au(iliary bus. $uring the loading of code into the control section, the decoder circuits are inactive, and input to the control section from the au(iliary bus is only to the opcode latches. &n the other hand, during the se"uencing of a process, the decoder

circuits of various PSSPs are active and controlling, or reacting to, the control signals of the au(iliary bus. @hile the decoder circuits are active it is not possible for the opcode latches to receive input from the au(iliary bus. As the local control bus for an actively se"uencing process, it handles control signals necessary for that process only. /t does not handle control signals that can affect other processes, but the global

90
control bus is still active ithin the process, providing inputs to the decoding circuits also. @ithin this design, eight signals are carried on the au(iliary bus hile it is used as a local control busDthree se"uencing control signals, three flag control signals, one signal for read; rite control, and one to provide control over the >&!? instruction. 5he three se"uencing control signals are SJ1, SJ2, and SJ-. 5here is one other se"uencing control signal, the SJ=, but it is a global signal carried on the global control bus. 5hese se"uencing control lines provide eight possible signal combinations, e(plained in the section dealing ith the se"uencing stac#. 5hese se"uencing signals, along ith all other signals of the local control bus, are isolated to the process of hich they are a part once the au(iliary bus has been apportioned, and the process has started se"uencing. 5he three flag control signals are carry, negative, and e"ual, the !, "!, and #! control lines. 5here is no status register for use ithin the process and each signal is set and held by the control section of the PSSP that last carried out an arithmetic or logical operation. 5he are t o e(ceptions to this. &ne is hen the process first starts and no flags have been set, and the other is hen a Bump instruction is e(ecuted that ill cause a reset of the flag involved. %i#e the se"uencing control lines, the flag control lines are local to the process and cannot affect any process outside the local apportioned section. 5he !;@ control line is used to carry the read or rite signal used in conBunction ith partial activation, or for enabling an &45 instruction. 5here is a global rite control line, the +@? control line, used in conBunction ith the =&7+ instruction and the secondary address bus, but it is limited to the =&7+ instruction that is only used by the &S. 5he !;@ control signal is local and can only affect the reading or riting of data in the processing section of a PSSP, never the control section. @henever the secondary address bus is used for instruction that indirectly refers to an operand, there is a signal put on the !;@ control line to cause appropriate action ithin the processing section of the PSSP addressed by the secondary address bus. @ith some instructions, it is necessary to partially activate t o other processing sections. /n these cases, one of the bilateral control lines provides partial activation to the processing section adBacent to the fully activated PSSP. At the same time the secondary address bus, in conBunction ith the !;@ control line, provides the partial activation to the other processing section. 5he last local control line implemented ith the au(iliary control bus is the /&%, hich is used to enable or disable a PSSP holding the >&!? instruction. !ecall that this instruction serves as the gate#eeper to the /;& bus for a process that needs to output data to the /;& bus. /t is a self.activating instruction that atches the /;& bus for an /;& routine identification number. 8o ever, there are times it is necessary to turn this instruction off to assure the orderly functioning of the local process. 5he /&%S instruction, used to set the /&% control line high or lo , causes the >&!? instruction to be active or not. 5he other gate#eeper instruction, >/!?, is controlled in another manner. !.1.3 Bilateral Control Bus ,our of the apportioned buses e(plained in the preceding section are actually divided into sections at discrete points here the divisions effectively cause groups of PSSPs to become isolated from other groupings of PSSPs. 5his allo s them to be assigned to a process that ill use them as an e(clusive resource. &ne other bus that as mentioned is the bilateral control bus and it also needs to be discontinuous bet een apportioned sections. /t has a very different structure than the other four

PSSP Systems 91
apportioned buses, but it is classified as an apportioned bus because it must also be made discontinuous at the same logical points. 5he bilateral control bus is not a bus structure as a bus is

normally thought of. /t is actually composed of t o connections bet een most logically adBacent PSSPs in the system. ?very standard PSSP has t o of these control lines bet een each logically adBacent PSSP, but se"uencing PSSPs only need one of these control lines going bet een them. 5he bilateral control bus is more accurately referred to as the bilateral control lines. ,urthermore, in most cases, these control lines are not noticeable during a casual inspection of a PSSP system. 'ecause they consist of t o lines going bet een logically adBacent PSSPs, most are short connections bet een the PSSPs ithin a circuit. 5hey ill not have the appearance of a bus ithin the circuit. ?ach standard PSSP

92
has t o connections going to each of its t o logically adBacent PSSPs. ,rom the point of vie of a particular PSSP, it has t o lines going to the PSSP preceding it and t o more going to the PSSP that follo s it. 5herefore, it has four bilateral control lines and each one serves a different function. 5hey must be made discontinuous here necessary, bet een apportioned sections, to help isolate the PSSPs in apportioned sections. As ill be presented in depth in the ne(t section, the apportioning s itches are addressable. 5hey re"uire input from the /;& bus and t o global control signals, to be set open or closed, as directed by the &S. 5he bilateral control lines are only needed by instructions that use t o PSSPs. 5he fully activated PSSP may need the address or operand in the processing section of an adBacent PSSP, and a bilateral control is used to partially activate that processing section. @ith the proper safeguards, the &S is not going to apportion a section of PSSPs for a process, and then straddle an instruction across the border bet een t o apportioned sections. 5herefore, it is not be necessary for these control lines to be physically severed as other apportioned buses are. 8o ever, logically they are discontinuous bet een apportioned sections and should be considered one of the apportioned buses. 5he s itches used for apportioning of the bilateral control bus could be the same type as those used on the other buses, but it is not a re"uirement. 5he s itches used for the bilateral control bus, as ell as those used for the SJ= control line, have less stringent re"uirements than the other apportioned buses. Apportioning s itches on most buses need to e(hibit very lo insertion loss and a high degree of isolation hen open. 'ilateral control lines are Bust short sections bet een adBacent PSSPs, so their s itching re"uirements are not so demanding. 5here is no reason that they cannot be solid.state s itches. 5he purpose of the bilateral control bus is to provide connections bet een the control section of the fully activated PSSP and the processing section of the t o adBacent PSSPs that may need partial activation. 5here are four of these control lines, t o to each adBacent PSSP. 5he connections enable the four follo ing functions0 5o partially activate the processing section of the PSSP that logically precedes the fully active PSSP to release its data onto the au(iliary data;control bus. 5his is necessary for the =&7+ instruction. 5his is the APA! control line. 5o partially activate the processing section of the PSSP that logically precedes the fully active PSSP to release its data onto the data bus. 5his is necessary for the =&75 instruction. 5his is the AP$! control line. 5o partially activate the processing section of the PSSP that logically follo s the fully activated PSSP to accept data from the data bus. 5his is necessary for the =&78 instruction. 5his is the A,$@ control line. 5o partially activate the processing section of the PSSP that logically follo s the fully activated PSSP to release its data onto the secondary address bus. 5his is necessary for instructions having an indirectly addressed operand. 5his is the A,A! control line. All four of these control signals are generated ithin the control section of the PSSP that is fully activated by the primary address bus. &nly one of these signals is generated for any particular instruction, and many instructions ill not re"uire them at all. 5hese control lines are different in the

PSSP Systems 9PSSPs used for se"uencing. @ith se"uencing PSSPs, only t o are needed, one to each adBacent PSSP. 5hey are called SS$! or SS$%, and they cause full activation of the adBacent PSSPs. ,or more details, refer to the section about se"uencing operations earlier in the te(t.

!.2 $pportioning 5he ability to apportion sections of PSSPs for the e(clusive use of a process is one of the t o essential aspects of a PSSP system. 5he other is the use of PSSPs for all processing, control, and storage functions needed ithin the system. 5he design of the PSSPs ma#es possible the full decentrali6ation and integration of all computing functions, hile the design of the bus system is hat ma#es apportioning possible. Apportioning is ho the system is split into sections that can be assigned to different processes, hich is hat gives the system the ability to run many processes simultaneously. 5 o aspects of apportioning need to be presented in detailDthe actual s itching mechanisms used, and ho the &S controls them. 5he first aspect is a hard are and design issue hile the second deals ith the soft are and ho it facilitates the apportioning process. 5ogether, the hard are and soft are are used to divide the PSSPs of the system into sections that can be assigned to individual processes, all of hich ill be able to run simultaneously. !.2.1 +&itches 5he s itches used for apportioning should be constructed using =?=S technology. /t can provide the high isolation and lo insertion loss needed. 5here must be no signal interference bet een the different sections of an apportioned bus, and there must not be signal degradation due to the use of s itches hen apportioned sections are combined to create larger apportioned sections. 8o ever, it is not necessary for all the s itches used for apportioning to be of the same type. 5he t o address buses, the data bus, and the au(iliary bus should be apportioned ith this type of s itch, but the SJ= control line and bilateral control lines have less demanding re"uirements. /ndividual s itches are used along the SJ= and bilateral control lines for apportioning, but each of the four maBor buses ill need ban#s of s itches that can sever all the bit lines on all four of the buses at the same time. 'ecause all four are severed in the same logical place, at the same moment, it ma#es sense to have the &S able to accomplish the action ith one set of commands. &ne set of commands carried out in the apportioning process ill cause all the s itches for a particular logical point to be set open or closed at the same time. ?ven though one s itch bloc# is used to sever all four of the buses ithin that s itch bloc#, a separate s itch is needed for each bit line on each of the four buses. ,or the sa#e of brevity such terms as s itch, s itches, and s itch.ban# are used loosely hen referring to the s itches used for apportioning. Apportioning ill re"uire the use of many s itches to sever the various bus lines. =any of these s itches are set to the same state at the same time, but this not al ays the case. 5here is the possibility of different groupings and combinations of s itches at different times during the life of the system. /t is also possible to use different addressing schemes to accomplish the various s itching needs ithin the system. 5herefore, it should be understood that any of the terms above might refer to a single s itch or group of s itches that need to be set to the same state at the same moment, and are collectively addressed ith a uni"ue address.

9*
5o set one s itch, or a s itch.ban#, the /;& bus and t o global control lines are needed. 5he /;& bus carries the address of the s itches, and the control lines carry the signals used to set the desired state of the s itches addressed. !efer to the diagram during the e(planation of ho a combination of s itches is prompted to ta#e an open or closed state. !emember, hether it is one s itch, or a group of s itches, the method is the same, and all the s itches affected ta#e the same state, at the same moment, and are reached ith the same address. At the bottom of the diagram are the four maBor buses to be divided, along ith the bilateral control bus. Above that, on the left side, are sho n the global control bus and the /;& bus. 5he /;& bus goes into an address decoder that ill decode the address for that particular s itch ban#. ,rom the global control bus come t o signals needed for s itch state control. 5he 'AS/$ signal is set high by the operating system to indicate to all apportioning s itches that the number on the /;& bus is a s itch

PSSP Systems 92
identification number. 5he &S sets the 'ASS signal high or lo to indicate the s itch should ta#e an

open or closed state. &ne signal, the 'AS/$ control signal, is combined ith the output from the address decoder in an AN$ gate. /f the address is true, and the 'AS/$ control line is true, then the output from the AN$ gate ill reflect the fact that the s itch has been selected to have its s itches set to open or close. 5his output from the AN$ gate ill put the s itch state latch into the mode to accept an input signal from the 'ASS control line so that it can accept the high or lo state. 8igh or lo on the 'ASS line reflects the open or closed state the s itches should ta#e. 5his signal is then input to the s itch driver circuits to cause all the s itches to either open or close as directed by the signal on the 'ASS control line. 5he s itch state latch ill hold this state until the ne(t time the s itch ban# is identified by the /;& bus and the signal on the 'AS/$ control line. !.2.2 +&itch Control <iven the hard are design described in the previous section, control of the apportioning s itches becomes a matter of soft are design. 5he operating system has the responsibility for control of the apportioning s itches ithin the system. As stated earlier, it is one of the most important tas#s of the &S, second only to the tas# of control over the /;& bus. @hile these t o processes, /;& bus control and apportioning, are both parts of the &S, they reside in different apportioned sections, and both run simultaneously ithin the system. Apportioning is secondary to control of the /;& system, but the process handling the apportioning ill need to ma#e e(tensive use of the /;& bus hen it apportions a section of PSSPs and loads a process. 'oth processes run separately because of the need for speed, especially ithin the /;& bus control process, but they both handle duties associated ith system control and are not truly independent of each other. Strictly spea#ing, apportioning is part of a much larger processDthat of loading a process for e(ecution. Apportioning is one of several things that the &S does hen it loads a process for e(ecution. /t re"uires e(tensive #no ledge of the s itches used for apportioning as ell as hich resources are already apportioned. After analy6ing the situation the &S ill set various apportioning s itches to achieve isolation of a group of PSSPs from the rest of the PSSPs in the system. An apportionable section is a group of PSSPs that e(ist in a logically linear group bet een t o apportioning s itch ban#s. 'y logically linear, / mean that the addresses form a continuous se"uence of addresses, regardless of ho they are physically arranged ithin the system. /n other ords, if bet een s itch ban# A and s itch ban# ' there are no other s itch ban#s, and addresses ( through y e(ist bet een these t o s itch ban#s, then addresses ( through y is an apportionable section of PSSPs. 5 o or more apportionable sections may be combined to form larger sections that can be apportioned as a group, if these sections are all logically contiguous to one another, so that hen they are combined, all the addresses form one continuous, logically linear group of addresses. 5his is necessary for a process to be able to reach any address ithin the apportioned section. A process cannot be given groups of PSSP addresses that are not contiguous. 5hat ould cause PSSPs that are physically isolated from each other to each have a portion of a code that belongs to the same process. 5he process ould fail because each part ould see# to address a PSSP in the other isolated section of the process. 8o ever, it should be #ept in mind, during program design, that a process may be divided into smaller processes that can run independently ithin the system and communicate ith each other via the /;& system.

96
5o apportion a section of PSSPs, the &S must ascertain ho much PSSP space is needed by the process. 5his information is found and retrieved from the process header hen the process is located in secondary storage. 5he &S ill have an array of information pertaining to all sections that can be apportioned. 5he &S maintains the s itch /$ numbers, the si6es of each section, the addresses involved, the use status of each section, and other pertinent information. 5he &S ill locate one or more free sections of PSSPs that meet the si6e re"uirements of the process. &nce the &S has decided hich apportionable section to give to the process, it ill determine hich s itch ban#s need to be set open to isolate the process. /f more than one section of PSSPs is used for a process, some s itch ban#s in these sections ill need to be set closed. &nce it has been determined hich s itches need to be set, it becomes a matter of ma#ing sure each of the s itch ban#s involved is set to the correct state at the

correct time. /t is necessary for the apportioning process to get the necessary time on the /;& bus to address the s itches involved hile the 'AS/$ and 'ASS lines are set to the correct state. 5he 'ASS control line is set ith the 'ASSS instruction, and the 'AS/$ control line is set ith the 'AS/S instruction. @hile the 'AS/$ control line is high, the /;& bus must not be used for any data other than the s itch address. 5herefore, the se"uence of instructions re"uires several cycles of /;& bus time to complete, during hich no other process is allo ed to input to the /;& bus. 5he 'AS/S and 'ASSS instructions must be part of the output routine that puts the s itch address onto the bus. 5here must be no possibility that other processes ill put data onto the bus that could be confused ith the address of a s itch hile the 'AS/$ line is in the high state. A short e(ample of the code used for setting the s itches as presented earlier in the te(t hen the global control instructions ere e(plained. !.3 ,perating +ystem ?(tensive mention has been already been made of ho the operating system in a PSSP system is different from the operating system in a traditional system. $espite the differences, the soft are still supports and complements the system hard are in both systems. ?ver since electronic computers came into e(istence, operating systems have evolved to complement the evolving capabilities of systems hard are. 5he design of a PSSP system is so radically different that it re"uires a total rethin#ing of hat an operating system is and hat its functions should be. /f a traditional system is booted and left at rest, ith only the system processes running, the &S ill continue to use a substantial portion of the systemAs resources. As more programs are loaded, the systemAs share of the resources decreases as it shares resources ith other processes. 5he &S is still in control as it is forced to use system resources to e(ecute one or more non.system processes. A close loo# ill reveal that the situation is actually much orse. ?very process that gets its portion of the systemAs resources does so only ith the active participation of the system itself. ,or e(ample, if a process accepts input or creates output, then it does so only via the use of interrupts, hich re"uire the active participation of the &S. ,urthermore, every instruction of a non.system process is e(ecuted ith the &S firmly in control of the +P4 being used for the instruction. @hile the user interacts ith the process, the process interacts ith the &S. 5he process canAt function ithout the &S. /n a ay, it is the &S that is actually doing everything. @e thin# of it as a process doing the or# during its time slot, but the process actually tells the &S hat it ants done, and then the &S does it.

PSSP Systems 9)
/n a PSSP.based system, each process is made to function autonomously ithin its isolated section of PSSPs. ?very process, including every system process, is functioning at the same time, independently of each other. +P4 time is not one of the allocated resources of a PSSP.based system. 5here are only t o resources in PSSP systems that need allocationDthe PSSP space, and time to use the /;& bus. 5he allocation of PSSP space has similarities to the allocation of memory in traditional systems, and the allocation of /;& bus time has similarities to the allocation of +P4 time. 8o ever, despite the similarities, the systems are radically different in ho they accomplish the or#load. PSSP space allocation is the apportioning process, and hile there are similarities bet een it and ho memory is allocated in traditional systems, there are some big differences. Apportioning is the permanent allocation of PSSP resources to a process. &nce an apportioned section of PSSPs has been assigned to a process, it becomes the e(clusive resource of the process for as long as that process is running in the system. 5here is no system of virtual PSSPs or sharing of PSSPs bet een processes. ,urthermore, memory is a static obBect used solely for the storage of data hile a section of PSSPs is an actively functioning entity that runs a process ithout help from the system. Another difference is ho memory is protected. 5raditional systems do little to protect memory. 5hey do generate error traps or e(ceptions to protect system operations and certain memory areas. Such methods often result in system failure and reboot. 5his cannot occur ithin a PSSP system. =emory protection is an inherent property of a PSSP system. /solated processes cannot reach into other processes. Process isolation ithin an apportioned section of PSSPs eliminates this potential for system failure even though a process may still fail. 'ecause all processes are isolated from each other,

they are protected from the failure of any one of them. All processes are allocated a share of time for outputting to the /;& bus, similar to the sharing of +P4 time ithin a traditional system, but again, there are some crucial differences. /n sharing a +P4, each process has a length of time in hich it is the primary process ithin the system, and all other processes ait for their turn. /n a PSSP system, it is rare that a process ill sit and ait for another process to ma#e use of the /;& bus. 4nless a process has been poorly designed, the only time it sits and aits is hen the &S needs to borro its buses for loading a process. A process must ait its turn to use the /;& bus, but it can process ithin its apportioned section hile it aits. /n sharing the /;& bus, each process is given a time slot in hich to put data onto the /;& bus. ?ach process has a share of time to use the /;& bus for output, even if it doesnAt ma#e use of the time. /f it fails to use its time slot for output to the /;& bus, it may receive less time in the future, but it ill still receive some time, no matter hat. /t uses its /;& gate#eepers to atch for opportunities to use the bus, but it is not held bac# from e(ecuting code. ?ffective use of the resources devoted to the process ithin such a system re"uires a ne ay of problem solving and algorithm implementation. 5ime.sharing only pertains to the output of data onto the /;& bus. 5his relates to the need to share data ith any other process or an actual /;& device, not to carrying out the e(ecution of instructions. ?(cept as noted above, all processes can e(ecute instructions continuously ithout interruption. /nput is available to the process as it is output by another process, and data for output can go into buffers to be put it onto the /;& bus as opportunities arise. !.3.1 Control o' the Bus +tructures /tAs time to ta#e a closer loo# at hat the &S is actually doing ithin this system. /t has been briefly mentioned already, but more focus has been put on individual tas#s that the &S must perform.

99
5he broadest possible vie of the &S reveals that these functions can all be grouped together as the tas# of controlling the bus structures of the system. 5his is hat the &S devotes most of its time to accomplishing. A traditional system usually has four basic bus structuresDthe address, data, control, and /;& buses. 5here are some variations, but the basic structures remain. 5hey tend to be passive devices that serve to connect the memory and /;& to the +P4. 5he buses in a PSSP system are dynamic and versatile. 5he configuration of the apportioned buses ill change many times during normal operation as numerous processes come to function simultaneously ithin the system. =ean hile, the nonapportioned buses are controlling the system and providing a means of communication for all processes via the /;& bus. Several bus structures in addition to the basic four are found in a PSSP system. /t ill have t o different address buses, a data bus, and an /;& bus that is as e(tensive as any other bus in the system. 5here is also a control bus for global control signals, and a dual.purpose bus that serves different functions at different times. ,inally, there is a set of control lines, the bilateral control bus, hich carries control signals bet een adBacent PSSPs. ,ive of these bus structures are apportioned, a process controlled by the &S. 5he si(th, the /;& bus, is used in conBunction ith a process that maintains rigid control over its use. ,inally, the &S uses a global control bus to control various parts of the system. All maBor system processes involve some aspect of control over the bus structures in the system. +ollectively these system processes are the &S and their purpose is to control the bus structures that unite and enable all aspects of the system. 5he apportioning process is the second maBor tas# the &S must perform. 5he &S has control over the s itches used for dividing the apportioned buses. 'y controlling the s itches, the &S can control the allocation of system resources. !egardless of ho many divisions are made to the apportionable bus structures, or ho many processes are given a section of the bus structures as an e(clusive resource, the &S still has ultimate control over the entire set of apportioned bus structures. &nly the &S can set the apportioning s itches, set the SJ= control signal that enables or disables se"uencing ithin a process, and #eep the information pertaining to their configuration. Any control that a process has over an apportioned section of buses is permitted by the &S and may be revo#ed at any time.

@hen the &S assigns an apportioned section to a process it also gives the process the right to slices of time in hich the process may output to the /;& bus. 5his is done for every process, including &S processes. ?very process, hen it is loaded into an apportioned section, must specify hat data it see#s to put onto the /;& bus. 5he &S must satisfy the needs of the process as much as possible. 5he &S even inserts the needed code into the process to insure that the process can only output to the /;& bus hen, and to the degree, specified by the &S. As ith the apportioning of the buses, the &S is in control, and this control is maintained throughout system operation. 5he apportioning process, as ell as the use of the /;& bus, is controlled by the &S through elements of the systemAs design, hich includes the control lines of the global control bus. Several control lines, the 'ASS, 'AS/$, and /&!% control lines, carry the signals that are controlled by the &S to effect the apportioning process and control over the /;& bus. 5hese lines, as ell as their control instructions, are privileged assets belonging to the &S for the purpose of e(erting its control over the system bus structures.

PSSP Systems 93
!.3.2 Booting) 7xecution) and Termination As in a traditional system, the purpose of booting in a PSSP system is to get the operating system up and running, so that the system is ready to e(ecute other processes. /t ma#es use of the '/&S to start loading the &S, initiali6ing system parameters, and chec#ing the viability of various system components. @hile the t o types of systems share common needs in booting, they differ in ho the process is accomplished. A PSSP system has at least three types of PSSPs, and a fourth if a speciali6ed PSSP is used for the /;& gate#eeper function. &ne type is the standard PSSP, most common ithin the system. Another is used for se"uencing. 5he third type of PSSP is li#e the standard type e(cept that one or both of the PSSP sections need to be read.only, so that data and code are retained hen the po er is removed. All three are used for the boot process, and they are all resident on the PSSP boot chip used for the initial boot process. 5he chip is not a memory chip, and there is no +P4, so there is no boot !&=. 5he three types of PSSPs are mi(ed on the chip according to the needs of the boot process. 5he integration and decentrali6ation of the computing functions is reflected in the needs of the system during the boot process. 5he actual implementation of the code is "uite a bit different. 8o ever, the basic need is still to establish the '/&S to be able to retrieve data from the secondary storage and continue building the &S. ,or e(ample, one of the first instructions to be e(ecuted is a =&75 instruction that ill be resident on a read.only standard PSSP activated hen po er is first applied. 5his instruction ill move an address to the se"uencer so that it can begin to se"uence other PSSPs that are part of the boot process. /nitial conditions see po er applied only to the section of PSSPs needed to load the &S. 5here is no need for the rest of the system to have po er since there are no other processes yet. A uni"ue benefit of this system is that po er does not need to be applied to unused sections of PSSPs until they are needed for a process. 8o ever, the bus structures are active from po er up, and the /;& bus is the first that needs to be brought under control as the '/&S is implemented. &nce the '/&S is implemented, the rest of the &S can be retrieved from secondary storage. $ata structures are needed for process control and apportioning, but such structures are common to all systems and differ only in the purpose they serve and the information they contain. Apportioning also begins during the boot process, as various &S processes need to reside in different apportioned sections to provide ma(imum speed and efficiency. !.3.3 I6, +ystem 5he /;& system is the central part of a PSSP system and its design involves many comple( issues. $esign choices for the /;& system ill affect most aspects of the system and its performance. 5he /;& system presented ithin this boo# is a simplified version of hat a real orld version ould be. Leeping it simple ill help the reader to easily grasp the fundamentals. /n a traditional system, the /;& is handled by system interrupts that re"uire the attention of the operating system. /n a PSSP system, each process must see# access from the &S to output data onto the

/;& bus. &nce access is granted, the process ill be notified of its turn to broadcast data onto the /;& bus, and any other process see#ing the data is free to copy it from the bus. 5he difference bet een the t o methods is enormous. /n a traditional system, a process ill send an interrupt to the system, and

30
then the system "ueries the device, or process, for the data. /n a PSSP system, a process ta#es the data off the /;& bus. 5he other device, or process, has already arranged ith the &S to broadcast the data onto the bus at regular intervals. /n a PSSP system, things do not come to a stop hile input or output is handled, but a process does not al ays have immediate access to the desired data. /;& is actually the core of a PSSP system, and it is constant process during system operation. /t is almost as if the system is the /;& bus and /;& soft are, ith the apportioned sections behaving as peripherals attached to the /;& bus. 5he operation of the /;& bus is so critical that the system cannot e(ist ithout it. All processes in apportioned sections become meaningless ithout the /;& bus that interconnects them. 5he /;& system ill be vie ed from three perspectives in this section. 5he systems vie of the /;& system presents an overall vie of its purpose and importance. ,rom the point of vie of the &S, the /;& is its most important tas#. ,or non.system processes, the /;& is the means by hich the process can interact ith every other process. @hen seen from the perspective of the system, the /;& system is its most important element. 5he other main processes of the &S, apportioning and loading, need the /;& system to do their Bob. So does every other process ithin the system. 5hey all become meaningless ithout a functioning /;& system. !egardless of hat any process may accomplish ithin its o n apportioned section, they cannot share the result ith another entity ithout the /;& system. 5hey cannot interact ith other processes or the outside orld ithout a functioning /;& system. 5he purpose and function of the /;& system is to be the conduit for inter.process communications ithin the system. 5his point cannot be overemphasi6ed. /n a traditional system, multiple processes reside in their assigned memory space, and each process gets a turn to use the +P4. 5hough there are protected areas of memory, for the most part, each process can access memory throughout the entire memory space. All needed data is accessible to other processes through memory sharing or data structures accessible through the &S. /n a PSSP system, this is not possible. ?ach process is completely isolated ithin its o n space and cannot be accessed by another process. 'ecause of this isolation, every process needs a method of e(changing data or messages ith other processes, and it is here that the /;& system plays a crucial role, all ithout the use of system interrupts. 5he /;& system is much more e(tensive, as it must be available to every process and be used for every bit of data e(changed bet een isolated processes. 5here are no e(ceptions. /f data is shared bet een isolated processes, the data must transit the /;& bus. 5he number of PSSP sections that can be apportioned limits the number of processes that a PSSP system can accommodate at any one time. 5he speed at hich these processes can run simultaneously depends, to a large degree, on ho capable the /;& system is at #eeping up ith inter.process communications. Assuming there is sufficient PSSP space, the ability of the /;& system to #eep up ith the communications load becomes the limiting factor in system throughput. /n a traditional system, this is not a problem. Processes run one at a time, so there can only be one process ma#ing use of the /;& system at any particular time. /n a PSSP system, all of these processes are running at the same time, each in its o n apportioned space, and processes may actually ait for opportunities to put data onto the /;& bus. 5he /;& system provides the means of communication bet een isolated processes. 5he isolation provides a substantial degree of system security and stability hile the /;& system enables interaction bet een processes that are isolated. At the same time, it provides a central point at hich to aim attac#s that see# to compromise the system or its processes. 5his possibility is hat drives many design choices ithin the /;& system. =any features have been mentioned already, and they ill be

PSSP Systems 31
vie ed collectively in the last section of this boo#, along ith all of the other design elements that enhance system security and stability. 8ere, it only needs be understood that many of the design

features of the /;& system e(ist for this purpose. /t is li#ely that, as future developments ithin the system occur, they ill most li#ely occur in the /;& system. 5he central role of the /;& system ma#es it the most li#ely candidate for improvements to enhance system throughput, security, and stability. 5he &S sees the /;& as its most important function. /ts other processes are secondary in importance to the /;& subsystem. /n many respects, the /;& system is the &S, as most of the resources used by the operating system are devoted to the successful functioning of the /;& system. /n a traditional system, +P4 time is shared among the many processes resident ithin the system. /n a PSSP system it is time for use of the /;& bus that is shared. ?ach process is given time slots to use the bus and then told hen they may use it. ?fficient use of the /;& bus is crucial to system performance and throughput. 5he principle tas# of the &S is to control use of the /;& bus and maintain efficiency in its use. 5o achieve this goal, many parts of the system are designed to facilitate the use of the /;& bus. 5he main hard are component of the /;& system, the /;& bus, reaches into every corner of the system. All standard PSSPs in the system are capable of putting data onto the /;& bus or receiving data from it. /t is also connected to every set of apportioning s itches as the s itches are addressed via the bus. 5he only parts of the system that do not connect to the /;& bus are the se"uencing PSSPs and various support components such as the po er supply and cloc#s. Also, for obvious reasons, the /;& bus has no connections to other buses ithin the system. 5he /;& bus is one of the t o buses that are not apportioned. 5hese t o buses provide the only physical lin# bet een all the processes in the system, hich are other ise completely isolated from each other. @hile the global control bus serves to transmit global control signals to all processes ithin the system, the /;& bus serves as the communication lin# bet een all of them. /ntra.process communication cannot occur on the /;& bus, nor is there is a need for such a service, but inter.process communication can only occur via the /;& bus. Aside from the /;& bus, the only other hard are items dedicated to the /;& system are a global control line, a local control line, and the speciali6ed PSSPs dedicated to /;& gate#eeper functions ithin each apportionable section. @ithin the global control bus there is the /&! control line used to signal all processes that an /;& routine /$ number is on the /;& bus. 5he au(iliary data;control bus also has a line that serves an /;& function. 5he /&% control line is used to enable or disable a PSSP holding the >&!? instruction. 5his instruction goes in an /;& gate#eeper PSSP that atches the /;& bus for an /;& routine /$ number in conBunction ith a signal on the /&! control line. 5his serves to signal the process that it is permitted to output data to the /;& bus. Another local control line, the !;@ line, is not dedicated to /;& functions, but it is used ith the &45 instruction to control the output of data to the /;& bus. 5he soft are components of the /;& system are designed to use the /;& hard are as efficiently as possible hile maintaining system security and stability. =any elements of the /;& system soft are are blended together to achieve the desired result. As ith most soft are, nothing is ritten in stone, and is revised and molded to fit specific systems or goals. 5he most essential soft are elements that are part of the /;& system are the protocol, the sub.process that constructs each /;& bus. A rudimentary understanding of these soft are elements is sufficient to see ho the /;& system facilitates inter.process communication hile maintaining system security and stability. !emember that this discussion presents a very simplified method of handling the /;& system to facilitate an

32
overall vie and understanding. A real life system is much more comple(, and careful consideration of this /;& system design ill reveal a host of details that are lac#ing. 5he protocol used for passing data or messages on the /;& bus is not complicated, but it is an essential element of the system. &ne ay to vie the /;& system is as a net or# bus used to connect all the processes ithin the system. %i#e all net or#s, a common language for the flo of data is needed. ,or this system design, a simple protocol ill be used as a ay of organi6ing the flo of data over the /;& bus here all data movement is tightly controlled. @hile a process may interrupt its program flo for /;&, interrupts do not occur ithin the /;& system, or any other part of the &S, at anyroutine, and the three sub.processes of the /;& system that are needed to achieve efficient use of the

time. $ata on the /;& bus flo s as a series of parallel bits. 5he number of bit lines used ill be referred to as a data unit. A process that puts data onto the /;& bus ill output a series of data units referred to as a pac#et. ?ach pac#et of data units is of a predetermined si6e, and needs an identifier as it begins. 5he identifier is the /;& routine /$ number. /t is follo ed by a null unit of data. 5hen comes another unit of null data or the /$ number of the process to hich the pac#et is addressed. 5he data that is being broadcast onto the bus follo s last. Please see the accompanying diagram for a visual representation of a pac#et. 5he only e(ception to this is hat the /;& system does to meter out the use of the bus or to facilitate &S functions. 5he /;& system puts the /&! number onto the /;& bus in conBunction ith the correct signal on the /&! control line and ill use a speciali6ed pac#et to do so. 'efore putting data onto the /;& bus, an output routine must detect its identifying number on the /;& bus in conBunction ith the correct signal on the /&! control line. 5his number is al ays the first data unit of the pac#et and it is put onto the bus by the /;& system. @hether more data units are in the pac#et is up to the process that has been given permission to output. !egardless of hether the process responds to its opportunity to output data, the &S ill still let the time allotment for the pac#et occur. /f the process chooses not to output data, the data units ill end up being null for each data unit of the pac#et e(cept the first one. !ecall that +%L2 beats once for every t o beats of +%L1. +%L2 is for the se"uencer and instruction timing, hile +%L1 is for sub.operations ithin an instruction. @hen the /;& routine /$ number is detected, it ill occur on the first of t o +%L1 cycles. 5he first cycle is hen the >&!? or >/!? detects the /;& routine /$ number on the bus in conBunction ith the /&! signal. /t also sets the three se"uence control lines to the correct state for notifying the se"uencer that it should finish its current instruction and handle a Bump from an /;& gate#eeper. &ne more cycle of +%L1 is needed to finish the instruction in the process of e(ecution by the se"uencer. &n the ne(t t o cycles of +%L1, the Bump for the >&!? or >/!? instruction is e(ecuted. 5his involves the se"uencer moving for ard one PSSP ithin the PSSP stac# and accepting an address for the /;& routine from the gate#eeper instruction. 5he first unit of data output by the /;& routine ill come on the ne(t t o cycles of +%L1. 5his data unit is designated for the process /$ number of the addressee, if there is one. ,ollo ing that ill be the actual data, hich may be any length of data units, up to the ma(imum allo ed by the system, so long as it is of a predetermined si6e.

PSSP Systems 35he first item is the /;& routine /$ number of the process outputting to the /;& bus. 5his is put onto the bus by the /;& system hile it has the /&! control line high. /t signals that the specified output routine has permission to put data onto the bus. ,ollo ing the identifier is one unused cycle of +%L2, during hich the Bump to the output subroutine is accomplished by the se"uencer. 5hen comes one data unit for the /;& routine /$ number of the process to hich the data pac#et is being sent. 5his data is not al ays needed, but the time cycle allotted to it must remain imbedded in the data pac#et. ,ollo ing that are the data units. 5here are a predetermined number of data units to every possible output routine ithin the system. 5here is no variance possible ith this re"uirement. System security and stability re"uirements do not allo a process to put data onto the /;& bus in an uncontrolled manner. All output is thought out in advance and provided for during the loading of a process. 5he &S does this because it is the only process ith the authority to move or change code. 5he code se"uences used for the output of data onto the /;& bus are actually constructed by the &S during process loading. 5he &S is the only process ith all the necessary information to do this. ?ven though the output formats for many devices are standardi6ed, it is not desirable to have a compiler handle the code for the /;& routines used in this system. As an e(ample, the handling process for a mouse installed by the &S provides information about its output format to the &S as part of the compiled code. @ith this information, the &S then constructs the necessary output code for that process. 5hen, information about the output routine passes to the /;& system so that it can ma#e the necessary allo ances for the mouse output. /n constructing the output code for the process, the &S ill also insure that the only possible output from that process ill be as

it as designed upon loading. 5he process is not allo ed to handle code, so no changes can be made once it has been loaded. &ther safeguards in the design prevent a process from putting data onto the /;& bus until it is given permission to do so. 5he re"uirement that the &S construct the output routines provides it ith complete #no ledge of the /;& re"uirements needed by every process. =ost of this information is

3*
passed on to the /;& system so it can be used to analy6e and provide the output time slots needed by each process. 5he &S also needs the information to construct the input routines other processes may need to receive that output as their input. @hile any process is free to receive input from the /;& bus, to do so re"uires it to have the necessary code to receive the full data pac#et. 5he &S #eeps this information, so it assumes the responsibility of constructing each input routine needed by every process. 5he input routine for each output pac#et is almost a mirror image of the output routine e(cept that a process needs to use the >/!? instruction for input. ?ach process inputting or receiving the data ill have its o n copy of the input routine ith different addresses. 5he si6es of all output routines used by all the processes are passed to the /;& system as each process is loaded into its apportioned section. /t remains for the /;& system to use this information to control the traffic on the bus as efficiently as possible. 5o accomplish this tas#, it has several subprocesses, each ith its o n function. 5he three most important processes are controlling, allocation, and statistics. 5hey all reside in different apportioned sections, so they run independently of each other, but there is a considerable amount of information passed bet een them over the /;& bus. 5he controller notifies each process in the system hen it may output to the bus. /t has a "ueue of /;& routine /$ numbers ith ho many cycles are needed by each process. A process may have several output routines, and each one must be identifiable. 5he controller process does not analy6e or #eep trac# of bus use. /t acts li#e a traffic light. /t ma#es the /&! control line high, puts an /$ number on the bus, and then aits the re"uired number of cycles before doing it again ith the ne(t process in the "ueue. /n the bac#ground, it updates its "ueue ith data received from the allocation process. 5he allocation process sends it information from hich to build or modify the "ueue. 5he allocation process has an /;& routine /$ for its output routine used to send data to the controller process. 5he allocation process does the analy6ing and ma#es necessary decisions concerning bus use. /t receives data from the statistics process about hether a process used the bus during its assigned turn. /f a process doesnAt use its turn it may receive less time to use the bus hile some other processes get more time. 5he allocation process generates the data sent to the controllerAs "ueue. 5his allocation process receives input from the &S hen there is a ne process, or hen a process terminates and no longer needs to use the bus. 5here also may be some prioriti6ing of output processes. 5he statistics process atches ho the bus is used. /t #eeps trac# of hich processes do not use the /;& bus. 5his information is passed to the allocation process to be used in analy6ing hich process should receive less time on the bus. /t notes an /;& routine /$ in conBunction ith the /&! line being high, and then ascertains hether the process put a data pac#et on the bus after its /$ number. /n the three sub.processes of the /;& system, the controller is the one that must maintain its speed, but the allocation process has the most comple( tas#. Several variables are used in its analyses. 5he priorities of any particular process and other considerations must be given eight ithin the analyses. A process sees the /;& as its lin# to the outside. At first glance, it might seem no better off than in a traditional system. 8o ever, a closer loo# reveals that it is substantially better off in a PSSP system. /t has its o n set of resources and is free to run continuously ithin its apportioned section. /t is also free to receive and ma#e use of any data on the /;& bus. /t needs to ait for input to occur, but that is a less onerous re"uirement than in a traditional system. 5hough the aiting period may be small, it must ait for the process it ants data from to be given permission to output data to the bus. +ontrast this ith a traditional system in hich input is implemented ith an interrupt that "ueries a process to get input, but only after it has received its turn to use the +P4. /n a PSSP system every process must ait

its turn to output data to the bus. 5he &S never "ueries a process to output data onto the bus. 5o do so

PSSP Systems 32
ould re"uire it to ait its turn to send a message to the process from hich it needs data. 5hen it ould need to ait for that process to receive permission to output the data. 5o ma#e it simple for a process, the &S has set up all the input and output routines that the process needs in the apportioned space belonging to the process, Bust as they are needed. 5he programmer specified hat input as needed and the output needs of the process. 5he process needs to tell the &S e(actly hat it may need to output and ho many data units are needed, ith a minimum or ma(imum possible time interval bet een each output. @ith this and other information the &S assembles all the code necessary for the /;& routines needed by the process. /ts or# is based on information obtained from the programmer of the process and from having constructed all other /;& routines ithin the system. &nce the process begins se"uencing, it can have input at any time by putting the /$ number of the process it ants to receive input from into the processing section of the PSSP holding the >/!? instruction. 5his instruction is al ays loo#ing for input from the /;& routine identified by the number in its processing section. /f that number is a valid /;& routine /$ number, the >/!? instruction ill eventually detect it in conBunction ith the /&! control line being high. @hile the process aits for input, it can se"uence other code. @hen the sought input is detected, a Bump ill occur to service the input. /f the process does not ant input to occur, it ill put a dummy /;& routine /$ number into the processing section of the >/!? instruction. The 'ollo&ing e%ents need to occur 'or input 'rom the I6, usE @hen the process is loaded, the &S constructs and inserts the input routines based on information obtained from the process being loaded. ,or each input routine, the process is given the input routine code, the /;& routine /$ number, and the starting address. /t also receives the starting address and length of the input buffer. &nly one >/!? instruction is needed for each process. All input routines can use the same >/!? instruction. @hen input is desired from a particular input routine, its /$ number must be put into the processing section of the PSSP ith the >/!? instruction after the starting address of the routine has been put in the processing section of the adBacent PSSP. 5he >/!? instruction ill then start atching for the input to occur, and the process can continue ith other instructions hile aiting for the desired input. !egardless of hat the main process is doing, the >/!? instruction ill atch for the /$ number of the input routine to occur in conBunction ith a signal on the /&! control line. @hen this occurs, the >/!? instruction signals the se"uencer to finish its current instruction and ma#e a Bump to the routine to service the input. 5he address of this routine is in the processing section of the PSSP follo ing the PSSP ith the >/!? instruction. 5he se"uencer then e(ecutes the input routine constructed by the &S. At the end of the routine is an instruction that puts a dummy input routine /$ number into the processing section of the PSSP ith the >/!? instruction to deactivate it. 5he last instruction of the input routine is the !?5 instruction. &utput is not much more complicated than input. A fe of the steps are different, but the process is straightfor ard. An important additional step involves the use of the /&% control line used to enable or disable the >&!? instruction, giving more control over hen it ill output data to the /;& bus. Another difference bet een input and output is that the >&!? instructionAs processing section,

and the processing section of the follo ing PSSP, is in read.only mode. 5his is done to prevent the improper use of the /;& bus. 'y having the output routine /$ number that is in the PSSP ith the >&!? instruction as read.only, a process cannot falsely claim to be another process and interfere ith the system. ,or the same reason, the address of the output service routine held in the follo ing PSSP must not be allo ed to change. 'ecause the processing sections used for the >&!? instruction are readonly, it is necessary for a separate >&!? instruction to e(ist for each output routine ithin a process. 5he process ill set up the data to be output by putting it into the processing sections of the PSSPs used for &45 instructions. 5his is done before enabling the >&!? instruction by setting the /&% control line high ith the /&%S instruction. &nce the >&!? instruction is enabled, it ill ait for its output routine /$ number to occur in conBunction ith the signal on the /&! control line. @hen the conditions are met, a Bump ill be initiated to the output service routine. @hen the service routine is finished se"uencing, the se"uencer ill return to here it left off before the interruption to service the output. The 'ollo&ing e%ents need to occur 'or output to the I6, usE @hen the process is loaded into an apportioned section, the &S determines the output needs of the process. /t ill construct the output routines for the process and pass the number of cloc# cycles needed, along ith the output routine /$ number of the process, to the /;& system, hich allocates time for the output. 5he &S ill give the code for the output routine, the /;& routine /$ number, and the starting address of the output routine to the process, as ell as the starting address and length of the output buffer. @hen the process is loaded, each possible output routine is given a PSSP ith the >&!? instruction in the control section and the /;& routine /$ number in its processing section. ?ach output routine has a start address installed in the processing section of the PSSP follo ing the PSSP ith the >&!? instruction. 5o enable output, the process must set the /&% control line high ith the /&%S instruction. 5his causes the >&!? instruction to self.activate. /t starts atching the data on the /;& bus and the signal on the /&! control line. @hen the /&! control line is high, it compares the data on the /;& bus to the output routine /$ number it holds in its processing section. @hen the /&! control line is high and the data on the /;& bus matches the output routine /$ number held in its processing section, Bump conditions are met. At this time, it sets the three se"uence control lines to the correct state, hich causes the se"uencer to finish its current instruction and ma#e a Bump to the output routine to put the data onto the /;& bus. 5he >&!? instruction also sets and holds the !;@ control line to the correct state, enabling the &45 instructions to put data onto the /;& bus. 5he output routine is composed of a series of &45 instructions. /t may also have a N&P instruction at its beginning. At the end of the

PSSP Systems 3)
routine is the ?&45, /&%S, and !?5 instructions. 5he ?&45 instruction causes the !;@ control line to go bac# to normal, hile the /&%S instruction sets the /&% control line lo to disable the >&!? instruction. ,inally, the !?5 instruction causes the se"uencing stac# to return to here it as before the Bump to the output routine occurred. 5his is a very simplified /;& setup, but it illustrates the rudiments of /;& in a system built around the use of PSSPs. /t allo s all processes to communicate ith other processes hile providing necessary safeguards for the system. 5here are many enhancements possible ithin this design. +onsidering the importance of the /;& system ithin a PSSP system it becomes obvious that the above design is too simple and a much more e(tensive set of services is re"uired for a real orld /;& system. !.3.! +ecurity and +ta ility Security and stability are t o aspects of the problem of un anted code. @hether the code is intentionally malicious, or the results of bad programming, the issues are the same. 8o can un anted code be #ept out of the systemE @hat can be done to mitigate the damageE @hat can be done to ma#e the system more secureE 5hese are the issues that need to be considered in any design. 5he design of a PSSP system goes a long ay to solving many of the problems, but it does not provide a total solution.

5he same features of a PSSP system that permit concurrent processes also provide a great deal of security and stability ithin the system. 5he three principle ays this problem is dealt ith involve the isolation each process receives ithin the system, ho all interaction bet een processes is limited to the flo of data via the /;& bus, and ho the code is handled ithin the system. 5he complete integration and decentrali6ation of system resources facilitates the apportioning of resources amongst the various processes ithin the system. 'y apportioning the resources of the system, the &S is able to isolate a process ithout being concerned that the process needs some other resource outside its allocated section. 5his forced isolation is complete for each process e(cept the system process. 5he &S is in its o n isolated section, but it retains the potential to reach into any part of the system, so its isolation e(ists only to the e(tent necessary for the benefit of the system. 5his isolation bet een processes includes all potential access via the address buses, data bus, au(iliary data;control bus, and the bilateral control lines. 5he global control bus is not included, nor is the /;& bus. /f, for some reason, a process did try to access a PSSP that as not a part of its apportioned section, an error ould occur, resulting in failure of the process. 8o ever, there is no possibility of the failure directly affecting the system, unless it occurs ithin the &S process. 5he design includes the /;& bus as the only means for communication bet een all processes internal and e(ternal to the system. All input devices, output devices, and processes resident in the system are obligated to use the /;& bus hen they need to communicate ith another device or process. /n many cases, this communication ta#es the form of data broadcast on the /;& bus and freely available to any process, but it can also be data specifically directed at another process. /n all cases, this transmission of data onto the /;& bus is planned in advance and tightly controlled by the &S. 5he &S ta#es into account the need of each process to e(change data ith other processes as the process is loaded into its apportioned section. An effort is made by the &S to provide the time, the input and output routines, and the control needed to ensure ma(imum /;& capability for the process, hile maintaining system integrity. All processes must e(change data ith other processes, or they

39
lose their meaning as a process, but all processes also need a fully functioning and secure system. Satisfying both of these needs is the Bob of the &S. 5he &S constructs the output routines for each process using the guidelines given via the code for the process. 5his means that the compiler generated the data necessary for the &S to construct the output routines needed by the process but only the &S can generate the code used to output data onto the /;& bus. 5his insures that the /;& system has full control over the code and is able to construct the input routine that is the reciprocal of each output routine. /n this manner, there is no possibility for uncontrolled output of data onto the /;& bus. ?ach output process developed by the &S is given an /;& routine identification number. 5his /$ number is used to inform all processes hen that output routine has access to the /;& bus for outputting data. 5he /;& system has a "ueue used to allot time slots to each output process. 5he time slots for outputting are signaled to each process by the /;& system putting the /&! number onto the /;& bus at the same moment that the /&! control line is set high. 5hese t o items, occurring together, ill signal a gate#eeper PSSP set up for that output routine to put data onto the /;& bus. &nly one gate#eeper ithin the system is set up to output data for any particular /&! /$ number. 8o ever, many gate#eepers may be used for input routines that contain this /$ number. 5here is no need to restrict or control data copied from the /;& bus, so there is no limitation on ho many processes may be aiting for input from a particular output routine. 5he &S tells each process, or output routine, hen it may put data onto the /;& bus. Similarly, the process is given no choice in ho it may output data to the /;& bus. /t does have some fle(ibility over hen it may occur, but only to the e(tent that it has the choice of not outputting to the /;& bus during the time slots allotted. /f a process chooses not to output data during its time slot, it ill have to ait for the ne(t time slot before it has the opportunity to output again. 5he code used in a particular output routine insures that the process has no choice other than to output data hen the &S signals that itAs time to do so. 5his code, constructed by the &S, includes the opcodes such as >&!?, &45, ?&45, /&%S, and !?5. 5he choice of using its timeslot, or not using it,

is left up to the process. 5he /&%S instruction is used to set the local /&% control line high or lo , hich gives the process the po er to enable or disable the >&!? gate#eeper instruction. 5he >&!? instruction atches the /;& bus for its /$ number, in conBunction ith the signal on the global /&! control line. @hen the &S signals the >&!? that its time slot has arrived, the >&!? initiates a Bump to output routine, if it is enabled. 5he output routine outputs the data onto the /;& bus using the series of &45 instructions, hich are only enabled if the >&!? instruction as e(ecuted prior to them. 5he &45 instruction re"uires the !;@ control line to be in the correct state, and the >&!? instruction sets this control line hen its Bump conditions are met. At the end of the routine is an ?&45 instruction that disables the &45 instructions by changing the state of the !;@ control line. &nce the &S has set up the output routine, there is no ay for the process to change or influence the code used in the routine. 5he /$ number and the address of the routine are also set up by the &S and are unchangeable, e(cept by the &S. 5here are no &45 instructions in the process, e(cept hat the &S has put in it. &45 instructions that do e(ist are not enabled until they are accessed through the /;& gate#eeper, the >&!? instruction. 5hen they are disabled at the end of the output routine. Any attempt to use this output routine to usurp the /;& bus ill fail. All of the above steps insure safe and controlled use of the /;& bus. 5his, combined ith the isolation of the processes ithin the system, helps guaranty the integrity of the system.

PSSP Systems 33
5he other aspect of controlling un anted code ithin the system involves ho the code is handled. 5he PSSP design #eeps the code and data separate ithin each PSSP. $ata can only reside in the processing section. $ata that ill be used as code, is not code until it has been put into the control section of a PSSP. Putting code into a control section is a privileged action limited to the &S. +ode can only be deposited into a control section ith the =&7+ instruction. 5he =&7+ instruction uses the +@? global control line to enable the addressed PSSP to accept data into its opcode latches from the au(iliary data;control bus. 5he instruction enables the PSSP it resides in to output data from its processing section to that same bus. 5his is the only ay data can be put into the opcode latches of the control section of a PSSP. 'efore code is put into a control section, it undergoes a series of chec#s. /t is chec#ed to ma#e sure it is not a restricted opcode going to a non.system process, and that it is a valid instruction. /t is also chec#ed for its potential to cause harm ithin the system. 5his system, by design, is immune to many of the virus codes that already e(ist, but this doesnAt mean damaging code canAt be developed. Any process permitted to enter the system is given a certain degree of legitimacy and is accepted by other processes in the system. Safeguards against malicious programs need to be instituted ithin the system at the point here the code is chec#ed during the loading process. $enying such a process entry into the system is the surest method of defeating it. 5his is an easier tas# ithin a PSSP system because all inter.process communications must occur via the /;& bus, and the &S is in control of the entire /;& process.

101

()OSS*R+
$ input : &ne of the t o input channels to the A%4 of each bit position in the processing section. $cti%ation : 5urning on all or part of a PSSP. $lternate mode o' addressing : A ay of addressing PSSPs that provides simultaneous full activation to multiple PSSPs ithin an apportioned section of PSSPs. $pportion : 5o set aside a section of PSSPs and associated bus structures to be used as the e(clusive resource of a process. $pportioned uses : 5he set of bus structures that are divided into sections to effect the isolation of a group of PSSPs. $pportioned sections : <roups of PSSPs that have been isolated from all other PSSPs, along ith a portion of the bus structures, and can be assigned as the e(clusive resource of a process. $pportioning process : A process controlled by the operating system that causes the physical and

logical isolation of a section of PSSPs and their associated bus lines. $pportioning s&itches : 5he groups of s itches used to physically divide various bus structures into sections. $uxiliary us : &ne of the apportioned bus structures. 5his bus serves as a data bus hen a process is being loaded into a ne ly apportioned section and a local control bus for a process that has begun se"uencing. $uxiliary data6control us : Same as the au(iliary bus. B input : &ne of the t o inputs to the A%4 of each bit position in the processing section of a PSSP. B$+I# control line : A control line of the global control bus used to signal all bus apportioning s itches that the data on the /;& bus is the identification number of a s itch. B$+I+ instruction : /nstruction used to set the high or lo state of the 'AS/$ control line.

102
B$+++ instruction : 5he instruction used to set the state of the selected bus.apportioning s itch. Bilateral control lines : %ines of the bilateral control bus. 5hese control lines cause partial activation of a PSSP adBacent to a fully activated PSSP. Carry 'lag control line : &ne of the three flag control lines of the au(iliary bus. C"?1 : &ne of t o cloc# signals in a PSSP system. +%L1 is used for sub.operations ithin an instruction, and it beats t o tic#s for every one tic# of +%L2. C"?2 : &ne of the t o cloc# signals in a PSSP system. +%L2 is used for timing of the se"uencer, and one tic# occurs for every t o tic#s of +%L1. Control section . &ne of the t o sections of a PSSP. 5he control section is responsible for some aspect of control ithin the PSSP, the process, or the system. C17 control signal : 5his signal, the code rite enable signal, is controlled by a PSSP e(ecuting the =&7+ instruction. /t is carried on the global control bus. #ata 'lo& controller : &ne portion of the processing section of a PSSP. 4sed to direct the output from the latches. #ata latch : &ne portion of the processing section of a PSSP. /t is used for data storage. #ecentralization : $ecentrali6ation, in a PSSP system, refers to the fact that there is no central point of processing, control, or memory ithin the system. #ecentralized processing units : 4sed to handle the processing, control, memory, and /;& functions in a PSSP system. #ecoder circuits : 5he maBor component of the control section of PSSPs. #irect addressing : /n a PSSP system, direct addressing means that the operand is in the processing section of the PSSP holding the related opcode. P++P : 5he acronym for decentrali6ed processing unit. P++P system : A computer system built ith a multitude of PSSPs instead of one or more +P4s. P++P used 'or se/uencing : A speciali6ed PSSP designed to only handle the three se"uencing instructions. P++P used as a gatekeeper : A speciali6ed PSSP designed to only handle the >&!? or >/!? instructions.

PSSP Systems 107na le6disa le the B,57 instruction : 5he /&%S instruction is used to set the /&% control line high or lo , hich enables or disables the >&!? instruction. 7na le6disa le the ,8T instruction : 5he !;@ control line is used by the >&!? instruction to enable the &45 instruction, and the ?&45 instruction resets the !;@ control line to disable it. 7,8T instruction : 5he ?&45 instruction resets the !;@ control line so that the &45 instructions are disabled. 7/ual 'lag control line : &ne of three flag control lines used for Bump decisions. 7xecution o' a process : A process e(ecutes on its o n in a PSSP system once the operating system has set the SJ= control line lo ithin the apportioned section in hich the process resides. .lag control lines : +ontrol lines carrying the signals used for Bump decisions.

.ull acti%ation : A PSSP receiving full activation from the primary address bus ill e(ecute its instruction. 9atekeeper 'unction : A PSSP ith the >&!? or >/!? instruction atches the /;& bus for a particular /;& process /$ number to sho up, and hen it does, initiates a Bump to an /;& routine. 9atekeeper instructions : >&!? and >/!? are the t o gate#eeper instructions. 9lo al control us : A non.apportioned bus used by the operating system to send control signals to various system components or processes ithin isolated sections. 9lo al control line : &ne of the control lines of the global control bus. 9lo al control instructions : 4sed solely by the operating system to set the state of the global control lines. I6, us : 5he bus used to input and output all data for isolated processes or devices ithin a PSSP system. /t is used for all inter.process communications. I6, gatekeeper : A PSSP ith the >&!? or >/!? instruction used to control access to the /;& bus. I6, routine identi'ication num er : ?very output routine established by the operating system has an /;& routine identification number uni"ue to it. I6, gatekeeper instructions : 5he >&!? or >/!? instructions used to enable access to the /;& bus. Identi'ication num er : 5he number used to identify a process, an /;& routine, or an apportioning s itch.

10*
Indirect addressing : /n a PSSP system, indirect addressing means that the operand is referred to ith an address. Internal signal 'lo& : 5he flo of signals bet een the processing and control sections of a PSSP. Internal e/ual 'lag control signal : 5he >&!? and >/!? use an internal e"ual flag control signal, instead of the e"ual flag control line. I," control line : A local control line of the apportioned au(iliary data;control bus used to enable or disable the >&!? instruction. I,"+ instruction : /nstruction used to set the state of the /&% control line. I,5 : /;& routine. I,5 control line : A global control line used to signal all /;& gate#eeper instructions that the data on the /;& bus is an /;& routine /$ number. I,5 identi'ication num er : A number assigned to an output routine. I,5"+ instruction : A privileged instruction used by the operating system to set the state of the /&! control line. Isolation : /n a PSSP system, all processes are physically and logically isolated from each other. "ocal control us : 5he au(iliary data;control bus local to a process and being used for local control signals. 5his can only occur hile a process is se"uencing. ;egati%e 'lag control line : &ne of the three flag control lines used for Bump decisions in a PSSP system. ,pcode latch : A component of the control section of a PSSP that holds the opcode. ,+ : 5he acronym used for operating system. ,8T instruction ena ling6disa ling : @hen the >&!? instruction initiates a Bump to output routine it ill set and hold the !;@ control line to the correct state to enable the &45 instruction. 5he ?&45 instruction ill disable it. ,utput data cycle : 5he series of data units that begins ith the /&! /$ number and ends ith the last data unit put onto the /;& bus by an output routine. Partial acti%ation : 5he processing section of a PSSP is partially activated for reading or riting data by a bilateral control line or the secondary address bus.

PSSP Systems 102

Primary address us : 4sed to cause full activation for instruction e(ecution. Pri%ileged instructions : /nstructions that can only be e(ecuted by the &S to affect some aspect of system control.

Processing section : &ne of the t o sections of a PSSP. 8andles all the processing and storage of data. 561 control signal : 4sed in conBunction ith the secondary address bus for reading or riting operand data. 5his signal is also used by the >&!? instruction to enable the &45 instruction. +econdary address us : 5he address buses in a PSSP system used for partial activation. +el'0acti%ation : 5erm is used for those PSSPs that contain instructions that are fully activated automatically by virtue of the instruction they carry. %imited to control functions. +e/uence control lines : ,our control lines used to carry signals that affect the se"uencer. +e/uence master control line : A global control line used to enable;disable the se"uencer in a process. +e/uencer : 5he PSSP used to cause full activation of other PSSPs. +e/uencing stack : 5he group of speciali6ed PSSPs used for se"uencing. +e/uencing stack adFustment : A Bump instruction that has a subse"uent return instruction ill cause an adBustment in the se"uencing stac# hen the Bump is made, and another adBustment hen the subse"uent return occurs. +e/uencing stack limit : 5he se"uencing stac# has an upper and lo er limit. !eaching these limits ill cause a Bump to an error routine. +pecialized P++Ps : PSSPs limited to speciali6ed control functions such as se"uencing. +G: control line : Se"uence master control line used to enable;disable se"uencing in one or more processes. +ystem resources : /n a PSSP system, the resources are the apportionable sections and their associated bus sections, as ell as time allotments for use of the /;& bus. +ystem process : Any process that is part of the operating system. Time allotment : /n a PSSP system, time allotments are assigned for use of the /;& bus.

10)

$
A input, -6 A$$+, 99 alternate mode of addressing, 66, 1-2 A%4, -6, 1-2 AN$, 99 apportioning, 21, 2*, 2), 6), 31, 36, 12-, 1-2 apportioned 'us Structures, 1-2 apportioned sections, 13 apportioning s itches, 13, 20, 126 arithmetic and logic operations, 9) au(iliary data;control bus, 21, -9, 1-2

B
' input, -6 'AS/$ control line, 32, 3-, 12) 'AS/$ signal, 12) 'AS/S instruction, 32 'ASS control line, 3'ASS global control line, 32 'ASS signal, 12) 'ASSS instruction, 32 bilateral control bus, -2, -3, 1*0 booting, 26, 126 bubble sort routine, 113 bus structures, 122

C
carry flag control line, -9 +%L1, and +%L2, 60, 126 code and data, 9, -1, 26 conditional Bump, **, 112 construction of the /;& routine, 2) control operations, 93

+@? control signal, **, 12), 129

#
data bus, 20, 21, 1-2 data flo controller, -6, -) data latch, *-, *6, 92 data unit, 110, 16decentrali6ation, 1decentrali6ed processing units, * direct addressing, )1 PSSPs for booting, 6-

7
?&45, 10e"ual flag control line, 9) e(clusive resource, 121, 12-, 1*0

.
flag control line, -), 9), 112 flag control signals, 1-3 full activation, 22

9
global control bus, 126 global control operations, 31

*
8%5, 112

I
/;& bus, 61, 12*, 129 /;& gate#eeper, 16, 161 /;& routine identification number, 2-, 29, 62, 32, 1*0 /;& system, 12) /N+, 99 indirect addressing, )1 /NP, 9* input routine, 96 instruction formats, )1, )3 instruction set, 69 integration, 1internal signal flo , -9, *2 /&% control line, 26, 6-, 10*, 1*0 /&%S, 10-, 10*, 1*0 /&!%S, 3*

B
>/!?, 2-, 22, 3*, 10>&!?, 2-, *1, **, 29, 62, 10-, 161

109
Bump instructions, 112

"
local control bus, *1 local control operations, 10-

:
memory protection, 30 =&7+, )3 movement of data, )* =&78, )2 =&75, )2

;
non.apportioned bus structures, 12N&P, 112 N&5, 99

one operand instructions, 9) opcode latch, 1-), 1-9, 1)) operating system, 121 &!, 99 &45, 9*, 92 output routine, 96

P
partial activation, 22 primary address bus, 22, -2, -6, *0, *9, 10*, 1-0 privileged instruction, 20, -9, *2, 126 processing section of PSSPs, -2 program flo operations, 11*

5
!;@ control signal, 1-3 read.only, 29, 6-, 1)1 !?5, 119

+
secondary address bus, 21, -2, *9, 22, )2, )6, 1-0 security and stability, 1)self.activating, 2-, -0, 2S?J, 23, 32 S?JS%, 23, 32 se"uencing PSSPs, 23 se"uencing operations, 3* se"uencing stac#, 23, 32, 39 S%, 99 SJ1, SJ2, SJ-, 60, 100, 129 SJ=, 2-, 29, **, 60, 36, 33, 129 S!, 99 SS?J, 23, 32 s itch control, 1*9 s itches, 1*2

T
termination, 26, 126 time allotment, 2), 16tree.li#e structure, 122, 1-0 t o operand instructions, 99

H
K&!, 99