Jitter and Wander In SONET/SDH Systems

White Paper
January 2001

Order Number: 249347-001

As of January 15, 2001, this document replaces the Level One document Jitter and Wander In SONET/SDH Systems White Paper.

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined. Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The SONET/SDH may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners.

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Jitter and Wander In SONET/SDH Systems

Contents
1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 Introduction .................................................................................................................. 5 The Phenomenon of Wander and Jitter ............................................................ 5 Solving the Problem.................................................................................................. 7 LXT6282: Description of Features .......................................................................7 Dejitter Mode ................................................................................................................ 8 Retiming Mode ............................................................................................................ 8 Pass-Through Mode .................................................................................................. 8 Definitions .....................................................................................................................9 Author ............................................................................................................................. 9

Figures
1 Local Exchange..................................................................................................... 7

Tables
1 2 SONET Jitter for DS1 ............................................................................................ 5 SONET jitter for DS3 ............................................................................................. 6

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Jitter and Wander In SONET/SDH Systems

1.0

Introduction
With the introduction of Synchronous Digital Hierarchy (SDH) and Synchronous Optical Network (SONET) new demands are placed on network synchronization. Synchronization performance of most telecommunications networks require improvement to support SDH and SONET. Short term performance (timing stability for durations up to 1000 seconds) necessitates the use of excellent clocks. Long term performance also becomes important, with the utilization of multiple Primary Reference Source (PRS) clocks and shorten synchronization chains to keep wander to a minimum. Also, for error free communications, all intermediate digital switches must be supplied from highly accurate and extremely stable clock sources. This must be guaranteed across network limits to minimize the effects of systemic error bursts on the quality of service. In the case of mobile radio networks, the clock signals (1.5 or 2 Mbit/s) for the tributaries of digital mobile radio networks (PCN) such as GSM or DCS must also be of the highest quality. The base stations (BTS) derive the carrier frequency for their burst transmissions from the incoming digital signal. Phase variations outside the permitted limits cause overlapping of the user channels, resulting in errors in the handover at cell boundaries. If the clock stability of the signal supplied by the network operator is insufficient, complex measures are needed in order to compensate for this in the access network. This requires systems which filter out the phase variations or even the installation of separate clock generation and distribution equipment. All these actions are necessary to maintain error free transmission of DS1, E1, and DS3 signals that pass through SDH and SONET.

2.0

The Phenomenon of Wander and Jitter

The phenomenon of wander occurs in plesiochronous networks and in synchronous networks in particular, sporadic pointer activity leads to low frequency variations which could spread throughout the network due to low-pass filter characteristics of the network elements. Accumulation may occur under worst-case conditions that can affect both PDH signals and mapped payload signals. The effect may be partially canceled out in the various synchronous signal layers but it may be amplified by additive superimposition. Wander of more than 18 microseconds can cause slips. On the other hand Jitter is defined as high frequency phase variations that occur when multiplexing PDH signals into an SDH network and subsequently demultiplexing them. In the case of a DS1 or E1 payload, the amount of jitter that SONET introduces on a DS1 payload is given in the table below.

Table 1.

SONET Jitter for DS1

Mapping Single Pointer Triple Pointer Bursts Phase Transient Periodics Periodics + Single Pointer 0.7 UI 0.6 UI 0.6 UI 0.6 UI 0.6 UI 0.6 UI

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Jitter and Wander In SONET/SDH Systems

The amount of jitter that a SONET system could introduce on a DS3 payload according to ANSI is given in the table below. Table 2. SONET jitter for DS3
Mapping Single Pointer Triple Pointer Bursts Phase Transient Periodics Periodics + Single Pointer 0.4 UI 0.7 UI 1.3 UI 1.2 UI 1.0 UI 1.3 UI

The above values were specified in order to maintain the 5-UI jitter requirement for DS3 payloads. While the rate of the outgoing 2 Mbit/s signal is normally equal to the rate of the 2 Mbit/s signal going into the SDH network, occasionally this relationship disappears. A retiming function is necessary for suppression of jitter and wander which the 2Mbit/s signal suffers during transmission in SDH and which makes the signal useless for carrying the synchronous frequency to the PDH domain. A smoothing buffer is needed to equalize the phase difference between the clock of the incoming 2 Mbit/s signal and the clock of the Network Element (NE). ETS 300462-2 and G.803 recommend using STM-N and/or a 2 MHz station clock as carriers for synchronization. Phase transients, which are the result of phase distortion due to pointer movement, are particularly evident when using a 2 Mbit/s signal as a synchronization. When downstream equipment uses this 2Mbit/s as its reference the possibility exists that such phase transients pull the clock out lock which will result in the loss of some data. Retiming of a 2 Mbit/s signal provides a way to overcome this particular problem. However, it introduces other issues, such as when retiming is applied, it enforces timing integrity at the cost of data integrity, while the traditional SDH method achieves data integrity at the expense of timing integrity (the occasional pointer adjustment). To retime an outgoing 2 Mbit/s signal, means simply to retime this signal with the internal clock of the multiplexer equipment in which the desynchronization takes place. This can be done by reading the recovered 2Mbit/s signal into an elastic store and timing the output of the elastic store with the system clock. Unfortunately, there are situations where it is impossible to follow the guidelines of G.803 and ETS 300462-2. These situations arise when SDH is used in access networks to connect users equipment (PABXs) to the switch/exchange. The standards recommend using the station clock outputs of the SDH equipment to synchronize the peripheral equipment. This is fine when it is possible, but often the distance between the CPE and the SDH-NE is too large to bridge with this signal or the CPE is not equipped with a special synchronization input or there is a mismatch in signal type. Another case arises when PDH or radio link spurs are used between the SDH network and the CPE. Refer to Figure 1. In these cases there are no other practical alternatives to simply using the 2 Mbits/s traffic signal as synchronization reference.

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Jitter and Wander In SONET/SDH Systems

Figure 1. Local Exchange

Local Exchange
ADM

E1 E1
PDHRadio Link

E1

ADM

ADM

SDH Ring
Local Exchange
ADM ADM

PABX

E1 E1
ADM

E1

E1 PBX BOX
CRC Monitoring Jitter

3.0

Solving the Problem

Level One Communications, with the introduction of the LXT6282 device addresses the specific problems mentioned above. The LXT6282 is an eight-channel digital interface. It integrates an E1 dejitter phase lock loop, an E1 retiming function and a CRC-4 monitor function for each E1 transmitter and a CRC-4 monitoring function for each E1 receiver. It is optimized for SDH applications and can be used in conjunction with the SXT6251 (21 E1 mappers) for STM-0/1 applications. On one side the LXT6282 connects with the SXT6251, while on the other side it connects with the LXT380, an octal E1 Line Interface Unit (LIU). It also includes a Motorola/Intel compatible microcontroller interface for alarm and performance monitoring.

4.0

LXT6282: Description of Features

The eight fully independent E1 transmitter blocks can be configured for different applications. Each transmitter input interface accepts an NRZ encoded E1 signal input and clock input. The incoming E1 signal may have a CRC-4 multiframe structure according to recommendation ITU G.704. A CRC-4 calculation is also performed over the multiframe and compared with the incoming CRC-4 value. The transmitter of the LXT6282 can be configured to operate in three different modes: Dejitter mode, Retiming mode, and Pass-Through Mode.

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5.0

Dejitter Mode
In the Dejitter mode, the transmitter filters jitter and eliminates gaps in the incoming E1 clock and data. The incoming data is fed into a 32-bit asynchronous FIFO. The write clock of the FIFO is the gapped input clock, which is fed to the dejitter attenuator consisting of a second All Digital Phase Locked Loop (ADPLL) having a 2.0 Hz loop bandwidth with external reference clock at 65.536 MHz +/- 100 ppm. The filtered clock output of the ADPLL is the read clock of the FIFO. This function is bypassed when the retiming function is enabled or configuring the data path in passthrough mode. This working mode is fully transparent- no data is lost or added in the transmission.

6.0

Retiming Mode
In the retiming mode, the transmitter eliminates wander and jitter in the incoming clock. Incoming E1 data is converted to a byte parallel format and fed into a two frame-wide elastic buffer. The E1 frame acquisition process initializes the write and read control logic of the elastic store. The data is read out of the elastic buffer using an external clock reference input. The reference clock may or may not be at the same frequency as the incoming clock. If the read and write frequencies are different, the elastic store will periodically overflow or underflow. In either case, the read control logic will process a controlled slip of one complete frame in order to recenter the elastic buffer. This will result in the loss or repetition of one complete frame. The retiming FIFO may also operate on an unframed 2Mbit/s signal busy setting the transmitter to Retiming Test Mode. In this case, the read and write control logic of the elastic store is in full free-running mode and independent of the framing algorithm. As the data is supposed to be unframed in this test mode, CRC-4 error monitoring is not valid. This mode is not transparent. It can handle a maximum of 26 time slots (208 UI) of wander or low frequency jitter before a frame slip occurs. This controlled frame slip assures that the time-slot assignment is not lost at the output of the device. When the device is set in the retiming mode all jitter and wander due to the multiplexing/demultiplexing process in the transmission is eliminated.

7.0

Pass-Through Mode
In the pass-through mode no dejitter or retiming is performed on the input data. The input clock is shunted to the output clock. CRC-4 monitoring and HDB3 encoding can be performed if so configured. The receiver of the LXT6282 consists of eight fully independent E1 receiver blocks. Each receiverinput interface includes an NRZ encoded E1signal input or HDB3 encoded data, a serial clock, and a Loss Of Signal Alarm Indication. The E1 input data may have a CRC-4 multiframe structure according to recommendation ITU G.704, also HDB3 code errors are detected and stored in a set of microprocessor-accessible counters. A CRC-4 calculation is also performed over the multiframe and compared to the incoming CRC-4 value. CRC-4 multiframe alignment is used for immunity against false framing and also provides nonintrusive error monitoring capabilities for the E1 payload. When CRC-4 is selected as the E1 framing option the transmitter attempts to synchronize to a 16-frame multiframe structure.

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The LXT6282 can also be used as a drop-in solution to make existing equipment compatible with the more stringent jitter specifications.

8.0

Definitions
Unit Interval (UI): Measure of jitter amplitude. 1 UI corresponds to an amplitude of one bit clock period. The unit interval is independent of bit rate and signal coding as it is referred to the length of a clock period.

9.0

Author
Fotis Konstantinidis is a Senior Application Engineer at Level One Communications, San Francisco. Mr. Konstantinidis has 15 years of experience in the telecommunications industry and holds a MSEE degree from the Univesity of Bridgeport. Level One Communications, 201 Mission St., 5th Floor, San Francisco, CA 94105.

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