Microprocessor-8086

By Pragnan Chakravorty
Director, CARET

M.Tech (IIT Kharagpur), Member-IEEE(USA), ACM(USA) Member IEEE :Communication. Soc, Microwave Theory and Techniques Soc, Antenna & Wave Propagation. Soc

Clique for Applied Research in Electronic Technology Advaita Corporation

Memory Interface BIU C-Bus

Instruction
6 5 4 3 2 1

Stream Byte Queue

ES CS SS DS IP

Control System A-Bus

EU

AH BH CH DH SP BP SI DI

AL BL CL DL

ALU

Operands Flags

8086 INTERNAL BLOCK DIAGRAM

FFFFFH 7FFFFH

Highest Address Top of Extra Segment

4489FH

Top of Code Segment

64K 70000H 5FFFFH 64K

ES
Extra Segment Base ES=7000H Top of Stack Segment 38AB4H

CS

IP=4214
348A0H Code Segment Base CS=348AH

SS
Stack Segment Base SS=5000H Top of Code Segment

50000H 4489FH 64K

BASE EA

CS
Code Segment Base CS=348AH Top of Data Segment 5FFFFH

3 4 8 A 0 + 4 2 1 4 3 8 A B 4

PHYSICAL ADDRESS

348A0H 2FFFFH

Top of Stack Segment

64K

DS
Bottom of Data Segment

SS

20000H

5FFE0H

Top of Stack

SP=FFE0
50000H Stack Segment Base SS=5000H

MEMORY SEGMENTATION
GENERATION OF PHYSICAL ADDRESS AS BASE + EFFECTIVE ADDRESS

BASE

5 0 0 0 0 EA + F F E 0 5 FF E 0

PHYSICAL ADDRESS

ENCODED IN INSTRUCTION

BX BP SI DI
EXPLICIT IN INTRUCTION

OR SINGLE INDEX OR

BX BP
DOUBLE INDEX

SI
OR

OR

DI
EU

OR

DISPLACEMENT
OR

CS SS DS ES

0000 0000 0000 0000

OR

ASSUMED UNLESS OVERRIDEN BY PREFIX

OR

OR BIU OR

OR

PHYSICALADDRESS

[BX]+[SI] [BX]+[DI] [BP]+[SI] [BP]+[DI] [SI] [DI] D16 [BX]

[BX]+[SI]+ D8 [BX]+[DI]+ D8 [BP]+[SI]+ D8 [BP]+[DI]+ D8 [SI]+D8 [DI]+D8 [BP]+D8 [BX]+D8

[BX]+[SI]+ D16 [BX]+[DI]+ D16 [BP]+[SI]+ D16 [BP]+[DI]+ D16 [SI]+D16 [DI]+D16 [BP]+D16 [BX]+D16

AL CL DL BL AH CH DH BH

AX CX DX BX SP BP SI DI

THE THIRTY TWO POSSIBLE WAYS OF ADDRESSING DATA IN 8086

THE EFFECTIVE ADDRESS PRODUCED BY THE MEMORY ADDRESSING MODES ARE ADDED TO DATA SEGMENT TO FORM THE PHYSICAL ADDRESS; BP IS USED TO COMBINE WITH STACK SEGMENT TO FORM THE PHYSICAL ADDRESS.SEGMENT OVERRIDE PREFIX CAN BE USED TO ENABLE THE EFFECTIVE ADDRESS TO BE ADDED TO ANOTHER SEGMENT BASE OTHER THAN THE DEFAULT BASE ADDRESS

8284 CLOCK GENERATOR RES

MN/MX CLK M/IO READY RESET INTA RD WR

RDY DT/R DEN ALE STB OE 74LS373 OCTAL LATCH (2 or 3)

WAIT STATE GENERATOR

AD0-AD15 A16-A19 BHE

T 8286 TRANSCEVER OE (2)

H L We OD RAM

CE OE PROM

Cs Rd Wr MCS-80 PERI

MULTIPLEXING & DEMULTIPLEXING OF ADDRESS AND DATA BUSES

T1 CLK

T2

T3

TWAIT

T4

T1

T2

T3

TWAIT

T4

B A S

ALE

I C

M/IO^

8 0 8

ADDR/STATUS

BHE^(A19-16)

S7S3

BHE^(A19-16

S7S3

BUS RESERVED

S
D15-D0 A15-A0 DATA OUT D15-D0

ADDR/DATA RD^

A15-A0

FOR DATA IN

Y S T E

READY

READY

READY

DT/R^

WAIT

WAIT

T I M

DEN^

I N

WR^

MEMORY ACCESS TIME

PROGRAM DEVOLOPMENT

START DEFINE PROBLEM DEVOLOP ALGORITHM CREATE SOURCE FILE ASSEMBLE

ALGORITHM FOR 8086

.ASM .OBJ .LST LOAD EMULATOR

LOAD DEBUGGER LOAD PROGRAM RUN & TEST PROGRAM ERRORS ?

YES

ASSEMBLY ERRORS LINK

NO .EXE .MAP .BIN YES LOAD PROGRAM RUN & TEST PROGRAM ERRORS ?

LOCATE NO

EXTERNAL SYSTEM

USE DEBUGGER TO FIND ERRORS

USE DEBUGGER TO FIND ERRORS

STOP

3FFH 3FCH

TYPE 255 POINTER AVAILABLE

084H 080H 07FH

TYPE 33 POINTER AVAILABLE TYPE 32 POINTER AVAILABLE TYPE 31POINTER RESERVED

8086 INTERUPT POINTER/VECTOR TABLE

014H 010H 00CH 008H 004H CS IP 000H

TYPE 5 POINTER RESERVED TYPE 4 POINTER OVERFLOW TYPE 3POINTER BREAK-POINT TYPE 2 POINTER NONMASKABLE TYPE 1POINTER SINGLE-STEP TYPE 0 POINTER DIVIDE ERROR

INTERRUPTS

SOFTWARE INTERRUPTS

HARDWARE INTERRUPTS

ALL 0 THROUGH 255 POSSIBLE INTERRUPTS INTERNALLY ACTIVATED AND HAS HIGHER PRIORITY THAN HARDWARE INTERRUPTS

INTERRUPTS 0 THROGH 255 ARE POSSIBLE FOR HARDWARE INTERRUPTS BUT 32 TO 255 ARE INDEED USED.WORKS ONLY WHEN IF IS SET BY STI INSTRUCTION.ACTIVATED BY EXTERNAL HARDWARE DEVICE THROGH NMI & INTR PINS OF 8086.HAS LOWER PRIORITY THAN SOFTWARE INTERRUPTS

HOW DOES SOFTWARE AND HARDWARE INTERRUPT WORK

SOFTWARE INTERRUPT: STACK POINTER IS DECREMENTED BY 2 AND FLAG REGISTER PUSHED IN. 8086 INTR PIN IS DISABLED BY CLEARING THE IF FLAG IN THE FLAG REGISTER. TRAP FLAG TF IS RESET STACK POINTER IS DECREMENTED BY 2 AND CURRENT CS CONTENT IS PUSHED IN STACK POINTER IS AGAIN DECREMENTED BY 2 AND CONTENT OF CURRENT IP IS PUSHED IN AN INDIRECT FAR JUMP IS MADE TO THE STARTING ADDRESS OF THE INTERRUPT SERVICE PROCEDURE REQUESTED DESIRED INTERRUPT SERVICE PROCEDURE IS EXECUTED

HARDWARE INTERRUPT: AFTER IF IS SET BY AN STI INSTRUCTION, INTR IS ENABLED WHEN INTR RECEIVES A HIGH SIGNAL,8086 SENDS OUT TWO INTA^ PULSES TO 8259A.8259A THEN SENDS THE DESIRED INTERRUPT TYPE TO 8086 8086 MULTIPLIES THE INTERRUPT TYPE BY 4 TO PRODUCE THE REQUIRED ADDRESS OF THE INTERRUPT VECTOR TABLE. CONTENTS OF FLAG ARE PUSHED INTO THE STACK IF AND TF ARE CLEARED RETURN ADDRSS IS PUSHED INTO THE STACK STARTING ADDRESS OF ISR IS TAKEN FROM INTERRUPT VECTOR TABLE ISR IS EXECUTED

PRIORITIES OF VARIOUS INTERRUPTS

INTERRUPT DEVIDE ERROR,INTn,INTO

PRIORITY HIGHEST PRIORITY

NMI

INTR

SINGLE-STEP

LOWEST PRIORITY

HOW DO MASTER AND SLAVE WORK?

WHEN THE SLAVE RECEIVES INTERRUPT SIGNAL ON ONE OF ITS IR INPUTS.IF THAT IR INPUT IS UNMASKED ON THE SLAVE AND IF IT HAS HIGHER PRIORITY THAN THE ONE BEING SERVICED IN THE SLAVE,THEN THE SLAVE SENDS AN INT SIGNAL TO IR INPUT OF THE MASTER.

IF THAT IR INPUT IS UNMASKED ON THE MASTER AND IF IT HAS HIGHER PRIORITY THAN THE ONE BEING SERVICED IN THE MASTER,THEN THE MASTER SENDS INT SIGNAL TO INTR OF 8086.

IF THE INTR IS ENABLED 8086 WILL SEND TWO INTA^ PULSES TO BOTH THE MASTER AND THE SLAVE.

THE SLAVE IGNORES THE FIRST INTA^ BUT THE MASTER RECEIVES IT AND SENDS A SLAVE INDENTIFICATION NUMBER ON ITS CAS0,CAS1,CAS2 OUTPUT LINES.

SENDING A 3 BIT IDENTIFICATION NUMBER ENABLES THE DESIRED SLAVE AND ON RECEIVING THE SECOND INTA^ THE SLAVE WILL OUTPUT THE DESIRED INTERRUPT TYPE THROUGH THE LOWER 8 DATA BUS LINES.

THERE AFTER 8086 HANDLES AND SERVES THE INTERRUPT TYPE ACCORDINGLY

MAINLINE PROGRAM IR4 PROC STI STI IR2 PROC MAINLINE PROGRAM IR4 PROC

EOI COMMAND IRET EOI COMMAND IRET IR2 PROC

EOI COMMAND IRET

EOI COMMAND IRET

;INITITALIZATION OF 8259A PRIORITY INTERRUPT CONTROLLER MOV AL,00010011B MOV DX,0FF00H OUT DX,AL MOV AL,01000000B MOV DX,0FF02H OUT DX,AL MOV AL,00000001B OUT DX,AL MOV AL,11111010B OUT DX,AL ;EDGE TRIGGERED SINGLE,ICW4 ;POINT TO 8259A CONTROL ;SEND ICW1 ;TYPE 64 ;POINT AT ICW2 ADDRESS ;SEND ICW2 ;ICW4 8086 MODE ;SEND ICW4 ;OCW1 TO UNMASK IR0 AND IR2 ;SEND OCW1

8251A (USART),UNIVERSAL SYNCHRONUS ASYNCHRONUS RECEIVER TRANSMITTER

SOME BASIC TERMINOLOGIES OF SERIAL DATA COMMUNICATION: SIMPLEX TRANSMISSION: IN THIS METHOD DATA IS TRANSMITTED IN ONLY ONE DIRECTION, A COMMERCIAL BROAD CASTING CENTRE IS A GOOD EXAMLE OF IT HALF DUPLEX TRANSMISSION: THIS MAKES COMMUNICATION IN EITHER DIRECTION BETWEEN TWO SYSTEMS BUT ONE DIRECTION AT A TIME. A RADIO WALKY-TALKY IS EXAMPLE OF IT FULL DUPLEX TRANSMISSION: EITHER SYSTEM CAN SEND RECEIVE DATA AT THE SAME TIME .PSTN TELEPHONE NETWORK BEING AN EXAMPLE OF IT BAUD RATE: BAUD RATE INDICATES THE RATE AT WHICH SERIAL DATA IS TRANSFERRED AND IS DEFINED AS 1/(THE TIME BETWEEN SIGNAL TRANSITONS)

ASYNCHRONUS DATA CHARECTER

START

D0

D1

D2

D3

D4

D5

D6

D7

STOP STOP

MODEM MICROCOMPUTER

MODEM MICROCOMPUTER

TXD RXD (3) RTS^ (5) CTS^ (4) CD^ (1) DTR^ (2) DSR^ DCE DTE DCE
TELEPHONE LINE

TXD RXD RTS^ CTS^ CD^ DTR^ DSR^ DTE

WORKING OF USART
1). AFTER THE TERMINAL IS TURNED ON IT RUNS SELF CHECKS IF ANY AND ASSERTS DATA-TERMINAL- READY(DTR^) 2). WHEN THE TERMINAL IS READY TO TRANSMIT OR RECEIVE, THE MODEM WILL ASSERT DATA SET READY (DSR^) TO THE TERMINAL. 3). WHEN THE TERMINAL HAS A CHARACTER READY TO SEND ,REQUEST TO SEND (RTS^) IS ASSERTED TO THE MODEM. 4). MODEM ASSERTS CARRIER DETECT (CD^) TO THE TERMINAL INDICATING IT HAS ESTABLISHED CONTACT WITH REQUIRED COMPUTER 5). WHEN THE MODEM IS FULLY READY TO TRANSMIT DATA IT ASSERTS CLEAR TO SEND (CTS^) SIGNAL BACK TO THE TERMINAL 6). WHEN THE TERMINAL HAS COMPLETED SENDING DATA IT NEEDS TO,IT MAKES ITS RTS^ SIGNAL HIGH AND THIS CAUSES THE MODEM TO UNASSERT CTS^

MODE WORD FOR 8251

D7 D6 D5 D4 D3 D2 D1 D0

S2

S1

EP PEN L2

L1

B2

B1
BAUD RATE FACTOR

0 0
SYNC MODE

1 0
(1X)

0 1
(16X)

1 1
(64X)

CHARACTER LENGTH

0 0
EVEN PARITY 1=EVEN 0=ODD PARITY ENABLE 1=ENABLE 0=DISABLE
5 BITS

1 0
6 BITS

0 1
7 BITS

1 1
8 BITS

NUMBER OF STOP BITS

0 0
INV

1 0
1 BITS

0 1

1 1
2 BITS

1 BITS AFFECTS TX; RX

COMMAND WORD FOR 8251

D7 EH D6 IR D5 D4 D3 D2 D1 D0 RTS ER SBRK RXE DTR TXEN
TRANSMIT ENABLE 1=ENABLE 0=DISABLE DATA TERMINAL READY HIGH WILL FORCE DTR O/P TO ZERO RECEIVE ENABLE 1=ENABLE RXRDY 0=DISABLE RXRDY SEND BREAK CHARECTER 1=FORCES TXD LOW 0=NORMAL OPERATION ERRORO RESET 1=RESET ALL ERROR FLAGS (PE,OE,FE)

ENTER HUNT MODE 1=ENABLE SEARCH FOR SYNC CHARECTER

INTERNAL RESET HIGH RETURNS 8251 TOMODE INSTRUCTION FORMAT

REQUEST TO SEND HIGH WILL FORCE RTS O/P TO ZERO

STATUS WORD FOR 8251

D7
DSR

D6
SYN DET

D5
FE

D4
OE

D3
PE

D2
TXE

D1
RXRDY

D0
TXRDY

DATA SET READY TEST MODEM FOR DSR

TRANSMITTER READY INDICATES ,8251 IS READY TO ACCEPT DATA

SYNC DETECT,SET FOR INTERNAL SYNC DETECT,INDICATES SYNC HAS BEEN ACHIEVED FRAMING ERROR,SET WHEN VALID STOP BIT NOT DETECTED,RESET BY ER OVERRUN ERROR SET WHEN CPU DOESNT READ A CHARACTER BEFORE THE NEXT ONE IS AVAILABLE.RESET BY ER OF CW SET WHEN PARITY ERROR IS DETECTED IT IS RESET BY ER OF CW

RECEIVER READY INDICATES THAT THE 8251 HAS RECEIVED SERIAL I/P & IS READY TO GIVE THAT TO CPU

DATA TERMINAL READY HIGH WILL FORCE DTR O/P TO ZERO

MOV DX,0FFF2H MOV AL,00H OUT DX,AL MOV CX,2 D0:LOOP D0 OUT DX,AL MOVCX,2 D1:LOOP D1 OUT DX,AL MOV CX,2 D2:LOOP D2 MOV AL,40H OUT DX,AL MOV CX,2 D3:LOOP D3 MOV AL,11001110B OUT DX,AL MOV CX,2 D4 LOOP: D4 MOV AL,00110111B OUT DX,AL

;POINT AT COMMAND REGISTER ADDRESS ;SEND ZEROS TO ENSURE DEVICE IS IN ;COMMAND INSTRUCTION ;FORMAT,BEFORE RESET IS ISSUED AND ;DELAY AFTER EACH COMMAND ;INSTRUCTION

;SENT INTERNAL RESET COMMAND TO ;RETURN DEVICE TO IDLE STATE LOAD DELAY ;CONSTANT AND DELAY

;DELAY LOAD COMMAND WORD AND SEND IT

;INSTRUCTIONS FOR TRANSMITTING DATA USING POLLING METHOD MOV DX,0FFF2H ;POINT AT CONTROL REGISTER TEST1: ;ADDRESS IN AL,DX ;READ STATUS AND CHECK STATUS AND AL,10000001B ;OFDATA SET READY AND TRANSMIT CMP AL,10000001B ;READY? CONTINUE TO POLL IF NOT JNE TEST1 ;READY OTHERWISE POINT AT DATA MOV DX,0FFF0H ;ADDRESS LOAD DATA TO SEND MOV AL, DATA_TO_SEND ;AND SEND IT OUTDX,AL ;INSTRUCTIONS FOR RECEIVING DATA USING POLLING METHOD MOV DX,0FFF2H TEST2: IN AL,DX AND AL,00000010B CMP AL,00000010B JNZ TEST2 MOV DX,0FFF0H IN AL,DX ;POINT AT CONTROL REGISTER ;ADDRESS ;READ STATUS AND CHECK STATUS ; RXRDY AND CONTINUE TO POLL IF NOT ;READY OTHERWISE POINT AT DATA ;ADDRESS AND GET DATA

8255 PARALLEL PORT DEVICE

COMMON METHODS OF PARALLEL DATA TRANSMISSION:
SIMPLE I/P O/P: IN THIS METHOD THE DATA IS TRANSFERRED ON PARALLEL LINES AS IT IS WITHOUT COORDINATION BETWEEN TRANSMITTING AND RECEIVING SYSTEM DATA

SIMPLE STROBE I/P O/P: HERE THE TRANSMITTING DEVICE SENDS A STROBE SIGNAL, RIGTH AFTER SENDING DATA,TO VALIDATE THE DATA TRANSMITTED STB^

DATA

SINGLEHANDSHAKE I/O: IN THIS METHOD THE STROBE SIGNAL RECEIVED FROM A TRANSMITTING DEVICE IS ANSWERED BY AN ACKNOWLEDGE SIGNAL FROM RECEIVING DEVICE ENSURING THE DATA HAS BEEN RECEIVED AND THE RECEIVING UNIT IS READY TO READ NEXT DATA STB^

ACK DOUBLE HANDSHAKE MODE: TRANSMITTING SIGNAL SEND STB^ TO RECEIVING END TO ASK WHETHER IT SHOULD SEND DATA,THE RECEIVING END IF READY WOULD SEND ACK TO SAY ITS READY THEN ANOTHER STB^ IS SENT FROM TRANSMITTER TO ASCERTAIN A VALID DATA TO RECEIVER.RECEIVERWOULD SEND ANOTHER ACK TO ANSWER THAT IT HAS RECEIVED DATA AND AWAITS ANY FURTHER REQUEST TO RECEIVE DATA STB^

ACK

MICRO COMPUTER

PORT DEVICE

PERIPHERAL

PARALLEL DATA LINES

STB^ ACK

MODES OF OPERATION
MODE 0: THIS MODE OPERATES OF SIMPLE I/P O/P WITHOUT HANDSHAKE ALL THE THREE PORTS CAN BE SET IN THIS MODE. MODE 1: THIS OPERATE IN HANSHAKED I/P OR O/P OPERATION BOTH PORT A AND PORT B CAN BE SET IN THIS MODE .PC0, PCI,PC2 FUNCTION AS HANDSHAKE LINES FOR PORT B. PC3,PC4 AND PC5 ACT AS HANDSHAKE LINE FOR PORT A.PC6 AND PC7 LINES ARE AVAILABLE FOR I/P AND O/P MODE 2: ONLY PORT A CAN BE SET IN THIS MODE.HERE PORT A CAN BE USED FOR BIDIRECTIONAL DATA TRANSFER IN A HANDSHAKE MODE.THIS MEANS DATA CAN BE I/P OR O/P THROUGH THE SAME EIGHT LINES.PC3 THROUGH PC7 ARE HANDSHAKE LINES .PC0 TO PC2 ACT AS HANDSHAKE PINS IF PORT B IS IN MODE 0, OTHERWISE ARE USED FOR HANSHAKE OF PORT B.