Regulation-2008

Academic Year -2013-2014

T.J INSTITUTE OF TECHNOLOGY KARAPAKKAM, CHENNAI-97

DEPARTMENT OF ECE

Question Bank
SUBJECT CODE SUBJECT NAME : EC235 : VLS !"S #$ SEM : !I YEAR : III

"#$$% T&'()*+
UNIT ! SPECIFICATION USING !ERILOG HDL Basic conce,ts- identi.iers- gate ,rimiti)es? gate dela0s? o,erators? timing controls? ,rocedural assignments conditional statements? !ata .lo+ and R7L? structural gate le)el s+itc' le)el modeling? !esign 'ierarc'ies? Be'a)ioral and R7L modeling? 7est (enc'es? Structural gate le)el descri,tion o. decoder? e6ualit0 detector? com,arator? ,riorit0encoder? 'al. adder? .ull adder? Ri,,le carr0 adder? ! latc' and ! .li, .lo,

#. E,-./01 2)0'3.* /2(45 2'&/60(4)/. 7(8'..019:

"#;+ "# 507'+ "Apr10)

1% &'at is (e'a)ioural modelling* 2% &'at are t'e t+o statements used in ,rocedural constructs* 3% &'at is initial statement* 4% &rite one e-am,le .or initial statement* /% !e.ine al+a0s statement% 1% &'at is timing control* 2% &'at are t'e t'ree .orms in timing control* "N(6<##+ 8% !e.ine dela0 control% 3% !e.ine intra-assignment dela0 control% 10% !e.ine e)ent control% 11% &'at is le)el sensiti)e timing control* 12% &rite a(out !44 design e-am,le% 13% !esign !44 using (e'a)ioural modelling% 14% &rite a(out u,-counter% 1/% !esign u,-counter using (e'a)ioural modelling* 11% &rite a(out do+n-counter% 12% !esign do+n-counter using (e'a)ioural modelling% 18% &rite a(out simulation result o. u,-do+n counter 13% &rite a(out (lock statement% 5N(6<#$+ 20% #i)e notes on se6uential (lock% 21% &rite a(out ,arallel (lock% 22% &rite a(out out,ut node% 23% &rite a(out timing ,eriod%
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Regulation-2008 24% &rite a(out (ista(le de)ice in,uts% 2/% &rite a(out un(ounded state%

Academic Year -2013-2014

2. E,-./01 01 8'5/0. /2(45 -)(='84)/. /18 -)(='84)/. =(15014(4> />>0917'15, =(18050(1/. >5/5'7'15 01 2'&/60(4)/. 7(8'..019: "#;+ 1% &'at is ,rocedural assignment* 2% &'at are t'e t+o kinds o. ,rocedural assignments* 3% &'at is (locking ,rocedural assignments* 4% &'at is non-(locking assignments* (Nov09) /% &'at is conditional statement* 1% !e.ine i. statements% 2% !e.ine case statement% 8% &rite s0nta- o. case statement% 3% !e.ine loo, statement% 10% &'at are t'e .our kinds o. loo, statements* 11% !e.ine .ore)er loo,% 12% &rite s0nta- o. .ore)er loo,% 13% #i)e notes on re,eat@loo, statements% 14% &rite t'e s0nta- o. re,eat@loo,% (Apr09) 1/% &rite a(out +'ile@loo, statement% 11% &rite s0nta- o. +'ile@loo,% 12% &rite a(out .or@loo, statement* 18% &rite an e-am,le o. .or-loo,* 13% &'at are t'e .our ,arts o. .or-loo,* 20% &rite an e-am,le o. assign-de assign* 21% &rite a(out a(solute dela0% 22% &rite a(out ,rocedural continuous assignment* 23% List out t'e kinds o. ,rocedural continuous assignments* 24% &rite a(out assign-de assign* 2/% &rite a(out .orce-release* 3. E,-./01 01 8'5/0. /2(45 8/5/ 3.(? 7(8'..019: "#;+ "# 507'+ "A-)<$9+ 1% 2% 3% 4% /% 1% 2% 8% 3% !e.ine data.lo+ modelling* 5Apr10) &'at is continuous assignment* &rite s0nta- o. continuos assignments* &'at are t'e c'aracteristics o. continuous assignments* &'at is im,licit continuous assignment* &'at is im,licit net declaration* !e.ine dela0* &'at are t'e t'ree +a0s o. s,eci.0ing dela0s* !e.ine regular assignment dela0* (Nov10)
Year9V sem9":23/49VLS 2

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Regulation-2008

Academic Year -2013-2014

10% &'at is im,licit continuous assignment dela0* 11% !e.ine net declaration dela0* 12% !e.ine e-,ression* 13% &'at is o,erands* 14% &'at is o,erators* 1/% &'at are t'e o,erator t0,es* 11% &rite a(out o,erator ,recedence* 12% &rite a(out arit'metic o,erator t0,e* 18% &rite a(out unar0 o,erator t0,e* 13% &rite a(out logical o,erator t0,e* 20% &rite a(out relational o,erator t0,e* 21% &rite a(out e6ualit0 o,erator t0,e* 22% &rite a(out B:! adder circuit using data .lo+ model* 23% &rite a(out t'e .ormat o. test data% 24% List out t'e ,ro(lem su..ered (0 modern tester% 2/% &rite a(out concatenation o,erator t0,e%

. E,-./01 01 8'5/0. /2(45 >?05=& .'6'. 7(8'..019: "#;+ "# 507'+ "A-)<$9+ 1% !e.ine s+itc' le)el modelling* 2% &'at is s+itc' modelling elements* 3% &'at are t'e t+o t0,es o. mos s+itc'es*
4. Define scan chain. (Apr12)

/% &'at is t'e e..ect o. scan signal asserted* 1% &'at is cmos s+itc'* 2% &'at are t'e t+o control in,uts in cmos* 8% !ra+ cmos s+itc'% 3% !esign o. cmos s+itc'% 10% &'at is (idirectional s+itc'es* 11% &'at are t'e t'ree ke0+ords used in (idirectional s+ic'tes*
12. Write about structure methods.

13% 14% 1/% 11% 12%

&'at is ,o+er and ground* &'at is resisiti)e s+itc'es* &'at is ,ull u, and ,ull do+n* "N(6<$9+ &'at is time dela0 +it' s+itc' ,rimiti)es* &rite cmos in)erter e-am,le*

18. What are the rules in scan design?

13% &'at is cmos nand gate* 20% !esign cmos in)erter circuit% 21% !ra+ t'e trut' ta(le o. cmos nand gate* 22% !esign o. cmos 2-in,ut nand gate* 23% &rite a(out ram cell% 24% &rite a(out cmos ram (lock*
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Regulation-2008
25. Write about serial and partial serial scan.

Academic Year -2013-2014

5. E,-./01 01 8'5/0. /2(45 5'>5 2'1=&: 1% !e.ine test (enc'* 2% &'at are t'e t'ree ,ur,ose o. test (enc'* 3% &rite t0,ical test (enc' .orm* 4% &'at are t'e t+o main a,,roac'es o. +a)e.orm generation* /% &'at are t'e t0,es o. +a)e.orms* 1% &'at is t'e (est +a0 to generate se6uence )alues* 2% !ra+ +a)e.orm generation using initial statement* 8% &'at is a module* 3% &'at is t'e di..erence (et+een module and instance* 10% &rite s0nta- o. a module* "A-)<##+ 11% &'at is a ,ort* 12% &'at is t'e c'aracteristics o. module* 13% #i)e an e-am,le o. module* 14% &'at is ,ort declaration* 1/% &'at is ,ort connecting rules* 5N(6<#$+ 11% &'at is in,uts* 12% &'at is out,uts* 18% &'at is inouts* 13% &'at is +idt' matc'ing* 20% &'at is unconnected ,ort* 21% !esign .ull adder circuit% 22% Ao+ to im,lement as0mmetric gates* 23% &rite a(out ske+ed in)erters% 24% &'en reset condition occurs% 2/% &rite t'e uses o. as0mmetric gates%

;. 0 . E,-./01 01 8'5/0. /2(45 8'>091 &0')/)=&* /18 08'15030')>: ";+ 1% &'at is design 'ierarc'0* 2% Ao+ ne+ 'ierarc'0 is de.ine* 3% &'at is root module* 4% !ra+ 'ierarc'0 o. (locks and module instantiation* /% &'at are t'e t+o (locks in to, modules* 1% &'at does addition instantiates* 2% &'at does su(traction instantiates* 8% &'at is identi.iers* 3% Ao+ to s,eci.0 t'e identi.iers* 10% &'at are t'e e-am,le o. identi.iers*

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Regulation-2008 Academic Year -2013-2014 00. E,-./01 01 8'5/0. /2(45 9/5' 8'./*>: "#$+ "# 507'+ "A-)<#$+ 11% &'at is gate dela0* 12% &'at are t'e t'ree t0,es o. gate dela0s* 5N(6<#$+ 13% &'at is rise dela0* 14% &'at is .all dela0* 1/% &'at is turn-o.. dela0* 11% &'at 'a,,ens i. one dela0 s,eci.ied* 12% &'at 'a,,ens i. t+o dela0 s,eci.ied* 18% &'at 'a,,ens i. t'ree dela0 s,eci.ied* 13% &'at is minBt0,Bma- )alues% 20% %&rite a(out min )alues% 21% &rite a(out ma- )alues% 22% &rite a(out t0, )alues% 23% &rite a(out dela0 used in gate instantiation% 5A-)<#$+ 24% &rite a(out (uilt in ,rimiti)e gates% 2/% &'at are t'e uses o. =seudo-n<CS gate*

7. E,-./01 01 8'5/0. /2(45 M/143/=54)019 5'>5 -)01=0-.'>: "#;+ "# 507'+ "Apr09) 1% &'at is critical .actor in )lsi* 2% !e.ine e-'austi)e testing% 3% !e.ine .ault model* 4% &'at is stuck model* (Nov09) /% &'at is stuck at .ault* 1% Ao+ stuck at .ault determines* 2% &'at are t'e ot'er models in .ault models* 8% &'at is t'e ,ro(lem arise +it' :<CS* 3% !e.ine C(ser)a(ilit0% 10% !e.ine controlla(ilit0% 11% &'at is meant (0 .ault co)erage* (N0v08) 12% &rite a(out good mac'ine% 13% Ao+ discre,anc0 detected* 14% &'at is t'e e..ect o. discre,anc0* 1/% Ao+ to ac'ie)e +orld class 6ualit0* 11% &rite a(out A7=#% 12% &'at is use o. A7=#* 18% &'at is t'e e..ect o. adding scan and (uilt in sel. test* 13% &rite a(out dela0 .ault testing% 20% Ao+ dela0 .ault occurs* 21% &rite a(out .ault% 22% List out t'e t0,es o. stuck at .ault* 23% &rite a(out s-a-0 .ault%
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Regulation-2008 24% &rite a(out s-a-1 .ault% 2/% &rite a(out s'ort circuit .ault%

Academic Year -2013-2014

@. D'>=)02' >(7' ',/7-.'> (3 =(7201/50(1/. =0)=405> 4>019 >5)4=54)/. 9/5' .'6'. 7(8'..019: "#;+ "# 507'+ "N(6<#$+ 1% &'at is structural gate le)el modelling o. decoder circuit* 2% &'at is modelling o. e6ualit0 detector* 3% !ra+ t'e diagram o. single rung ladder model% 4% &rite a(out kirc'o..Ds current la+% /% List t'e conditions .or t'e occurrence o. .all dela0% 1% &rite a(out a(solute dela0% 2% &'at are t'e limitations o. ,arasitic estimation* 8% &'at is com,arator circuit* "N(6<#$+ 3% &rite i9o ,ort declaration in design o. 4(it magnitude com,arator* 10% &'at is t'e ,ur,ose o. c'aracteriEation* 11% &rite a(out c'aracteriEation test% 12% &'at is t'e need .or c'aracteriEation test* 13% #i)e notes on 0ield% 14% &rite a(out ,roduction test% 1/% List out t'e need .or ,roduction test* (Nov10) 11% List out t'e ,arameters )eri.ied (0 ,roduction test* 12% &rite a(out (urn-in ,arameter% 18% &rite t'e ste,s in)ol)ed during (urn-in* 13% List out t'e uses o. .unctional test* 20% &'at are t'e .aults detected (0 !!Q test* 21% List out t'e ,ro(lem o. !!Q testing% 22% &rite a(out s0stematic class in ,rocess s,eed% 23% List out t'e tools a)aila(le in t0,ical :A! tool set* 24% &rite a(out (ridging .aults% 2/% &rite a(out random class%

9.

E,-./01 01 8'5/0. /2(45 S*>5'7 .'6'. 5'>5 5'=&10A4'>: "#;+ 1% 2% 3% 4% /% 1% &'at is 8"7A#* &'at is 87A#* !e.ine (oundar0 scan* &'at is s0stem le)el test tec'ni6ue* !e.ine non-in)asi)e mode% !e.ine ,in ,ermission mode%

2% &'at is (oundar0 scan met'odolog0* "N(6<#$+ 8% &'at is BR*

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Regulation-2008 Academic Year -2013-2014 3% &'at is BS:* 10% &'at is BSR* 11% &rite a(out BS7* 12% &rite a(out !:C!"* 13% #i)e notes on R* 14% #i)e notes on 7A=* "A-)<#$+ 1/% &rite a(out 7:>* 11% &rite a(out 7! * 12% #i)e notes on 7!C* 18% &rite a(out 7!R* 13% &rite a(out 7<S* 20% #i)e notes on 7RS7* 21% &rite a(out normal o,eration o. c'i, in (oundar0 scan% 22% &rite a(out critical ,at' dela0s% 23% !ra+ t'e diagram o. multi,le t'res'old )oltage :<CS logic% 24% &rite t'e condition .or circuit in stand-(0 mode% 2/% &rite a(out (oundar0 scan arc'itecture% #$. E,-./01 /2(45 6.>0 8'>091 3.(? /18 5&'0) 341=50(1>: "#;+ "# 507'+ "N(6<$@+ 1% &rite t'e ,rocess o. )lsi design .lo+% 2% &rite t'e ste,s in)ol)ed in ,'0sical design* 3% &'at is VA!L* 4% &'at are maFor ca,a(ilities o. VA!L* /% &'at is design met'odolog0* 1% &'at is gate le)el modelling* 2% &'at are t'e t+o t0,es o. design met'odolog0* 8% &'at is data.lo+ modelling* 3% &'at is (e'a)ioural modelling* "Apr11) 10% &'at are t'e data t0,es o. VA!L* 11% &'at is net data t0,e* 12% #i)e some e-am,le o. net data t0,e* 13% &'at is register data t0,e* 14% #i)e some e-am,le o. register data t0,e* 1/% &'at is a ,arameter* 11% &'at is task in VA!L* 12% #i)e some e-am,les .or s0stem task in )erilog* 18% &'at is com,iler directi)e* 13% #i)e some e-am,le o. com,iler directi)es* 20% &'at are t'e ad)antages o. B S7 ,rocess* 21% &rite a(out ,rec'arge ,'ase% 22% List out t'e disad)antages o. domino logic% 23% &rite a(out non-monotonic% (Nov10) 24% List out t'e a,,lications o. memor0 sel.-test% 2/% &rite a(out ::L%
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Regulation-2008

Academic Year -2013-2014

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