Code No: RR411106 Set No.

1
IV B.Tech I Semester Supplementary Examinations, February 2007
VLSI DESIGN
(Bio-Medical Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Explain with neat sketches the Drain and Transfer characteristics of n-channel
enhancement MOSFET.
(b) With neat sketches explain the transfer characteristics of a CMOS inverter.
[10+6]
2. With neat sketches explain how pnp transistor is fabricated in Bipolar process. [16]
3. Design a stick diagram for p-MOS Ex-OR gate. [16]
4. Design a layout diagram for the PMOS logic shown below Y = (A + B).C [16]
5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If n-
channel sheet resistance Rsn = 10 4 Ω per square and p-channel sheet resistance
Rsp = 3.5 × 104 Ω per square. [16]

Figure 5
6. Clearly discus about the following FPGA Technology
(a) Anti fuse Technology.
(b) Static RAM Technology. [8+8]
7. (a) Define the term DFT and explain about it.
(b) Explain any one test procedure to test sequential logic. [8+8]
8. Mention different growth technologies of the thin oxides and explain about any one
technique. [16]

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Code No: RR411106 Set No. 2
IV B.Tech I Semester Supplementary Examinations, February 2007
VLSI DESIGN
(Bio-Medical Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) Derive an equation for IDS of an n-channel Enhancement MOSFET operating

in linear region.
(b) A PMOS transistor is operating in saturation region with the following para-
meters. VGS = −5V ; Vtp = −1.2V ; W/L = 95; µnCox = 95 µA/V 2
Find Trans conductance of the device. [8+8]

2. With neat sketches explain CMOS fabrication using Twin - Tub process. [16]

3. Design a stick diagram for the NMOS logic shown below Y = (A + B).C [16]

4. Design a layout diagram for the CMOS logic shown below Y = (A + B).C [16]

5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If n-

channel sheet resistance Rsn = 10 4 Ω per square and p-channel sheet resistance
Rsp = 2.5 × 104 Ω per square. [16]

Figure 5
6. Differentiate between CPLD and FPGA with neat sketches explain the architecture
of any one of the CPLD. [16]

7. With respect to synthesis process explain the following terms.

(a) Flattening
(b) Factoring.
(c) Mapping. [6+5+5]

8. Explain about the following packaging design considerations.

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Code No: RR411106 Set No. 2
(a) VLSI design rules.
(b) Thermal design consideration. [8+8]

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Code No: RR411106 Set No. 3
IV B.Tech I Semester Supplementary Examinations, February 2007
VLSI DESIGN
(Bio-Medical Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. (a) With neat sketches explain the Drain characteristics of the p-channel Enhance-
ment MOSFET.
(b) An p-MOS Transistor is operated in the Active region with the following
parameters VGS = −4.5V ; Vtp = −1V ; W/L = 95; µnCox = 95 µA/V 2
Find its drain current and drain source resistance. [8+8]
2. With neat sketches explain BICMOS fabrication in an p-well process. [16]
3. Design a stick diagram for n-MOS Ex-OR gate. [16]
4. Design a layout diagram for the CMOS logic shown below Y = (A + B + C) [16]
5. Calculate on resistance of the circuit shown in Figure 5 from VDD to GND. If n-
channel sheet resistance Rsn = 10 4 Ω per square and p-channel sheet resistance
Rsp = 4.5 × 104 Ω per square. [16]

Figure 5
6. With neat sketches explain the architecture of PAL. [16]
7. With respect to synthesis process explain the following terms.
(a) Flattening
(b) Factoring.
(c) Mapping. [6+5+5]
8. With neat sketches explain the ION- lithography process. [16]

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Code No: RR411106 Set No. 4
IV B.Tech I Semester Supplementary Examinations, February 2007
VLSI DESIGN
(Bio-Medical Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. A MOS Transistor in the active region measured to have a drain current of 20 µA

when VDS =Veff. When VDS is increased by 0.5V, ID increases to 23 µA. Estimate
the out impedance rds , and the out impedance constant λ. [16]

2. (a) Compare between CMOS and bipolar technologies.

(b) With neat sketches explain nMOS fabrication process. [8+8]

3. Design a stick diagram for n-MOS Ex-OR gate. [16]

4. Design a layout diagram for two input pMOS NOR gate. [16]

5. Derive an equation for the propagation delay from input to output of the pass
transistor chain shown in Figure 5. [16]

Figure 5
6. With neat sketches explain the architecture of PAL. [16]

7. What is need for RTL simulation? Clearly explain RTL simulation flow in the
ASIC design flow and also mention few leading simulation tools. [16]

8. Explain about the following two oxidation methods.

(a) High pressure oxidation.

(b) Plasma oxidation. [8+8]

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