02-Computer System Technology

Computer System Technology
1. 2. 3. 4. 5. 6. From Components to Applications Computer Systems and Their Parts Generations of Progress Processor and Memory Technologies Peripherals, I/O, and Communications Software Systems and Applications
Levels of Representation (abstractions)

High Level Language Program (e.g., C) Compiler Assembly Language Program (e.g.,MIPS) Assembler Machine Language Program (MIPS) Machine Interpretation Hardware Architecture Description (e.g., block diagrams) Architecture Implementation Logic Circuit Description (Circuit Schematic Diagrams)
MIPS Instruction Representations 2
temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw lw sw sw

0000 1010 1100 0101
$t0, 0($2) $t1, 4($2) $t1, 0($2) $t0, 4($2)

1001 1111 0110 1000 1100 0101 1010 0000 0110 1000 1111 1001 1010 0000 0101 1100 1111 1001 1000 0110 0101 1100 0000 1010 1000 0110 1001 1111
Register File
AL U
From Components to Applications
Software
Hardware
Electronic components Lowlevel view
3 4
Application domains
Application designer
Computer designer
System designer
Highlevel view
Computer archit ecture Computer organization
Figure 3.1
Subfields or views in computer system engineering.
Computer Architecture, Background and Motivation
What Is (Computer) Architecture?

Clients requirements: function, cost, . . . Clients taste: mood, style, . . .
Goals Interface Means
Architect
Construction tec hnology: material, codes, . . .
Engineering
Arts
The world of arts: aesthetics, trends, . . .
Interface
Figure 3.2 Like a building architect, whose place at the engineering/arts and goals/means interfaces is seen in this diagram, a computer architect reconciles many conflicting or competing demands.
Circuit designer
Logic designer
Computer Systems and Their Parts

Computer
Analog
Digital
Fixed-function
Stored-program
Electronic
Nonelectronic
General-purpose
Special-purpose
Number cruncher
Data manipulator
Figure 3.3 The space of computer systems, with what we normally mean by the word computer highlighted.
Computer Architecture, Background and Motivation 5
Price/Performance Pyramid
Super
$Millions
$100s Ks
$10s Ks
$1000s
$100s
$10s
Mainframe
Server
Differences in scale, not in substance
Workstation
Personal
Embedded
Figure 3.4
Classifying computers by computational power and price range.

6
Automotive Embedded Computers

Impact sensors
Airbags
Brakes
Engine
Cent ral controller Navigation & entert ainment
Figure 3.5 Embedded computers are ubiquitous, yet invisible. They are found in our automobiles, appliances, and many other places.
Personal Computers and Workstations
Figure 3.6 Notebooks, a common class of portable computers, are much smaller than desktops but offer substantially the same capabilities. What are the main reasons for the size difference?
Digital Computer Subsystems
Figure 3.7 The (three, four, five, or) six main units of a digital computer. Usually, the link unit (a simple bus or a more elaborate network) is not explicitly included in such diagrams.
Generations of Progress
Table 3.2 The 5 generations of digital computers, and their ancestors. Generation (begun)
0 (1600s) 1 (1950s) 2 (1960s) 3 (1970s) 4 (1980s) 5 (1990s)
Processor Memory I/O devices technology innovations introduced

(Electro-) mechanical Vacuum tube Transistor SSI/MSI LSI/VLSI ULSI/GSI/ WSI, SOC Wheel, card Magnetic drum Magnetic core RAM/ROM chip Lever, dial, punched card Paper tape, magnetic tape Drum, printer, text terminal
Dominant look & fell

Factory equipment Hall-size cabinet Room-size mainframe
Disk, keyboard, Desk-size video monitor mini Desktop/ laptop micro
SRAM/DRAM Network, CD, mouse,sound SDRAM, flash
Sensor/actuator, Invisible, point/click embedded
10
IC Production and Yield

30-60 cm Blank wafer with defects Slicer 15-30 cm
x x x x x x x x x x x
Patterned wafer Processing: 20-30 steps
Silicon crystal ingot
0.2 cm Good die Microchip or other part Mounting
(100s of simple or scores of complex processors)
Dicer
Die
Die tester
Part tester
Usable part to ship
~1 cm
~1 cm
Figure 3.8
The manufacturing process for an IC part.

11
Effect of Die Size on Yield
120 dies, 109 good
26 dies, 15 good
Figure 3.9
Visualizing the dramatic decrease in yield with larger dies.
Die yield =def (number of good dies) / (total number of dies) Die yield = Wafer yield [1 + (Defect density Die area) / a]a Die cost = (cost of wafer) / (total number of dies die yield) = (cost of wafer) (die area / wafer area) / (die yield)
12
Processor and Memory Technologies

Interlayer connections deposited on the outside of the stack
Backplane PC board Die
Bus CPU Connector Memory (a) 2D or 2.5D packaging now common Stacked layers glued together
(b) 3D packaging of the future
Figure 3.11
Packaging of processor, memory, and other components.
13
Moores Law
TIPS Tb
Processor
1.6 / yr 2 / 18 mos 10 / 5 yrs GIPS
R10000 Pentium II Pentium 256Mb 68040 64Mb 16Mb 80386 68000 MIPS 80286 4Mb 1Mb 1Gb
Processor performance
Gb
80486
Mb 4 / 3 yrs
256kb 64kb
kIPS 1980
1990
2000
kb 2010
Calendar year
Trends in processor performance and DRAM memory chip capacity

Memory chip capacity
Memory
Pitfalls of Computer Technology Forecasting

DOS addresses only 1 MB of RAM because we cannot imagine any applications needing more. Microsoft, 1980 640K ought to be enough for anybody. Bill Gates, 1981 Computers in the future may weigh no more than 1.5 tons. Popular Mechanics I think there is a world market for maybe five computers. Thomas Watson, IBM Chairman, 1943 There is no reason anyone would want a computer in their home. Ken Olsen, DEC founder, 1977 The 32-bit machine would be an overkill for a personal computer. Sol Libes, ByteLines
Input/Output and Communications
Typically 2-9 cm
Floppy disk
CD-ROM
. ..
(a) Cutaway view of a hard disk drive
.. .
Magnetic tape cartridge
(b) Some removable storage media
Figure 3.12
Magnetic and optical disk memory units.
16
Communication Technologies
10 12
Processor bus
Geographically distributed I/O network System-area network (SAN) Local-area network (LAN) Metro-area network (MAN)
Bandwidth (b/s)
10 9
10 6 Same geographic location
Wide-area network (WAN)
10 3 10 9 (ns)
10 6 (s)
10 3 (ms)
(min)
10 3
(h)
Latency (s)
Figure 3.13 Latency and bandwidth characteristics of different classes of communication links.
Software Systems and Applications
Software Application:
word processor, spreadsheet, circuit simulator, .. .
System Operating system Enabler:

disk driver, display driver, printing, .. .
Translator: Coordinator:
scheduling, load balancing, diagnostics, .. . MIPS assembler, C compiler, .. .
Manager:
virtual memory, security, file system, .. .
Figure 3.15
Categorization of software, with examples in each class.
18
High- vs Low-Level Programming

More abstract, machine-independent; easier to write, read, debug, or maintain More conc rete, machine-specific, error-prone; harder to write, read, debug, or maintain
Swap v[i] and v[i+1]
temp=v[i] v[i]=v[i+1] v[i+1]=temp
add add add lw lw sw sw jr
$2,$5,$5 $2,$2,$2 $2,$4,$2 $15,0($2) $16,4($2) $16,0($2) $15,4($2) $31
Assembler
Interpreter
Compiler
Very high-level language objectives or tasks
High-level language statements
Assembly language instructions, mnemonic
Machine language instructions, binary (hex)
00a51020 00421020 00821020 8c620000 8cf20004 acf20000 ac620004 03e00008
One task = many statements
One statement = several instructions
Mostly one-to-one
Figure 3.14
Models and abstractions in programming.

19
Computer Performance
1. 2. 3. 4. 5. 6. Cost, Performance, and Cost/Performance Defining Computer Performance Performance Enhancement and Amdahls Law Performance Measurement vs Modeling Reporting Computer Performance The Quest for Higher Performance
Cost, Performance, and Cost/Performance

$1 G
Computer cost
$1 M
$1 K
$1 1960
1980
2000
2020
Calendar year
Cost/Performance
Performance Superlinear: economy of scale Linear (ideal?)
Sublinear: diminishing returns Cost
Figure 4.1
Performance improvement as a function of cost.
22
Defining Computer Performance

CPU-bound task
Input
Processing
Output
I/O-bound task
Figure 4.2 Pipeline analogy shows that imbalance between processing power and I/O capabilities leads to a performance bottleneck.
23
Six Passenger Aircraft to Be Compared

B 747
DC-8-50
24
Performance of Aircraft: An Analogy

Table 4.1 Key characteristics of six passenger aircraft: all figures are approximate; some relate to a specific model/configuration of the aircraft or are averages of cited range of values. Aircraft Airbus A310 Boeing 747 Boeing 767 Boeing 777 Concorde DC-8-50 Passengers
250 470 250 375 130 145
Range (km)
8 300 6 700 12 300 7 450 6 400 14 000
Speed (km/h)
895 980 885 980 2 200 875
Price ($M)
120 200 120 180 350 80
Speed of sound 1220 km / h

Different Views of Performance

Performance from the viewpoint of a passenger: Speed
Note, however, that flight time is but one part of total travel time. Also, if the travel distance exceeds the range of a faster plane, a slower plane may be better due to not needing a refueling stop
Performance from the viewpoint of an airline: Throughput

Measured in passenger-km per hour (relevant if ticket price were proportional to distance traveled, which in reality it is not) Airbus A310 Boeing 747 Boeing 767 Boeing 777 Concorde DC-8-50 250 895 = 0.224 M passenger-km/hr 470 980 = 0.461 M passenger-km/hr 250 885 = 0.221 M passenger-km/hr 375 980 = 0.368 M passenger-km/hr 130 2200 = 0.286 M passenger-km/hr 145 875 = 0.127 M passenger-km/hr
Performance from the viewpoint of FAA: Safety

Cost Effectiveness: Cost/Performance

Table 4.1 Key characteristics of six passenger aircraft: all figures are approximate; some relate to a specific model/configuration of the aircraft or are averages of cited range of values.
Aircraft Passengers Range (km) Speed (km/h) Price ($M)
Larger values better Throughput (M P km/hr)

0.224 0.461 0.221 0.368 0.286 0.127
Smaller values better Cost / Performance

536 434 543 489 1224 630
A310 B 747 B 767 B 777 Concorde DC-8-50
250 470 250 375 130 145
8 300 6 700 12 300 7 450 6 400 14 000
895 980 885 980 2 200 875
120 200 120 180 350 80
27
Concepts of Performance and Speedup

Performance = 1 / Execution time Performance = 1 / CPU execution time (Performance of M1) / (Performance of M2) = Speedup of M1 over M2 = (Execution time of M2) / (Execution time M1) Terminology: M1 is x times as fast as M2 (e.g., 1.5 times as fast) M1 is 100(x 1)% faster than M2 (e.g., 50% faster) is simplified to
CPU time = Instructions (Cycles per instruction) (Secs per cycle) = Instructions CPI / (Clock rate)
Instruction count, CPI, and clock rate are not completely independent, so improving one by a given factor may not lead to overall execution time improvement by the same factor.
28
Elaboration on the CPU Time Formula

CPU time = Instructions (Cycles per instruction) (Secs per cycle) = Instructions Average CPI / (Clock rate)
Instructions: Number of instructions executed, not number of instructions in our program (dynamic count) Is calculated based on the dynamic instruction mix and knowledge of how many clock cycles are needed to execute various instructions (or instruction classes) 1 GHz = 109 cycles / s (cycle time 109 s = 1 ns) 200 MHz = 200 106 cycles / s (cycle time = 5 ns)
Clock period
Average CPI:
Clock rate:
29
Dynamic Instruction Count

How many instructions are executed in this program fragment? 250 instructions for i = 1, 100 do 20 instructions for j = 1, 100 do 40 instructions for k = 1, 100 do 10 instructions endfor endfor endfor Static count = 326
Each for consists of two instructions: increment index, check exit condition 12,422,450 Instructions 2 + 20 + 124,200 instructions 100 iterations 12,422,200 instructions in all 2 + 40 + 1200 instructions 100 iterations 124,200 instructions in all 2 + 10 instructions 100 iterations 1200 instructions in all for i = 1, n while x > 0
Faster Clock Shorter Running Time

Suppose addition takes 1 ns Clock period = 1 ns; 1 cycle Clock period = ns; 2 cycles
4 steps
Solution
1 GHz
20 steps 2 GHz
In this example, addition time does not improve in going from 1 GHz to 2 GHz clock
Figure 4.3
Faster steps do not necessarily mean shorter travel time.

31
Performance Enhancement: Amdahls Law

50
f =0
f = fraction
unaffected p = speedup of the rest
40 Speedup (s ) 30 20
f = 0.05 f = 0.01 f = 0.02
10
f = 0.1
1 s = f + (1 f)/p
50
0 0 10 20 30 Enhancement factor (p ) 40
min(p, 1/f)
Figure 4.4 Amdahls law: speedup achieved if a fraction f of a task is unaffected and the remaining 1 f part runs p times as fast.
Amdahls Law Used in Design

Example 4.1
A processor spends 30% of its time on flp addition, 25% on flp mult, and 10% on flp division. Evaluate the following enhancements, each costing the same to implement: a. Redesign of the flp adder to make it twice as fast. b. Redesign of the flp multiplier to make it three times as fast. c. Redesign the flp divider to make it 10 times as fast. Solution a. Adder redesign speedup = 1 / [0.7 + 0.3 / 2] = 1.18 b. Multiplier redesign speedup = 1 / [0.75 + 0.25 / 3] = 1.20 c. Divider redesign speedup = 1 / [0.9 + 0.1 / 10] = 1.10 What if both the adder and the multiplier are redesigned?
33
Amdahls Law Used in Management

Example 4.2
Members of a university research group frequently visit the library. Each library trip takes 20 minutes. The group decides to subscribe to a handful of publications that account for 90% of the library trips; access time to these publications is reduced to 2 minutes. a. What is the average speedup in access to publications? b. If the group has 20 members, each making two weekly trips to the library, what is the justifiable expense for the subscriptions? Assume 50 working weeks/yr and $25/h for a researchers time. Solution a. Speedup in publication access time = 1 / [0.1 + 0.9 / 10] = 5.26 b. Time saved = 20 2 50 0.9 (20 2) = 32,400 min = 540 h Cost recovery = 540 $25 = $13,500 = Max justifiable expense
Performance Measurement vs Modeling

Execution time
Machine 1
Machine 2 Machine 3
Program A B C D E F
Figure 4.5
Running times of six programs on three machines.
35
Generalized Amdahls Law

Original running time of a program = 1 = f1 + f2 + . . . + fk New running time after the fraction fi is speeded up by a factor pi f1 + p1 p2 f2 + ... + pk If a particular fraction is slowed down rather than speeded up, use sj fj instead of fj / pj , where sj > 1 is the slowdown factor fk
Speedup formula 1 S= f1 + p1 p2 f2 + ... + pk fk
36
Performance Benchmarks
Example 4.3 You are an engineer at Outtel, a start-up aspiring to compete with Intel via its new processor design that outperforms the latest Intel processor by a factor of 2.5 on floating-point instructions. This level of performance was achieved by design compromises that led to a 20% increase in the execution time of all other instructions. You are in charge of choosing benchmarks that would showcase Outtels performance edge. a. What is the minimum required fraction f of time spent on floating-point instructions in a program on the Intel processor to show a speedup of 2 or better for Outtel? Solution a. We use a generalized form of Amdahls formula in which a fraction f is speeded up by a given factor (2.5) and the rest is slowed down by another factor (1.2): 1 / [1.2(1 f) + f / 2.5] 2 f 0.875
Performance Estimation
Average CPI = All instruction classes (Class-i fraction) (Class-i CPI) Machine cycle time = 1 / Clock rate CPU execution time = Instructions (Average CPI) / (Clock rate) Table 4.3 Usage frequency, in percentage, for various instruction classes in four representative applications.
Data compression C language compiler Reactor simulation Atomic motion modeling
Application Instrn class
A: Load/Store B: Integer C: Shift/Logic D: Float E: Branch F: All others
25 32 16 0 19 8
37 28 13 0 13 9
32 17 2 34 9 6
37 5 1 42 10 4
38
CPI and IPS Calculations

Example 4.4 (2 of 5 parts) Consider two implementations M1 (600 MHz) and M2 (500 MHz) of an instruction set containing three classes of instructions: Class F I N CPI for M1 5.0 2.0 2.4 CPI for M2 4.0 3.8 2.0 Comments Floating-point Integer arithmetic Nonarithmetic
a. What are the peak performances of M1 and M2 in MIPS? b. If 50% of instructions executed are class-N, with the rest divided equally among F and I, which machine is faster? By what factor? Solution a. Peak MIPS for M1 = 600 / 2.0 = 300; for M2 = 500 / 2.0 = 250 b. Average CPI for M1 = 5.0 / 4 + 2.0 / 4 + 2.4 / 2 = 2.95; for M2 = 4.0 / 4 + 3.8 / 4 + 2.0 / 2 = 2.95 M1 is faster; factor 1.2
MIPS Rating Can Be Misleading

Example 4.5 Two compilers produce machine code for a program on a machine with two classes of instructions. Here are the number of instructions: Class A B CPI 1 2 Compiler 1 600M 400M Compiler 2 400M 400M
a. What are run times of the two programs with a 1 GHz clock? b. Which compiler produces faster code and by what factor? c. Which compilers output runs at a higher MIPS rate? Solution a. Running time 1 (2) = (600M 1 + 400M 2) / 109 = 1.4 s (1.2 s) b. Compiler 2s output runs 1.4 / 1.2 = 1.17 times as fast c. MIPS rating 1, CPI = 1.4 (2, CPI = 1.5) = 1000 / 1.4 = 714 (667)
Reporting Computer Performance
Table 4.4
Measured or estimated execution times for three programs. Time on machine X Program A Program B Program C All 3 progs 20 1000 1500 2520 Time on machine Y 200 100 150 450 Speedup of Y over X 0.1 10.0 10.0 5.6
Analogy: If a car is driven to a city 100 km away at 100 km/hr and returns at 50 km/hr, the average speed is not (100 + 50) / 2 but is obtained from the fact that it travels 200 km in 3 hours.
41
Comparing the Overall Performance

Table 4.4 Measured or estimated execution times for three programs.
Time on machine X Program A Program B Program C 20 1000 1500
Time on machine Y 200 100 150
Speedup of Y over X 0.1 10.0 10.0 6.7 2.15
Speedup of X over Y
10 0.1 0.1 3.4 0.46
Arithmetic mean Geometric mean
Geometric mean does not yield a measure of overall speedup, but provides an indicator that at least moves in the right direction
42
Effect of Instruction Mix on Performance

Example 4.6 (1 of 3 parts) Consider two applications DC and RS and two machines M1 and M2: Class Data Comp. Reactor Sim. A: Ld/Str 25% 32% B: Integer 32% 17% C: Sh/Logic 16% 2% D: Float 0% 34% E: Branch 19% 9% F: Other 8% 6% M1s CPI 4.0 1.5 1.2 6.0 2.5 2.0 M2s CPI 3.8 2.5 1.2 2.6 2.2 2.3
a. Find the effective CPI for the two applications on both machines. Solution a. CPI of DC on M1: 0.25 4.0 + 0.32 1.5 + 0.16 1.2 + 0 6.0 + 0.19 2.5 + 0.08 2.0 = 2.31 DC on M2: 2.54 RS on M1: 3.94 RS on M2: 2.89
The Quest for Higher Performance

State of available computing power ca. the early 2000s: Gigaflops on the desktop Teraflops in the supercomputer center Petaflops on the drawing board Note on terminology (see Table 3.1) Prefixes for large units: Kilo = 103, Mega = 106, Giga = 109, Tera = 1012, Peta = 1015 For memory: K = 210 = 1024, M = 220, G = 230, T = 240, P = 250 Prefixes for small units: micro = 106, nano = 109, pico = 1012, femto = 1015
44
Performance Trends and Obsolescence

TIPS Tb
Processor
1.6 / yr 2 / 18 mos 10 / 5 yrs GIPS
R10000 Pentium II Pentium 256Mb 68040 64Mb 16Mb 80386 68000 MIPS 80286 4Mb 1Gb
Processor performance
Gb
80486
Mb 4 / 3 yrs
1Mb 256kb
64kb
kIPS 1980
1990
2000
kb 2010
Calendar year
Memory chip capacity
Memory
Figure 3.10 Trends in processor performance and DRAM memory chip capacity (Moores law).
Can I call you back? We just bought a new computer and were trying to set it up before its obsolete.
45
Super-computers
PFLOPS Massively parallel processors $240M MPPs
Supercomputer performance
$30M MPPs TFLOPS CM-5 CM-5 CM-2 Y-MP GFLOPS Vector supercomputers
Cray X-MP
MFLOPS 1980
1990
2000
2010
Calendar year
Figure 4.7
Exponential growth of supercomputer performance.

46
The Most Powerful Computers

1000
Plan Develop Use
Performance (TFLOPS)
100+ TFLOPS, 20 TB
100
ASCI Purple
30+ TFLOPS, 10 TB
ASCI Q
10+ TFLOPS, 5 TB
10
3+ TFL OPS, 1.5 TB
ASCI W hite ASCI Blue

1+ TFL OPS, 0.5 TB
ASCI
1 1995
ASCI Red 2000 2005 2010
Calendar year
Figure 4.8 Milestones in the DOEs Accelerated Strategic Computing Initiative (ASCI) program with extrapolation up to the PFLOPS level.
47
Performance is Important, But It Isnt Everything

TIPS
DSP performance per Watt GIPS
Absolute proce ssor performance
GP processor performance per Watt MIPS
Figure 25.1 Trend in computational performance per watt of power used in generalpurpose processors and DSPs.
Performance
kIPS 1980
1990
2000
2010
Calendar year
48
Roadmap for the Rest of the Book

Fasten your seatbelts as we begin our ride! Ch. 5-8: A simple ISA, variations in ISA Ch. 9-12: ALU design Ch. 13-14: Data path and control unit design Ch. 15-16: Pipelining and its limits Ch. 17-20: Memory (main, mass, cache, virtual) Ch. 21-24: I/O, buses, interrupts, interfacing Ch. 25-28: Vector and parallel processing
49

02-Computer System Technology

Caricato da

Informazioni sul documento

Copyright

Formati disponibili

Condividi questo documento

Condividi o incorpora il documento

Opzioni di condivisione

Hai trovato utile questo documento?

Questo contenuto è inappropriato?

Copyright:

Formati disponibili

02-Computer System Technology

Caricato da

Copyright:

Formati disponibili

Computer System Technology

Levels of Representation (abstractions)

temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw lw sw sw

$t0, 0($2) $t1, 4($2) $t1, 0($2) $t0, 4($2)

From Components to Applications

Computer archit ecture Computer organization

Subfields or views in computer system engineering.

Computer Architecture, Background and Motivation

What Is (Computer) Architecture?

Goals Interface Means

Construction tec hnology: material, codes, . . .

The world of arts: aesthetics, trends, . . .

Computer Architecture, Background and Motivation

Computer Systems and Their Parts

Classifying computers by computational power and price range.

Automotive Embedded Computers

Cent ral controller Navigation & entert ainment

Personal Computers and Workstations

Computer Architecture, Background and Motivation

Digital Computer Subsystems

Processor Memory I/O devices technology innovations introduced

Dominant look & fell

Disk, keyboard, Desk-size video monitor mini Desktop/ laptop micro

SRAM/DRAM Network, CD, mouse,sound SDRAM, flash

Sensor/actuator, Invisible, point/click embedded

Computer Architecture, Background and Motivation

IC Production and Yield

Patterned wafer Processing: 20-30 steps

Silicon crystal ingot

0.2 cm Good die Microchip or other part Mounting

(100s of simple or scores of complex processors)

Usable part to ship

The manufacturing process for an IC part.

Computer Architecture, Background and Motivation

Effect of Die Size on Yield

120 dies, 109 good

Visualizing the dramatic decrease in yield with larger dies.

Computer Architecture, Background and Motivation

Processor and Memory Technologies

Backplane PC board Die

(b) 3D packaging of the future

Packaging of processor, memory, and other components.

Computer Architecture, Background and Motivation

Trends in processor performance and DRAM memory chip capacity

Memory chip capacity

Pitfalls of Computer Technology Forecasting

Input/Output and Communications

Magnetic tape cartridge

(b) Some removable storage media

Magnetic and optical disk memory units.

Computer Architecture, Background and Motivation

10 6 Same geographic location

Wide-area network (WAN)

Software Systems and Applications

System Operating system Enabler:

Categorization of software, with examples in each class.

Computer Architecture, Background and Motivation

High- vs Low-Level Programming

Swap v[i] and v[i+1]

temp=v[i] v[i]=v[i+1] v[i+1]=temp

add add add lw lw sw sw jr

$2,$5,$5 $2,$2,$2 $2,$4,$2 $15,0($2) $16,4($2) $16,0($2) $15,4($2) $31

Very high-level language objectives or tasks

High-level language statements