Application Note Mw3 Dft-V4-Es

DSCH APPLICATION NOTE Fault Testing in Dsch
Page 1/18) etienne.sicard@insa-toulouse.fr 01/09/10

Introducing Fault Testing in Dsch version 3.5

Etienne SICARD
Professor
INSA-Dgei, 135 Av de Rangueil
31077 Toulouse France
www.microwind.org
email: Etienne.sicard@insa-toulouse.fr
Belgacem HAMDI
Assistant Professor
Laboratoire dElectronique et MicroElectroniqe
Monastir Tunisie
email: belgacem.hamdi@yahoo.fr

This document introduces concepts for fault testing at logic level in Dsch35. The mechanisms for logic
fault injection and simulation is described. The testing features of Dsch35 are illustrated with a Full
Adder logic design.

1 INTRODUCTION
Design of logic integrated circuits in CMOS technology is becoming more and more complex since
VLSI is the interest of many electronic IC users and manufacturers. A common problem to be solved
by designers, manufacturers and users is the testing of these Ics.
1.1 Typical IC production flow

Wafer Probe Test Packaging
Marking Final Test
Visual
inspection
QA sample
Test
Shipping

Figure 1: typical IC production flow
Testing can be expressed by checking if the outputs of a functional system (functional block,
Integrated Circuit, Printed Circuit Board or a complete system) correspond to the inputs applied to it.
If the test of this functional system is positive, then the system is good for use. If the outputs are
different than expected, then the system has a problem: so either the system is rejected (Go/No Go
test), or a diagnosis is applied to it, in order to point out and probably eliminate the problem's causes.
Testing is applied to detect faults after several operations: design, manufacturing, packaging and
during the active life of a system.
Design for Testability (DfT) is the ability of simplifying the test of any system. DfT could be
synthesized by a set of techniques and design guidelines where the goals are:
minimizing costs of system production
minimizing system test complexity : test generation and application
improving quality and reliability
In the production process cycle, a fault can occur at the chip level. If a test strategy is considered at the
beginning of the design, then the fault could be detected rapidly, located and eliminated at a very low
cost. When the faulty chip is soldered on a printed circuit board, the cost of fault remedy would be
multiplied by ten. And this cost factors continues to apply until the system has been assembled and
packaged and then sent to users.

..
10
..
10
10

..
Test cost
Chip level
Board level
System level
System level at
field
Test
economy

Figure 2: Test cost (The rule of ten)
1.2 Scope of testing
1.2.1 Engineering Test

The engineering test is a Diagnostic Test witch deals with Fault location, Failure analysis and Design
and/or process debugging

1.2.2 Manufacturing Test

Manufacturing Test is a Characterization Test
Performance characterization: parametric test (fig. 3)
Reliability characterization: bathtub curve (aging)


max
min
Measurement in spec
Test OK
Measurement lower
than minimum spec
Test KO
Vd
Id

Figure 3: parametric test

1.2.3 Production Test
Simple parametric test
Functional test
Reliability screening (burn-in)

2 Fault testing
2.1 Types of Faults
Fault: a physical defection a circuit/system
Permanent fault: a fault that is continuous and stable, whose nature do not change before,
during, and after testing
Affecting the functional behaviour of the system permanently
A.k.a. hard fault or solid fault
Usually quite localized
Can be modeled
Temporary fault: a fault that is present only part of the time, occurring at random moments
and affecting the system for finite, but unknown, intervals of time
Transient fault: caused by environmental conditions
No well-defined fault model
Called soft error in RAM
Often assumed no permanent damage was done
Intermittent fault: caused by non-environmental conditions
Often repeatable
Can use permanent fault models and repeated test with stress
2.2 Fault Model and Error
The Fault model can be definite as the logical effect of a fault. Error is the manifestation of a fault that
results in an incorrect module output or system state. Faults can be classed into two categories:
2.2.1 Structure faults
Stuck-at faults: stuck-at-0 and stuck-at-1
Bridging (short) fault
Open (break) fault

Transistor stuck-on and stuck-open faults
Transition and delay faults
2.2.2 Functional faults
RAM coupling and pattern-sensitive faults
PLA cross-point faults

2.3 Failure
Failure: deviation of a system from its specified behaviour
Fault error failure
Failure mechanism: physical or chemical process that causes devices to malfunction; they manifest
themselves on the circuit level as failure modes
Failure mode: the cause of rejection of failed device (effect of failure mechanism), such as
open/short interconnections, or degraded parameter values

2.4 Testing and fault coverage
Testing is the process of determining whether a device functions correctly or not
How much testing of an IC is enough?
Yield (Y) is the ratio of the number of good dies per wafer to the number of dies per wafer
Fault coverage (FC) is the measure of the ability of a test set T to detect a given set of faults that
may occur on the DUT (Device Under Test)
FC= (#detected faults)/(#possible faults)
2.5 Defect level and fault coverage
Defect level (DL) is the fraction of bad parts among the parts that pass all tests.
DL= 1 Y
(1-FC)

Where FC refers to the real defect coverage (probability that T detects any possible fault in F or not)
and DL is the DPM (defects per million). Typical values claimed are less than 200 DPM, or 0.02%.

2.6 The testing problem
The first idea to test an N input circuit would be to apply an N-bit counter to the inputs
(controllability), then generate all the 2N combinations, and observe the outputs for checking
(observability). This is called "exhaustive testing", and it is very efficient, but only for few- input
circuits. However, this technique becomes very time consuming when the input number increases.

Exhaustive testing
N inputs 2
N
Combinaisons
100 MHz tester:
32 inputs 0,7 Minutes

40 inputs 3 Hours

64 inputs 58 Centuries!!

The question is: Given a set of faults in the circuit under test (CUT), how do we obtain a certain
(small) number of test patterns which guarantees a certain (high) fault coverage?
What faults to test? (fault model)
How are test patterns obtained? (test pattern generation)
How is test quality (fault coverage) measured? (fault simulation)
How are test vectors applied and results evaluated? (ATE/BIST)
(ATE: Automatic Test Engine; BIST: Built In Self Test).

2.7 Fault Modeling: Stuck Fault Modeling: Stuck-at Fault
Single (line) stuck-at fault: line has a constant value (0/1)
Multiple stuck faults: several single stuck-at faults occur at the same time
(For a circuit with k lines (Nodes), there are 2k single stuck faults, and 3
k
-1 multiple stuck faults)
A test for a fault f in circuit C is an input combination for which the output(s) of C is different when f
is present than when it is not.


Faulty system
Test pattern
Defect
Fault free system
Fault

A test vector x detects fault f iff
C(x) C
f
(x) = 1
Where: C(x) is the response of the fault free circuit, and C
f
(x) is the response of the faulty circuit)
A test set for a class of faults F is a set of tests T such that for any fault fF, there exists at least a
vector tT such that t detects f.

Example

Fault
C
b
a Fault f: C stuck-at 0; C s-a-0; C s/0; C/0
or C@0
Vector 111 is a test vector of the Fault f

a b C(correct) C
f
(a@0) C
f
(a@1) C
f
(b@0) C
f
(b@1) C
f
(C@0) C
f
(C@1)
0 0 0 0 0 0 0 0 1
0 1 0 0 1 0 0 0 1
1 0 0 0 0 0 1 0 1
1 1 1 0 1 0 1 0 1

2.8 Fault diagnosis
Fault detection: tells only whether a circuit is fault-free or not
Fault identification (location; isolation): provides the location and the type of the detected fault and
other related information
Fault diagnosis: includes both fault detection and fault identification

2.9 Testing
Testing is a process which includes test pattern generation, test pattern application, and output
evaluation
The quality of a test set depends on its fault coverage(FC) as well as its size
FC (typically 98-99% single stuck faults) can be determined by fault simulation
2.10 Fault Collapsing
Stuck-at fault collapsing typically reduces the total number of faults by 50 to 60% [Bushnell 2000].
Fault collapsing for stuck-at faults is based on the fact that a SA0 at the input to an AND (NAND) gate
is equivalent to the S@0 (S@1) at the output of the gate. Similarly, a S@1 at the input to an OR
(NOR) gate is equivalent to the S@1 (S@0) at the output of the gate. For an inverter, a S@0 (S@1) at
the input is equivalent to the SA1 (S@0) at the output of the inverter. Furthermore, a stuck-at fault at
the source (output of the driving gate) of a fanout-free net is equivalent to the same stuck-at fault at the
destination (gate input being driven). Therefore, the number of collapsed stuck-at faults in any
combinational circuit constructed from elementary logic gates (AND, OR, NAND, NOR, and inverter)
is given by:
Number of collapsed faults = 2(number of POs+number of fanout stems)
+ total number of gate (including inverter) inputs
total number of inverters
A number of interesting properties are associated with detecting stuck-at faults in combinational logic
circuits; for example, two such properties are described by the following theorems:
Theorem 1
A set of test vectors that detects all single stuck-at faults on all primary inputs of a fanout-free
combinational logic circuit will detect all single stuck-at faults in that circuit.
Theorem 2
A set of test vectors that detect all single stuck-at faults on all primary inputs and all fanout branches
of a combinational logic circuit will detect all single stuck-at faults in that circuit.

Example:

Y

a
b
c
e
f
g

h
i
d
X
1
X
2
X
3

This example circuit has one primary output and one fanout stem. The total number of gate inputs is 7,
including the input to the one inverter; therefore,
The number of collapsed faults = 2(1+1)+71 = 10.
Note that single-input gates, including buffers, are treated the same as an inverter in the calculation of
the number of collapsed faults because all faults at the input of the gate are equivalent to faults at the
output.

2.11 Test Compaction
Test compaction refers to the process of reducing the number of test patterns in a test set without
reducing its fault coverage. Equivalence fault collapsing and dominance fault collapsing are used to
aid test compaction

3 Test Module in DSCH
3.1 Tool specification

Cancel
NEXT
DFT & Fault
Analysis


faddDFT.sch
successefully generated
Cancel
NEXT

3.2 Manual Test Flow

3.3 Automatic Test Flow


4 Case study on Dsch35: Full Adder

4.1 Generating the reference truth table
A

B
C

Carry

Out

4.2 Stuck-at-0/Stuck-at-1fault injection

The fault injection and fault simulation at a node N consists to open the connection (A,B) and replace
it by the circuit of the figure below (for the simulation (in Dsch3) Muxes should be with a nil delay
because they just serve to simulate a stuck-at fault at the node N).

V
ss

Node N
A (normal data)
B
A
B
V
dd

Fault injection Mode
A
B
s@0/s@1
Fault
injection

4.3 Test Vector Reduction
Test vector reduction consists to find the minimum set of test vectors which detects all single stuck-at
faults.
Test vector reduction is the bsed on the following rules and theorems:
a. For AND gate, all s/0 faults are equivalent.
b. For OR gate all s/1 faults are equivalent.
c. Any test which detects will also detects : Need not consider
d. Equivalence fault collapsing + dominance fault collapsing => only (n+1) faults on any n-
input gate need be considered.
e. Theorem: In a fanout free combinational circuit, any test set which detects all stuck faults on
primary inputs will detect all stuck faults.
f. Definition: The set of all primary inputs and all fanout branches are called the checkpoints of
the circuit.
g. Theorem: In a combinational circuit, any test set which detects all single (multiple) stuck
faults on check points will detect all single (multiple) stuck faults.
<belgacem> The sequence of test vector can be also arranged with the minimun number of transitions
in order to minimize power consumption when the test is applied to the ciruit (ATE, BIST, LFSR).
This can be added to Dsch3.5 DFT tool.
4.4 Full Adder with redundancy:

X

Out
A

B

C

Carry

Stuck-at 0 and stuck-at 1 at the node X are not detectable thanks to redundancy. The full adder
performs corrects outputs even with fault at the node X.

4.5 Other tutorials
4.5.1 Exemple 1
The following circuit has 5 nodes, therefore 10 possible stuck-at faults. Lets consider the fault
injection at the node X.

X
C
B
A
Out

Figure 4 (a): Exemple circuit 1

A
B
C
Out

Figure 4(b): Simulation of the fault free circuit

X
C
B
A
out
Fault
injection
V
ss

X
(normal data)
Y
V
dd

s@0/s@1
Fault injection
Mode
Y

Figure 5: fault injection at the node X

s@0 fault
injection
s@0 fault
injection
Fault Injection=0: Normal Function Mode
Fault Injection=1: Test Mode
A
B
C
Fault
injection
Fault type
Out

Figure 6: Dsch3.5 Simulation of the circuit with fault injection

A B C Out
Fault-Free
Out
A@0
Out
A@1
Out
B@0
Out
B@1
Out
C@0
Out
C@1
Out
X@0
Out
X@1
Out
S@0
Out
S@1
0 0 0 1 1 1 1 1 1 1 0 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 0 1
0 1 0 1 1 0 1 1 1 1 0 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0 1
1 0 0 1 1 1 1 0 1 1 0 1 0 1
1 0 1 1 1 1 1 1 1 1 1 1 0 1
1 1 0 0 1 0 1 0 0 1 0 1 0 1
1 1 1 1 1 1 1 1 0 1 1 1 0 1

Table 1: Truth Tables for Fault-Free and Faulty Circuits of Figure 4(a)

The vector 110 detects A@0, B@0, C@1, X@1 and S@1 (5/10 faults).
The vector 100 detects B@1, X@0 and S@0 (3/10 faults).
The vector 010 detects A@1, X@0 and S@0 (1/10 faults).
The vector 111detects the remaining fault C@0.
Therefore 4 test vectors (110, 100, 010, 111) detect all stuck-at faults (test time will be the half of an
exhaustive test).
4.5.2 Exemple 2
Lets consider the following circuit (Multiplexer)

Y

a
b
c
e
f
g

h
i
d
X
1
X
2
X
3

Figure 6: Example 2 circuit

X
1
X
2
X
3
000 001 010 011 100 101 110 111
Y (fault-free) 0 1 0 0 0 1 1 1
aS@0 0 1 0 0 0 1 0 0
aS@1 0 1 1 1 0 1 1 1
bS@0 0 1 0 1 0 1 0 1
bS@1 0 0 0 0 1 1 1 1
cS@0 0 0 0 0 0 0 1 1
cS@1 1 1 0 0 1 1 1 1
dS@0 0 1 0 0 0 1 0 0
dS@1 0 1 0 0 1 1 1 1
eS@0 0 1 0 1 0 1 1 1
eS@1 0 0 0 0 0 0 1 1
fS@0 0 0 0 0 0 0 1 1
fS@1 0 1 0 1 0 1 1 1
gS@0 0 1 0 0 0 1 0 0
gS@1 1 1 1 1 1 1 1 1
hS@0 0 0 0 0 0 0 1 1
hS@1 1 1 1 1 1 1 1 1
iS@0 0 0 0 0 0 0 0 0
iS@1 1 1 1 1 1 1 1 1
Table 2: Truth Tables for Fault-Free and Faulty Circuits of Figure 6

The truth table entries where the faulty circuit produces an output response different from that of the
fault-free circuit are highlighted in gray. As a result, the input values for the highlighted truth table
entries represent valid test vectors to detect the associated stuck-at faults. With the exception of line d
S@1, line e S@0, and line f S@1, all other faults can be detected with two or more test vectors;
therefore, test vectors 011 and 100 must be included in any set of test vectors that will obtain 100%
fault coverage for this circuit. These two test vectors detect a total of ten faults, and the remaining
eight faults can be detected with test vectors 001 and 110; therefore, this set of four test vectors
obtains 100% single stuck-at fault coverage for this circuit.
Four sets of equivalent faults can be observed in Table 2. One fault from each set can be used to
represent all of the equivalent faults in that set. Because there is a total of ten unique faulty responses
to the complete set of input test patterns, then ten faults constitute the set of collapsed faults for the
circuit.
Therefore, test vectors for Example 2 circuit are 011; 100; 001 and 110.


5 References
[Chen2002] Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU 2002
[Sicard2005a] E. Sicard, S. Ben Dhia Basic CMOS cell design, McGraw Hill India, 450 pages,
ISBN 0-07-0599335, June 2005 (international edition to appear 2007)
[Sicard2005b] E. Sicard Introducing 90-nm technology in Microwind3, application note, July 2005,
www.microwind.org
[Sicard2006a] E. Sicard Microwind Users Manual, lite version 3.1, www.microwind.org, INSA
editor, 2006
[Sicard2006b] E. Sicard Introducing 65-nm technology in Microwind3, application note, July 2006,
www.microwind.org

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