Government Engineering College Kozhikode-5

Analog Electronics Lab Manual AI09 407(P)

(Version 0.8j - 11-02-2012)

Prepared by:- Mohammed Sadik(2010 AEI batch) <sadiqpkp(at)gmail(dot)com> Mansoor M (2008 AEI batch) <mansoormanzu(at)gmail(dot)com> Guided by :- Smt. Subhija(Asst. Professor)

Veried by:- Smt. Subhija(Asst. Professor)/ FIX ME /

A Type set in L TEX 2 by Mohammed Sadik.

Circuit designed in circuit by Mohammed Sadik and Mansoor M. Graphs plotted with circuit and gnuplot. Platform : GNU/Linux Other free softwares used: GNU Bash, GNU Emacs.. . . . . .

This work is licensed under : Creative Commons Attribution-ShareAlike 3.0 License. To view a copy of this license, visit http://creativecommons.org/licenses/by-sa/3.0/ or send a letter to Creative Commons, 444 Castro Street, Suite 900, Mountain View, California, 94041, USA.

Thanks to:1. 2. 3. 4. 5. 6. 7. 8. The principal, GECK HOD-Applied Electronics Dr. Reena P(Associate Professor(ECE)) Smt. Subhija madam Najmudheen (Cherumukku) Musthafa M(AEI 2010 Batch) Jithin(AEI 2010 Batch) Jeeson(AEI 2010 Batch)

CONTENTS
Transistor Circuits
1. 2. 3. 4. 5. 6. 7. Power amplier circuits - Class B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Schmitt trigger circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RC phase shift oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 RC low pass and high pass lters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Astable multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bootstrap sweep circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Tuned amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Op-Amp Circuits
8. 9. 10. 11. 12. 13. 14. Op-amp - Basic operational circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Measurement of Op-Amp parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Dierentiators and integrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Astable and monostable multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Second order low pass and high pass lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Wien bridge oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Precision rectier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

PSPICE
15. 15a. 15b. 15c. 15d. 15e. 15f. 15g. 15h. 15i. 15j. PSPICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Inverting amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Non-inverting amplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Voltage follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Astable multivibrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Zero crossing detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 RC low pass lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 RC high pass lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Second order high pass lter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Frequency response of Op-AmpIntegrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Frequency response of Op-AmpDierentiator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

meet me at https://launchpad.net/sadiq

Experiment 1

CIRCUIT DIAGRAM
VCC +6V

470F + CC D1 D2 VS 20Hz 2VPP + CC 470F

R 1k T2 SL100 1N 4001 1N 4001 T1 SK100 R 1k RL 22 CC 470F VO

Expected graph
I

Vo

Experiment 1

POWER AMPLIFIER CIRCUITS CLASS B

AIM
To setup and study the working of a complementary symmetry class B push-pull audio power amplier.

COMPONENTS AND EQUIPMENTS REQUIRED

Transistors, diodes, capacitors, resistors, potentiometer, bread board, connecting wires, DC source, signal generators and CRO.

THEORY
In class B power ampliers, the collector current ows for 180 of the input cycle. Class B operation means the Q point is at the cut o. A complementary pair of NPN and PNP transistors with identical characteristics is used in complementary symmetry class B power amplier. They are connected as emitter follower in push-pull arrangement. Pushpull means one transistor drives current through load in one direction(ie, pushing), while the other transistor drives current in opposite direction(ie,pulling). These ampliers are of less cost and bulkiness due to no need of input transformer for phase splitting. When the input is in +ve half cycle, the base of transistor T2 (NPN) is driven +ve related to emitter. So the transistor becomes in ON state. Where as the other transistor T1 (PNP) is OFF. During the -ve half cycle it happens vice versa. Now the output current ows in the opposite direction and its amplitude is same as that of input due to unit gain. Compensating diodes are used to avoid thermal run away, which is due to the sensitivity of collector current with temperature. The bias current through the diodes must be same as that of the quiescent collector current. That is, diode curves should match with VBE curves of the transistors. Here, the transistor will start conducting only when input is greater than 0.6V. So the output voltage distorts near zero crossing. This distortion is known as cross over distortion. This can be eliminated by connecting a resistance RB in series with diodes. The voltage developed across the resister drives the transistor into class AB operation. Because the operating point moves towards class A operating point slightly. To couple a lower impedance at low frequency, a high value coupling capacitor is required.

Design:
Design of class B power amplier using single power supply: i. Selection of transistors: Select complementary pair transistors SK100 as T1 and SL100 as T2 . 2N3055 and MJ2955 are also high power complementary pair transistors. ii. Selection of diode: Select diodes 1N4001. Diodes and transistors should be made of same material because the diodes are compensating the VBE of transistors. iii. Selection of RL : 2 Vp Output power= 2R L Vp = Vin = 1V because the amplier is an emitter follower 25mW = Then RL = 20 use 22 std.

1 2RL

iv. Design R: The bias current through the compensating diodes ID is same as the ICQ in order to match the diode curves and VBE curves of the transistors. ICQ should be 1 to 5% of ICsat . VCEQ 3 Average current ICsat = R = R = 43mA L L ID = (VCC VBE )/2R since ICQ = ID = ICsat 5% = 2.15mA R = 1.1k, use 1k std. v. Selection of coupling capacitor Cc : RL Cc > Ts , where Ts is the lowest signal frequency. 1 Cc = 220 = 360F . Use 470F std. RL

PROCEDURE
1. Test all components. Setup the class B power amplier circuit using dual power supply as shown in gure. Short the diodes and observe the cross over distortion on CRO screen. 2. Apply an input of low frequency 2Vpp sine wave. Observe the input and output waveforms on the CRO screen. Using the expression Vp2 /2RL , calculate ac power delivered to the load. 3. Repeat the same for class A power amplier circuit using single power supply. Observe that the cross over distortion is still present slightly. 4. Repeat the experiment for class AB amplier and observe that the cross over distortion is eliminated.

RESULT
Class B power amplier is designed, and is setup on bread board and input and output waveforms are observed on CRO.

Experiment 2

VCC 12V 0.1F C1 R1 Q1 BC107 22k 27k Q2 BC107 R2 IE2

RC1 5.6k RB 33k Vin 20VPP RE

RC2

2.7k VO

2k

Design:
Let Q1 , Q2 = BC 107, VCC = 12V, = 100, UTP = 6V, LTP = 4V, RE = 2.2k Design of RE : UTP = IE2 RE + VBE = 6V LTP = IE1 RE + VBE = 4V Choose RE = 2.2 IE1 = (4 0.7)/2.2 = 1.5mA IE2 = (6 0.7)/2.2 = 2.4mA Design of RB : It is current limiting factor gain given by Vin = peak input voltage = 10V VB = maximum voltage at the base of Q2 2. 4 IC = 2.4A IB2min = 2 = hf e 100 10 6 RB = = 33k 120 Design of RC1 and RC2 , where Q1 is ON: VCC IE1 RE1 VCEsat RC 1 = I E1 12 1.5 103 2.2 0.2 = 1.5 103 = 5. 6k Vin VB IB

Experiment 2

SCHMITT TRIGGER
AIM
To setup a schmitt trigger circuit for a UTP of 6V and an LTP of 4V.

COMPONENTS AND EQUIPMENTS REQUIRED

Transistor, resistor, capacitors, signal generators, connecting wires, bread board, DC power source, and CRO.

THEORY
If a cross coupling of bistable multivibrator is removed and its emitter is coupled, it becomes schmitt trigger. It is a comparator used to convert a periodical random wave to a square wave of same frequency. So schmitt trigger is called a squaring circuit. Output of the schmitt trigger goes to high level when the amplitude of the input signal goes above a pre-determined level called Upper Threshold Point or Upper Triggering Point(UTP). The output goes to low level when the input signal goes below a predetermined level called Lower Threshold Point or Lower Triggering Point(LTP). The schmitt trigger is also known as two level comparator, since it compares the input analog waveform with respect to the preset values UTP and LTP. With no input, transistor Q1 stays in cut o state and Q2 in saturation state. Current IE2 ows through the common emitter resister RE causing a potential drop equal to IE2 RE . Now the minimum voltage required to make Q1 ON(ie,UTP) is equal to VBE1 + IE2 RE . When the input amplitude increases and reaches UTP, Q2 turns ON. Subsequently Q2 turns OFF and the output rises to VCC . Now, current IE2 becomes zero and IE1 starts owing through RE . The minimum voltage required to hold the transistor Q1 ON(ie,LTP) is equal to VBEcutin + IE1 RE . When the amplitude of the input sine wave becomes less than this, Q1 turns OFF, in turn Q2 turns on and the output voltage drops. RC2 is made smaller than RC1 to make IE2 > IE1 .

PROCEDURE

1. Test the components, devices and probes. Setup the circuit. 2. Switch on power supply, and observe VC1 and VC2 without any input. Verify whether VC2 is low and VC1 is high. 3. Apply 20 VP P , 1 kHz sine wave at the input and observe the output waveform. 4. Keep the time/div knob of CRO in x-y mode and feed Vin to the x-channel and Vo to the y -channel. Observe the hysteresis curve on CRO.

Where Q2 is ON: VCC IE2 RE VCEsat RC 2 = I E2 12 2.4 103 2.2k 0.2 = 2.4 103 = 2. 7k 2. 4 IC = 2.4A = IB ows Q2 = hf e 100 Let IB ows through R1 and 9IB ows through R2 . 9IB R2 =VBE IE2 RE VBE + IE2 RE R2 = 9I B R2 0. 7 + 2. 4 2. 2 R2 = 9 24 106 =27k Design of speed capacitor C1 : C1 R2 = CRB2 , where C is base emitter capacitance of the transistor and is kept as per data of BC107, use 4.7pf .

10

RESULT
Schmitt trigger circuit for a UTP of 6V and LTP of 4V is set up on a bread board and input and output waveform are observed on CRO.

Excpected graphs

11

Experiment 3

CIRCUIT DIAGRAM
VCC 12V 0.01F CC + -

47k

R1

RC 2.2k BC107

0.01F 0.01F 0.01F C C C

10k R2

RE 680

4.7k + C - 22F

R R

4.7k R 4.7k

Excpected graph

12

Experiment 3

RC PHASE SHIFT OSCILLATOR

AIM
To design and setup RC phase shift oscillator using BJT to generate a sinusoidal waveform of 1KHz frequency.

COMPONENTS REQUIRED
Transistor, resistors, capacitors, bread board, DC source and CRO.

THEORY
An oscillator is a circuit that generates ac signals from a dc input. An oscillator requires an amplier, a frequency selective network and a positive feedback from the output to the input. Barkhausen criterion for sustained oscillator is A = 1, where A is the gain of the amplier and be a feedback factor. If a common emitter amplier is used, there is a 180 phase shift between the base and collector voltages. The collector to base Feedback network must introduce an additional phase shift of 180 at a particular frequency. Here 3 sections of RC network(phase shift oscillator network) are used so that each section introduce approximate 60 phase shift at resonant frequency. 1 2RC = 6+
4RC R

F =

1 if RC = R 2RC 10

The three sections of network oers a of

1 . 29

Hence the gain should be 29. For this,

RC R

R hf e 23 + 29 RC +4 56 if Rc = R

Phase shift oscillator useful in the audio frequency range(ie, upto 20KHz).

13

Design
i. ii. Output requirements: Sine wave with amplitude 10Vpp and 1KHz Design of the amplier: Select the transistor BC 107. It can provide a gain more than 29 because its minimum hf e = 100

iii. DC biasing conditions: VCC = 12V, IC = 2mA, VRC = 40% of VCC = 4.8A VRE = 10% of VCC = 1.2V VCE = 50% of VCC = 6V VCC is taken as 20% additional to the required output peak value. iv. Design of RC : VRC = IC RC = 4.8V from this, RC = 2.4k , use 2.2k std. v. Design of RE : VRE = IE RE = 1.2V from this, RE = 600, use 680 std.

vi. Design of voltage divider R1 and R2 : From the data sheet of BC107, its hf e(min) = 100 IC 2mA IB = = 20A = hf e 100 Assume the current through R1 = 10IB and that through R2 = 9IB , to avoid loading the potential divider by the bias current. VR2 = voltage across R2 = VBE + VRE = 0. 7 + 1. 2 = 1. 9V 1. 9 Also, VR2 = 9IB R2 = 1.9V Then R2 = = 10.6k , use 10k std. 9 20 106 VR1 = Voltage across R1 = VCC VR2 = 12 1.9 = 10.1V 10.1 = 50.5k , use 47k std. Also, VR1 = 10IB R1 = 10.1V s Then R1 = 10 20 106 vii. Design of a frequency selective network: Required frequency of oscillator is 1KHz. 1 f = = 1KHz . Take R = 4.7k to avoid loading of RC by RC Rc 2RC 6 + 4 R network. Then C = 0.01F . Use 4.7k in the last RC stage. viii. Design of bypass capacitors, CE : ie, XCE
RE . 10

Then CE

1 = 23F 22F (assuming fL = 100Hz) 2 10 68

14

PROCEDURE
Check the transistor. Connect the resistive components and give power supply. Check the dc bias conditions so that transistor must operate in active region. Connect the RC network. VBC should be zero or less. Connect the feedback network and observe the sine wave on CRO screen and measure its amplitude and frequency. Observe the waveform at the base and collector of the transistor simultaneously on CRO screen and notice the phase dierence between them.

RESULT
RC phase shift oscillator using BJT is designed and setup on a bread board and output waveform is observed on CRO.

15

Experiment 4

RC low pass lter

RC high pass lter

VO

R 6.8 C 0.022F VO

R 6.8 C 0.022F

Vin 5VPP

Vin 5VPP

Design
1 we have fH = 2RC Let R = 10 times the output impedence of the function generator ie, R = 6000 6.8k C = 0.023F 0.022F Let fH = 1KHz Let fL = 1KHz

Design
1 2RC Let R = 10 times the output impedence of the function generator ie, R = 6000 6.8k C = 0.023F 0.022F we have fL =

OBSERVATIONS RC low pass lter

f log f Vo Gain(dB)

RC high pass lter

f log f Vo Gain(dB)

16

Experiment 4

RC LOW PASS AND HIGH PASS FILTERS

AIM
To design and setup low pass and high pass circuit for a 3dB frequency of 1KHz and study the frequency response.

COMPONENTS AND EQUIPMENTS REQUIRED

Capacitor, resistor, bread board, signal generator and CRO.

THEORY
Filters are the network designed to pass only certain frequency band. It can be broadly classied as passive or active lters, according to the device used to implement them, lters can also be classied according to the frequency spectrum it passes. Such as low pass, high pass, band pass and band reject lter. A passive low pass lter is shown in gure, it passes low frequency readily and attenuates high frequencies. Since the reactance of the capacitor C decreases with increase in frequency, at high frequency the capacitor act as virtual short and output falls to zero for a sinusoidal input Vin , the output Vo will decrease with increase in frequency, the magnitude of the ratio of output voltage to input voltage of the circuit is given by A= 1 1+
1 , Higher cuto frequency. fH = 2RC f =Input signal frequency. f fH 2

A high pass lter can be made from the low pass lter by merely interchanging its resister and capacitor. However their values are dierent from that of a low pass lter. Since the reactance of the capacitor decreases with increase in frequency, the higher frequency in the input region appear at the output with less attinuation than the lower frequency component. The magnitude of the output voltage to input voltage of the circuit is given by 1 A= 1+
1 fL = 2RC , Lower cuto frequency. f =Input signal frequency. fL f 2

17

Graphs to be plotted

RC low pass lter fH

(Hz )

3dB Av (dB ) RC high pass lter fL

(Hz )

3dB Av (dB )

18

PROCEDURE

1. Setup the circuit and set the input sine-wave volt at 5Vpp and observe the input and output on the two channels of the CRO. 2. Vary the input frequency from 10 Hz to 100KHz or more and note down the output volt in the tabular column. 3. Plot the graph on a semi log graph sheet with f along x-axis and gain in dB along y -axis. 4. Mark a point on the graph sheet at a 3dB less than the maximum gain. Extend the point to the x-axis and mark the lower 3dB frequency.

RESULT
Designed and setup RC low pass and high pass lters and the waveform are plotted. 1. The 3dB frequency of the RC low pass lter = . . . . . . . . . 2. The 3dB frequency of the RC high pass lter = . . . . . . . . .

19

Experiment 5

Astable multivibrator
Vcc +9V RC1 4.7k C1 0.01F Q1 BC107 R1 82k 82k R2 C2 0.022F VB1 VB2 Q2 BC107 RC2 4.7k

20

Experiment 5

ASTABLE MULTIVIBRATOR
AIM
To design and setup an Astable multivibrator using transistors, study its performance and observe the wave form at various points of it.

COMPONENTS AND EQUIPMENTS REQUIRED

Transistors, resistors, capacitors, bread board and DC supply.

THEORY
Astable multivibrator is also called free running oscillator. It does not have a stable state. The circuit transmit from one quasi-stable state to the other and back automatically. Depending up on the charging and discharging periods of two timing capacitors. When one transistors is ON state, other remains in OFF state, both will not be in the same state at the same time. The collector voltage of ON transistor is approximately 0.3V and that of OFF transistor is the Vcc supply. Suppose, transistor Q1 is OFF and transistor Q2 is OFF, then the capacitor C2 (whose left side was at potential - IC2 RC2 ) starts charging to Vcc through R2 and Q2 . When the potential at left side of the capacitor become the cutting voltage(0.6V), Q1 starts conducting after a sudden over shoot in potential at the base of Q1 , it settles at 0.7V, when Q1 conducts, Q2 goes to OFF state due to regenerative action. Thus the time duration in which Q2 remains in ON state(as well as Q1 remains in OFF state) is given by the expression T2 = 0.69R2 C2 . Sudden conduction of Q1 causes a potential drop of IC1 RC1 at the collector of Q1 . This sudden change gets transferred to the base of Q2 causing potential of 0.7V IC1 RC1 at the right side of the capacitor C1 . Now C1 start to charge to VCC through R1 &R2 . When the potential at the right side of the capacitor C1 reaches cutting voltage, Q2 starts conducting resulting sudden voltage drop of IC2 RC2 transfer from collector of Q2 to the base of Q1 . the base potential of Q1 is then 0.7V IC2 RC2 . This cycle repeats. Time duration in which Q1 remains ON(as well as Q2 remains in OFF state) is given by the expression T1 = 0.69R1 C1 .

21

Design:
Output requirements: A square wave of amplitude 9V, frequency 1KHz and duty cycle = 1/3. Choose transistor BC 107 Take VCC = 9V, since the amplitude of the square wave required is 9V. T = T1 + T2 = 1ms Since duty cycle = 1 T1 = , we get T1 + T2 3 T1 0.33ms T2 0.66ms

Design of RC1 and RC2 : RC 1 =

VCC VCE1 sat = 4.35k , use 4.7k std. IC1 sat Take RC1 = RC2 = 4.7k Design of R1 and R2 : The resistors R1 and R2 must be able to provide base current enough to keep the transistors in saturation. IC 2mA IB min = = = 20A hf e hf e Consider an over-driving factor of 5, so that transistor will be indeed in saturation. Then actual base current IB = 5IB textmin = 0.1mA VCC VBE sat R1 = = 83k, use 82k std. for R1 and R2 0.1mA R1 and R2 should be less than hf e RC , condition satises in the above design. Design of C1 and C2 : T1 = 0.33ms = 0.69 R1 C1 . Then C1 = 0.006F, use 0.01F std. T2 = 0.66ms = 0.69 R2 C2 . Then C2 = 0.02F, use 0.022F std.

22

If R1 = R2 = R and C1 = C2 = C, T1 = T2 = 0.693RC The time period of the output signal T = T1 + T2 1.38RC .

PROCEDURE

1. Verify the connections of all components, device and probes. 2. Set up the circuit observe the collector and base waveforms of both the transistors.

RESULT
Designed and set up the Astable multivibrator and the waveforms are plotted.

23

Experiment 6

Bootstrap sweep circuit

Vcc D +10V 1N4001 + C1 47F R 5.6k

RB 100k 10F CB - + Vin 10VPP

Q2 BC107 VO RE 4.7k -VEE

Q1 BC107

C2 0.1F

Design:
Outupt requirements: Amplitude and time period of sawtooth waveform = 10V, 1ms. DC bias conditions: VCC = 10V, VEE = 10V, Ic = 2mA Design of C2 : For capacitor, IT = CV, 2 103 1 103 = C 10 Then C2 = 0.2F, use 0.22muF std. Design of R: Since voltage across the resistor R is always constant (VCC ), VCC 10 R= = = 5k, use 5.6k std. I 2 103 Design of C1 : Since C1 is acting as a voltage source, take C1 = 100C = 100 0.22

24

Experiment 6

BOOTSTRAP SWEEP CIRCUIT

AIM
To set up and study a bootstrap sweep circuit.

EQUIPMENTS AND COMPONENTS REQUIRED

Transistor, diode, resistor, capacitor, bread boar, signal generator, DC supplies and CRO.

THEORY
If the charging and discharging currents of capacitor is made constant, the voltage across the capacitor will rise or fall linearly bootstrap circuit achives constant current through the capacitors. When the Vcc supply is switched on, capacitor C1 charges from Vcc supply through diode D. Once the charge is over, the potential at the left side of the capacitor is positive and hence the diode becomes reverse biased. Transistor Q1 act as a high switch and transistor Q2 follows input since it is an emitter follower conguration. When the trigger voltage rises to logic high state, the transistor Q1 will switch to saturation. Now the transistor Q1 is made OFF by applying a negetive going gating pulse. The capacitor C charges through R. Then the potential at the base of Q2 increases and emitter of Q2 follows the input since it is a emitter follower. Capacitor will charge with a constant current. Established by the constant potential dierence across the resistor R and hence the charging will be very linear. RC time constant will determine the slope of the sweep. For linear charging of the capacitor to Vcc , circuit is designed so that Ts = RC . Resistor R must be a high value resistor. Since the base current of Q2 is depended on it. To provide sucient base current to transistor Q1 , RB should be less than hF E R. The capacitor C1 must be much higher than C to function as a voltage source.

PROCEDURE
1. Verify the condition of all components and setup the circuit. 2. Input trigger must be a square wave or pulse waveform with 1 ms time period. For negative part of the cycle amplitude must be suciently high. 3. Observe the trigger waveform and output waveform on CRO screen. 4. Vary RC product and RB and observe the changes in the output waveform.

RESULT
Designed and set up the bootstrap sweep circuit and the waveform were plotted.

25

Experiment 7

VCC +12V L 10mH R1 33k 0.01F CC1 RL 320 0.01F

C 0.2F CC2 0.01F

VO

Vin 100mV

R2 47k RE 6k

CE

26

Experiment 7

TUNED AMPLIFIER
AIM
To design and set up a tuned radio frequency amplier using descrete components, also to obtain its frequency response and to calculate its Q-factor.

COMPONENTS AND EQUIPMENTS

Transistor, IFT, resistors, capacitors, bread board, connecting wires, signal generator, DC source and CRO.

THEORY
Tuned voltage amplier amplies the signal of decided frequency and attinuates all other frequencies. The frequency of oscillation is determined by a parallel resonant circuit. 1 A parallel LC circuit provides High impedence at the resonant frequency for f0 = 2 . LC The gain of the amplier is maximum at the center frequency, because of the gain is directly proportional to the impedence of the collector. On either side of the resonant frequency, voltage gain falls. Transistor in the tuned circuit is biased to funtion in class C operation. In a class C amplier collector current ows for less than half a cycle. The LC circuit produces sine wave at the collector from the half cycles of input signal. The selectivity of the circuit, requency . Q, is given by the expression Q = resonantf bandwidth The #### of the tuned circuit to amplify a narrow band of frequencies makes in ideal for amplifying radio and TV signals. They are widely used as an intermediate frequency stage of radio and tv recievers. Figure shows a single capacitor recievers use standard 455KHz as. If transformer is employed as the LC circuit, radio recieves and standard 455KHz and if a high frequency transistor is used in the ciruit because the frequency of operation is large.

PROCEDURE
1. Set up the circuit on the bread board. Check the DC biasing condition using a multimeter, the transistor must lie in cut-o region. VBE should be zero or less. 2. Apply 100mV sine wave from the signal generator to the input of the circuit, keeping a 3MHz or more, measure the output amplitude corresponding to dierent frequencies and enter it in tabular column. 3. Plot the frequency response characteristics on a graph sheet with gain in dB on y -axis and log f on x-axis. 4. Find the bandwidth and calculate the quality factor of the tuned circuit using respective expression.

27

28

RESULT
Designed and set up tuned amplier, Q-factor =. . . . . . . . . Band width=. . . . . . . . .

29

Experiment 8

-OFFSET NULL -1V +1V V-

1 2 741 IC 3 4

8 7 6 5

NC V+ OUT +OFFSET NULL

Inverting amplier
Rf 10k +VCC 7 6 4 -VCC VO

Non-inverting amplier
Rf 10k +VCC 7 6 4 -VCC VO

2 1k

741 IC

741 IC

1k

Vin 2VPP

Vin 2VPP

Zero crossing detector

2

Voltage follower
2

741 IC

+VCC 7 6 4 -VCC VO Vin 2VPP

741 IC

+VCC 7 6 4 -VCC VO

3 Vin 2VPP

30

Experiment 8

BASIC OPERATIONAL CIRCUIT

AIM
To 1. 2. 3. 4. design and setup the following basic operational amplier circuits: Voltage follower Zero crossing detector Non-inverting amplier Inverting amplier

COMPONENTS AND EQUIPMENTS REQUIRED

Power supplies, CRO, function generator, op-amp, resistors, bread board and wires.

THEORY
Voltage amplier: Doing a slight change in non-inverting amplier circuit, a voltage follower circuit can be setup. If Rf = 0, expression for the gain of non-inverting amplier becomes 1. The name voltage follower came from the fact that the output is the replica of the input is unity gain and no0 change in polarity. This circuit provides very high input impedance and very low output impedance. It is used as a buer between a high impedance signal source to a low impedance load. Inverting amplier: This is one of the most popular op-amp circuits. The polarity of the input voltage gets inverted at the output. If a sine wave is fed to the input of this amplier, the output will be an amplied sine wave with 180 phase shift. The gain of the inverting amplier is given by the expression A = Rf /Ri where Rf is the feedback resistance and Ri is the input resistance. The input resistance of the inverting amplier is Ri . Inverting amplier can be used as a scalar because the amplitude of the output can be varied by the resistance Rf or Ri . Non inverting amplier: This circuit provides a gain to the input signal without any change in polarity. The gain of the non inverting amplier is given by the expression A = 1 + Rf + Ri . Where Rf is the feedback resistance and Ri is the input resistance. The input resistance of non inverting amplier is extremely large, typically 100M . This is because Vi appears across Ri as the potential dierence between input terminal is zero.

31

Design:
Voltage follower Circuit is non-inverting. Gain = 1 + Gain must be unity for a buer Rf = 0 ie, Rf = 0 Then Ri Non-inverting amplier Gain of non-inverting amplier A = 1 + Let the gain be 11, so that ratio Take Ri = 1k and Rf = 10k Inverting amplier Gain of an inverting amplier A = Let the required gain be -10 Rf Then = 10 Take Ri = 1k Rf = 10k Ri Rf Ri Rf =0 Ri Rf Ri Rf Ri

Expected Graphs Zero crossing detector

Vin +Vsat

Vsat

Voltage follower
Vin Vo

32

RESULT
The basic operational ampliers: 1. Zero crossing detector 2. Voltage follower 3. Non inverting amplier 4. Inverting amplier Are designed and setup on bread board and waveforms are plotted.

Expected Graphs Non-inverting amplier

Vin Vo

Inverting amplier
Vin Vo

33

Experiment 9

To measure input oset voltage To measure input bias voltage

Rf 10k +15V 2

741 IC

+15V 2

7 6 4 -15V 0.01F VO

741 IC

7 6 4 -15V VO

1k

3 1k

To measure input bias current

0.01F

To measure slew rate

1M +15V +15V 2 2

741 IC

741 IC

7 6 4 -15V VO

7 6 4 -15V 3 VO Vin

To measure CMRR
Rf 100k 100 R1 R2 100 10 Vin 3 +15V 2

741 IC

7 6 4 -15V VO

34

Experiment 9

MEASUREMENT OF OP-AMP PARAMETERS

AIM
To 1. 2. 3. 4. 5. measure the following parameters of Op-Amp: Input oset voltage Input oset current Input bias current Common Mode Rejection Ratio(CMMR) Slew rate

COMPONENTS AND EQUIPMENTS REQUIRED

Op-Amp, resistors, capacitors, bread board, power supply, function generator and CRO.

THEORY
Input bias current, IB :- The inverting and non inverting terminals of an Op-Amp are two base terminals of the transistors of a dierential amplier. In an ideal Op-Amp nocurrent ows through these terminals. However a small amount of current ows through these terminals which is of the order mA. Input bias current, IB = (IB1 + IB2 )/2 where IB1 andIB2 are the base bias current of the Op-Amp. Input oset current, IO :- The bias current IB1 &IB2 will not be equal in an Op-Amp. Input oset current is dened as the algebraic dierence between the current into the inverting and not inverting terminals. Typical and maximum values of oset current are 20A and 200A. Input oset current, IO = |IB1 IB2 | Input oset voltage, VO :- Even if the input voltage to an Op-Amp is zero, output voltage may not be zero. This is because of the circuit imbalances inside the Op-Amp. In order to compensate this, a small voltage should be applied between the terminals. Input oset voltage is dened as the voltage that must be applied between the input terminals of an Op-Amp to nullify the output voltage. Typical and maximum values of input oset voltage are 2mV and 6mV . CMRR:- It is the ratio of dierential mode gain to common mode gain. If a signal is applied common to both, the output of Op-Amp signal will be alternated. CMRR is usually expressed in dB . When an input signal VG is applied, common to both inputs common mode voltage gain Ac = Vo /Vi . Dierential mode gain Ad = Rf /Ri . Then CMRR is given by the expression: CM RR = 20 log 35 Ad Ac in dB

Calculations
i. Input oset voltage: Ri Vio = Vo Ri + Rf V0 = ......... Vio = . . . . . . . . . ii. Input oset current = IB1 IB2 Vo = . . . . . . mV Vo = . . . . . . mV IB1 1M = . . . . . . mV IB2 1M = . . . . . . mV I B1 = .........A I B2 = .........A Input oset current = |IB1 IB2 | = . . . . . . . . . A I B1 Input bias current : 2 = .........A I B2 Vo iii. slew rate = = . . . . . . . . . t iv. Ad = ......... Vo Ac = = ......... Vi Ad CMRR = 20 log Ac = .........

36

Slew rate:- Slew rate is the maximum rate of change of output voltage. It is the measure of fastness of Op-Amp. It is expressed in V /s. The internal output capacitance prevents sudden rate of output voltage for a sing input. If the slope requirements of the output voltage of the Op-Amp is greater than the slew rate distortion curve.

PROCEDURE
1. To nd input oset voltage:- Setup the circuit and measure the output voltage. Input oset voltage can be measured using the expression, Vio = Vo Ri /(Rf + Ri ). Where Vo = output voltage and Vio = input oset voltage. Check the Op-Amp to nd input oset voltage. Setup the circuit and measure the output voltage. Input oset voltage is given as V = V o Ri Rf + Ri

2. To nd input bias current and input oset current:- Setup the circuit and measure the output voltage using the expression Vo = IB 1 R and Vo = IB 2 R. IB 1 orIB 2 can be calculated. Then input oset current =IB 1 IB 2 . IB 1 + IB 2 Input bias current = 2 3. To nd slew rate:- Setup the circuit. Apply a square wave input of 1V,1KHz. Vary input frequency and observe the output. Increase the frequency until the output gets disturbed. Calculate slew rate by measuring the slope of the output wave.

RESULT
The following parameters of op-amp is measured. 1. 2. 3. 4. 5. Input oset voltage Input oset current Input bias current Slew rate CMRR = = = = = . . . . . . . . . mV . . . . . . . . . V . . . . . . . . . A . . . . . . . . . s . . . . . . . . . dB

37

Experiment 10

DIFFERENTIATOR
Rf 15k +VCC 7 6 4 -VCC VO

Ri =15k C=0.01F

741 IC

Rcomp =1.5k

Design:
fL = 1KHz C = 0.01F Rcomp = Rf ||R1 Take Rf = 15k, Av = 10 Rf 15 = 1. 5k = 10 R1 = R1 10

INTEGRATOR

C= 0.01F

Rf =150k +VCC 7 6 4 -VCC VO

Ri =15k

741 IC

Rcomp =1.5k

Design:
1 fH = 2RC Take fH = 1KHz C = 0.01F Rf = 10 R1 = 15k R1 Rf = 10 15 = 150k Rcomp = R1 ||Rf = 15k 38

Experiment 10

DIFFERENTIATOR AND INTEGRATOR

AIM
To design and setup dierentiator and integrator.

COMPONENTS AND EQUIPMENTS REQUIRED

741 IC, resistors, capacitor, function generator, power supply and CRO.

THEORY
Integrator: A voltage integrator is an electronic device performing a time integration of an electric voltage, thus measuring a total electric ux. Integrators are commonly used in wave shaping networks and signal generators. For proper integration, time period T of the signal must be larger than Ri C . The output voltage can be expressed as Vo = 1 RC Vin dt

Gain and linearity of the output waveform are the two important advantages of open integrators over ordinary integrators. Linearity of the waveform is due to the linear charging of the capacitors. Current through the capacitors is always constant and hence through the input resistance is constant due to constant potential drop across it. Current through input resistor and capacitor is same. A high value resistor is required across the capacitor. At low frequencies of the input voltage, capacitor behaves as a open circuit. In the absence of feedback resistor Rf , OpAmp may saturate at low frequency even for a very low voltage present at the inputs. This is because the open loop gain of Op-Amp is very high. When feedback resistor is connected, the gain will be reduced considerably at low frequencies. At higher frequencies, circuit will behave as an ordinary integrator. In other words, at very low frequencies Rf is eective and at high frequencies C is eective in the feedback path. When the input to an integrator is sine wave, output will be negative cosine wave. If the output is a square wave with duty cycle 50% output will be a triangular wave. Integrator is a rst order low pass lter. It permits low frequencies to pass to output. Dierentiator: If the input resistance of an amplier is replaced by a capacitor, it forms a dierentiator. The output of this circuit are derivatives of the input. Gain of the dierentiator increases with increase in frequency which makes the circuit unstable. This is a drawback at this circuit. The output voltage Vo can be expressed as V o = Rf 39 dVin dt

Dierenciator
f log f V0 Gain(dB ) f

Integrator
log f V0 Gain(dB )

40

Dierentiator functions as a high pass lter. At high frequency it becomes unstable and breaks into oscillation. Input impedance decreases with increase in frequency which makes the circuit very susceptible to high frequency noise. Both stability and high frequencies noise problems are reduced signicantly by the addition of two components Pi and CE .

PROCEDURE
DIFFERENTIATOR 1. Setup the dierentiator circuit, feed Vpp 1ms square wave at the input and observe the output and input in CRO. 2. Repeat the experiment by feeding triangular wave or sine wave at the input and observe the output 3. Feed a sine wave to the input and not down the output amplier by varying the frequency of the sine wave. Enter it in the tabular column and plot the frequency response curve. INTEGRATOR 1. Setup the integrator circuit. Feed Vpp 1ms square wave at the input and observe the input and output simultaneously on CRO. 2. Vary the dc oset of the square wave input and observe the dierence in the output waveform. 3. Repeat the experiment by feeding triangular wave and sine wave at the input and observe the output.

RESULT
Circuit for dierentiator and integrator are designed and set up on bread board and input and output waveforms observed on CRO and frequency response curves are plotted.

41

Experiment 11

Stable multivibrator with 50% of duty cycle

47k 2 +VCC 7 6 4 -VCC 10k VO

741 IC

Design
T 1+ = RC ln 2 1 R= ......... R = 47k, R1 = R2 = 10k

3 0.01F

10k

Astable multivibrator with 10% duty cycle

D1 RB 82k D2 RA 10k 2

Design
T =1ms, R1 = R2 = 10k T1 =0.1ms, T2 = 0.9ms 1+ T1 =RA C ln 1 1+ T2 =RB C ln 1 RA =10k, RB = 86k

741 IC

+VCC 7 6 4 -VCC 10k VO

3 0.01F

10k

42

Experiment 11

ASTABLE AND MONOSTABLE MULTIVIBRATOR USING OP-AMP

AIM
To design and setup an: 1. Astable multivibrator using op-amp for a frequency of oscillation of 1KHz. 2. Monostable multivibrator using op-amp for a pulse width of 1ms.

COMPONENTS AND EQUIPMENTS REQUIRED

Op-amp, resistor, capacitor,connecting wires, power supply and CRO.

THEORY
Astable multivibrator:- Astable multivibrator is capable of producing square wave for given frequency, amplitude and duty cycle. The output of the op-amp is forced to swing ### between positive saturation +Vsat and negative saturation Vsat resulting in a square wave output. This circuit is also called free running multivibrator or square wave generator. The output of the op-amp will be in positive saturation of dierential input voltage is negative and vice versa. The dierential voltage Vd = Vc Vsat . Where is the feedback factor and Vsat is the potential at non inverting terminals of the op-amp. Consider the instant at which Vo = +Vsat . Now the capacitor charges exponentially towards +Vsat through RA . Automatically Vd increases and crosses zero. This happens when Vc = +Vsat . The moment Vd become positive due to further charging of the capacitor. Output charges to Vsat . Now capacitor starts discharging to zero and recharges towards Vsat . Now Vd decreases and crosses zero. This happens when Vo = Vsat . The moment Vd becomes -ve gain output charges to +Vsat . This completes one cycle. 2 The time period T of the square wave is T = 2Rc ln 1+ . Where = R1R . If 1 +R2

T = 2. 2Rc . is made 1 2 Astable multivibrator is particularly useful for the generation of frequency is in the audio frequency range. Higher frequencies are limited by the delay time and slew rate of the op-amp.

Monostable multivibrator:- Monostable multivibrator is also called one shot. It has a stable state and a quasi-stable state. The circuit remains in stable states until triggering signal causes a transition to quasi-stable states. After time interval it returns to the stable state. So a signal pulse is generated when a trigger is applied. Consider the instant at which the output Vo = +Vsat . Now the diode D1 damps the capacitor voltage Vc at 0.7V. Feedback voltage available at non inverting terminal is +Vsat . 43

Monostable multivibrator
15k 2 1N4001 D 0.01F 3 +VCC 7 6 4 -VCC Cd 0.1F 1N4001 D Rd 8.2k R1 10k VO

741 IC

T R1 R

= = =

Design 1 RC ln , T = 1ms 1 R2 = 10k, = 0.05,C=0.1F .........

R2 10k

44

When the negative giving trigger is applied such that the potential at non-inverting terminal becomes less than 0.7V, the output switches to Vsat . Now the capacitor charges through R towards Vsat , because the diode becomes biased. When the capacitor voltage becomes more negative than Vsat . The comparator states charging to +Vsat through R until Vc reaches 0.7V and C becomes damped to 0.7V. The pulse width is given by 1 T = RC ln 1 approximately. If = 0.5, T = 0.69RC ; The time period of trigger must be larger than the output pulse width,T. The circuit does not respond to a trigger that appear, before the specied output pulse width and here it is called non-retriggerable monostable multivibrator.

PROCEDURE
Astable multivibrator:1. Verify whether the op-amp is in good condition by writing it as zero crossing op-amp or voltage follower. 2. Setup the astable multivibrator and observe the waveform saturation pin number 6 and 2 of op-amp on CRO and note down their amplitude and frequency. Monostable multivibrator:1. Verify whether the op-amp is in good condition by writing it as zero crossing op-amp or voltage follower. 2. Setup the monostable multivibrator and feed 6Vpp , 300Hz square wave at the trigger input. If the pulse generator available are narrow pulses, limited of square wave. 3. Observe the waveform at pin number 5,6 and 2 of op-amp on a CRO. Note down its amplitude and frequency.

RESULT
Designed and setup astable and monostable multivibrator.

45

Experiment 12
Rf 22k 27k R1 R3 R2 33k 33k 3 +15V 2

LPF Design
fL = 1KHz 1 fL = 2 R2 R3 C 2 C 3 Av = . . . . . . . . . C2 = C3 = . . . . . . . . . F R2 = R3 = Ri = . . . . . . K Rf = ......... Av = 1 + Ri Ri = . . . . . . . . . Rf = . . . . . . . . .

741 IC

7 6 4 -15V RL 10 VO

C2 0.047F Vin 2VPP

0.047F C3

HPF
27k R1 +15V 2 0.1F C1 R2 Vin 2V PP 0.1F C2 3 15 R2 15 Rf 22k

Design
fH = 1kHz 1 fH = 2 R2 R3 C 2 C 3 Rf = ......... AV = 1 + R1 R1 = 27k Rf = ......... R1 C2 = C3 = 0.01F R2 = R3 = R = . . . . . . . . .

741 IC

7 6 4 -15V RL 10 VO

46

Experiment 12

SECOND ORDER LOW PASS AND HIGH PASS CIRCUIT

AIM
To design and setup second order low pass and high pass lter.

COMPONENTS AND EQUIPMENTS REQUIRED

Op-Amp, resistors, capacitors, bread board, connecting wires, dual DC source or 2 DC sources, signal generator and CRO.

THEORY
Low pass lter:The null o of the second order lter is 40dB/decade. A rst order low pass lter can be converted into a second order type simply by using an additional RC network. The gain of the chi-second order is set by R1 and Rf , while the higher cut o frequency. It is determined by R2 , L2 , R3 and L3 are given by the expression fH = 1 2 R2 R3 C 2 C 3

Refer to the circuit diagram. At low frequencies both capacitors appear open and circuit becomes a voltage follower. As the frequency increases, the gain eventually starts to decrease. Second order high pass lter:Second order high pass lter can be considered by constructing from a second order low pass by interchanging the frequency deciding resistors and capacitors. Consider the circuit diagram. At low frequency the capacitors appear open and voltage gain approaches zero. At high frequency the capacitors appear short circuited and circuit become a non-inverting amplier. The cut of frequency of the lter is given by two expressions. 1 fL = 2 R2 R3 C 2 C 3 If C2 = C3 = C and R2 = R3 = R, then fL = 1 2RC

47

Vo

log f

20 log

Vo Vs

48

PROCEDURE
Second order low pass lter 1. Setup the circuit and feed a 2Vpp sin wave from the signal generator. 2. Vary the frequency of sine wave in steps and note down the corresponding output voltage. 3. Mark higher cut of frequency on the graph sheet and calculate the cuto in dB/decade from graph sheet. Second order high pass lter 1. Setup the circuit and feed 2Vpp sine wave from the signal generator. 2. Vary the frequency of sine wave in steps and note down corresponding output voltage. Plot the frequency response on semi log graph sheet. 3. Mark lower cuto frequency on the graph sheet and calculate the cuto in dB/decade from the graph sheet.

RESULT
Designed and setup the second order low pass and high pass lter circuit. fH = . . . . . . . . . fL = . . . . . . . . .

49

Experiment 13

Rf 47k +15V 2

Ri 1k

741 IC

7 6 4 -15V R1.5 VO

C 0.1F R 1.5

0.1F C

Design
The required frequency of the oscillation, fo = 1KHz 1 Given, fo = , C = 0.1F 2RC Then, R = 1.6K, use 1.5K std. Rf = ...... Gain = 1 + Ri Take Ri = 1k Then Rf = 2.2k, use 4.7k potentiomenter.

50

Experiment 13

WEIN BRIDGE OSCILLATOR

AIM
To design and setup a wein bridge oscillator using Op-Amp for a frequency of 1KHz.

COMPONENTS AND EQUIPMENTS REQUIRED

Op-amp, capacitors, resistors, potentiometer, breadboard, connecting wires, DC source and CRO.

THEORY
Figure shows the wein bridge oscillator using Op-Amp instead of transistor. The OpAmp output is applied as an input volt to the wein bridge oscillator between points A and C. The output of the wein bridge which acts as the feedback network is applied to the Op-Amp input between the points D and B. The R and C components in the frequency sensitive arms of the bridge will decide the 1 . oscillator frequency. The expression for the oscillator frequency is given by fo = 2RC The oscillator frequency can be varied by varying both the capacitor simultaneously. The ampliers gain can be changed by changing the value of resistor. Gain of the non-inverting ampliers is adjusted at A 3. Wein Bridge acts as the lead-lag RC feedback network. At a particular frequency called frequency of oscillation, the phase shift introduced by the wein bridge by zero degree and feedback factor = 1/3.

PROCEDURE

1. Setup the circuit after verifying whether the Op-Amp is in good condition. 2. Note down the amplitude and frequency of output waveform.

RESULT
Designed and setup wein bridge oscillator using Op-Amp.

51

Experiment 14

10k 1N4001 D 10k Vin 3 2

+VCC 7 D VO

741 IC

4 -VCC

6 1N4001

52

Experiment 14

PRECISION RECTIFIER
AIM
To set up the and study a half wave rectier using Op-Amp.

COMPONENTS AND EQUIPMENTS REQUIRED

Op-Amp, resistor, diode(1N 4001), bread board, connecting wires, function generator, power supply and CRO.

THEORY
An inverting voltage follower can be converted into an ideal half wave rectier by adding two diodes as shown in gure. When Vin is +ve Vo become -ve and the diode gets forward biased. At this moment, diode D2 is reverse biased. When Vin become negative Vo become +ve and diode D2 get forward biased. If a sinusoidal wave is applied at Vin , +ve going ripples appear at output point Vo and -ve going ripples appear at output point V1 . Op-Amp rectier is also called precision rectier because it is also to rectify very low amplitude signal. Ordinary diode rectier need minimum input voltage of the order of cut-in voltage of the diode. Op-Amp rectier also provide gain.

PROCEDURE
1. Verify whether the Op-Amp is in good condition by wiring it on zero crossing detecter or voltage follower. 2. Setup half wave rectier and feed 100mV Vpp sine wave at the input. 3. Observe the negative going and +ve going half cycles at the output V1 and V2 .

RESULT
Designed and setup the precission half wave rectier circuit and obtained the rectied output waveform.

53

54

PSPICE
INTRODUCTION
PSPICE stands for Simulation Program with Integrated Circuit Emphasis. It is a general purpose circuit program that can be used to simulate and analyse electrical and electronics circuits. The electronic components such as resistors, capacitors, diodes, opamps etc can be used to perform dierent analysis such as DC analysis, DC sweep operating point etc. The earlier SPICE was available only on main frame computers. In 1984 microsim introduced PSPICE(PC based SPICE) which works on Personal computers. ngSPICE is a free software alternate for PSPICE, which is available on GNU/Linux and other Unix based Operating Systems.

55

Rf 10k +VCC 2

Ri =1k

741 IC

7 6 4 -VCC VO

Vin 2VPP

56

INVERTING AMPLIFIER
AIM
To simulate and observe characteristics of inverting amplier.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for Source IN. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Place voltage at input and output of op-amp. Take transient in that given values. Save the program and simulate.

RESULT
The simulation output is obtained in a new window.

57

Rf 10k +VCC 7 6 4 -VCC VO

741 IC

1k

Vin 2VPP

58

NON-INVERTING AMPLIFIER
AIM
To simulate and observe characteristics of non-inverting amplier.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components you want and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for source. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Place voltage at input and output of op-amp. Take transient in that given values. Save the program and simulate.

RESULT
The simulation output is obtained in a new window.

59

+15V 2

741 IC

7 6 4 -15V VO

3 Vin

60

VOLTAGE FOLLOWER
AIM
To simulate and observe characteristics of voltage follower.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for source. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Place voltage at input and output of op-amp. Take transient in that given values. Save the program and simulate.

RESULT
The simulation output is obtained in a new window.

61

47k 2

741 IC

+VCC 7 6 4 -VCC 10k VO

3 0.01F

10k

62

ASTABLE MULTIVIBRATOR
AIM
To simulate and observe characteristics of astable multivibrator.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for source. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Place voltage at input and output of op-amp. Take transient in that given values. Save the program and simulate.

RESULT
The simulation output is obtained in a new window.

63

741 IC

+VCC 7 6 4 -VCC VO

3 Vin 2VPP

64

ZERO CROSSING DETECTOR (COMPARATOR)

AIM
To simulate and observe characteristics of zero crossing detector.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for source. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Place voltage at input and output of op-amp. Take transient in that given values. Save the program and simulate.

RESULT
The simulation output is obtained in a new window.

65

R 6.8 C 0.022F VO

Vin 5VPP

66

RC LOW PASS FILTER

AIM
To simulate and observe characteristics of RC low pass lter.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for source. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Place voltage at input and output of op-amp. Save the program and select sweep. Then select diode. Give start frequency=10Hz and end frequency=1MHz. Use Vdc for input then simulate the program. We will get the frequency response.

RESULT
The simulation output is obtained in a new window.

67

VO R 6.8k C 0.022F

Vin 5VPP

68

RC HIGH PASS FILTER

AIM
To simulate and observe characteristics of RC high pass lter.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for source. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Save the program, select sweep. Then select diode. Give start frequency=10KHz and end frequency=1MHz. Use Vdc for input, then simulate the program. We will get the frequency response.

RESULT
The simulation output is obtained in a new window.

69

Rf 15k 27k R1 R3 R2 22k 22k 3 +15V 2

741 IC

7 6 4 -15V RL 10 VO

C2 0.01F Vin 2VPP

0.01F C1

70

SECOND ORDER HIGH PASS FILTER

AIM
To simulate and observe characteristics of second order high pass lter.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for source. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Place voltage at input and output of op-amp. Save the program, select ac sweep, take diode, then give start frequency=10Hz and end frequency=1MHz. Use Vac for input. Then simulate the program. We will get the frequency response.

RESULT
The simulation output is obtained in a new window.

71

C= 0.01F

Rf =150k +VCC 7 6 4 -VCC VO

Ri 15k

741 IC

Vin 2VPP

72

FREQUENCY RESPONSE OF OP-AMP INTEGRATOR

AIM
To simulate and observe characteristics of frequency response of op-amp integrator.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for source. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Place voltage at input and output of op-amp. Save the program, select ac sweep, take diode, then give start frequency=10Hz and end frequency=1MHz. Use Vac for input. Then simulate the program. We will get the frequency response.

RESULT
The simulation output is obtained in a new window.

73

Rf 15k +VCC 7 6 4 -VCC VO

2 C 0.01F 3

741 IC

74

FREQUENCY RESPONSE OF OP-AMP DIFFERENTIATOR

AIM
To simulate and observe characteristics of frequency response of op-amp dierentiator.

PROCEDURE
Go to start and then pspice of schematics. Take a new page, select the components and place it and complete the circuit on schematics. For ground use AGND. Use ASIN for source. Check the source and select it, make oset=0, magnitude=1V and frequency=1KHz. Give Vdc for pin numbers 7 and 4 of op-amp. Place voltage at input and output of op-amp. Save the program, select ac sweep, take diode, then give start frequency=10Hz and end frequency=1MHz. Use Vac for input. Then simulate the program. We will get the frequency response.

RESULT
The simulation output is obtained in a new window.

75