09EC61

USN VI SEMESTER END EXAMINATION MAY / JUNE 2012 Electronics and Communication Engineering

FUNDAMENTALS OF VLSI DESIGN (09EC61)

Time:3Hrs Instructions: Max. Marks: 100 1. Answer one full question from each unit. 2. Any missing Data can be suitably assumed. UNIT-I
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1.

a. b. c. a. b. a. b. c.

What is speed power product? And hence explain the evolution of microelectronics. Explain the working of enhancement made and depletion made MOSFET with neat diagrams. Write a note on twin tub process. Explain PMOS fabrication steps with neat diagrams. Write a note on Ebeam Mask and also explain its 2 important approaches.

2.

UNIT-II
3. Discuss the effect of threshold voltage in MOSFET and Derive the relations used. Calculate the native threshold voltage for an n-transistor at 3000K for a process with a si substrate with NA=1.80x106, a sioz gate oxide with thickness 200A0 (Assume ms=0.9v, Qfc=0) Describe the phenomena of channel-length Modulation and Mobility variation in MOSFET. Discuss the effect of Noise Margin with respect to CMOS inverter? Plot
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4.

a.

V0 , if n=p, n =1.5, n =25 and n <1 V1 p p p

What is Transmission Gate? Explain the importance of Transmission Gate, and Mention its draw back. Write a note on Body effect with necessary diagram.

10 Marks

b. c. 5. a. b. c. 6. a. b.

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UNIT-III
Write the four basic MOS layers and their color coding. Write the stick diagram for x AB CD . What are -based design rules? Write -based rules for wires and transistors. Explain the following circuit elements i) capacitors ii) interconnects iii) resistors. Write the layout for the following i) CMOS 3 i/p NOR gate ii) y= AB CD E (CMOS).
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10 Marks

UNIT-IV
7. a. b. What is scaling and hence find the scaling factor for 1) Saturation current Idss 2) Switching energy per gate Eg Calculate the Area capacitance with the associated structure
08 Marks

07 Marks

given: For 5 m technology. Metal to substrate = 0.075x10-4/m2 Metal to metal 1 = 0.1x10-41 m2 Find relative Area, cm, cp, poly area cg and total capacitance Ct. Page 1 of 2
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09EC61
c. 8. a. b. c. 9. a. Write a note on Super buffer.

USN
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How does the noise limit the logic levels and supply voltage. Derive the expression for the totaldelay when N inverters are cascaded. What are the limitations of scaling (any two).

UNIT-V
Realize the following expression Z= A ( B C ) ( D E ) using Pseudo-Nmos logic. Discuss its features and hence show VOL FOV in Pseudo nmos circuits. Explain the precharge and Evaluate mode in dynamic Cmos logic and discuss its merits and demerits. Explain the CMOS domino logic and discuss its features. Explain how any Boolean expression can be realized using pass transistor logic.
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b.
10

a. b.

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Possession of any kind of written material, mobile/ electronics gadgets & scribbling on QP, amounts to Malpractice