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A Novel Implementation of CRC Algorithm In XMODEM Protocol on FPGA Using VHDL

[1]

A.Bhargav,

[2]

J.E.N.Abhilash

[3]

N.Srikanth

Dept. of ECE, SCET

Associate, Professor. Dept. of ECE, SCET, Narsapur,

Associate, Professor. Dept. of ECE, SCET, Narsapur

Abstract X modem protocol requires a CRC to ensure the data correct. There are many implementations of the CRC algorithm. In this paper, CRC algorithm is implemented in Xmodem protocol. The implementation of 8-bit parallel CCITT CRC16 reduces the number of clock cycles required to generate the CRC. This implementation is for single- byte and multi byte inputs. CRC for 1024 bits of data can be achieved in 128 clock cycles using VHDL language. Keywords- LFSR; CRC parallel computation; Xmodem protocol; VHDL I. INTRODUCTION

Vacated r bits with zeros and the position of zeros are the location of the CRC. The above k + r bits of data complement to the generator polynomial and the remainder is the CRC. The original k-bit binary number and the r-bit CRC are all sent out when transmission. The received k + r bits of data complement to the generator polynomial and if the remainder is zero, indicating the transmission data is correct, or else it is incorrect. The following is the specify CRC implementation principle. The k-bit binary number is about to be transmission, using M (X) said, M (x) = C k - 1 X k - 1 + C k - 2 X k - 2 + + C i X i + +C1X+C0 (1)

Xmodem protocol is a widely used asynchronous file transfer protocol. The standard mainly contains two components: Xmodem and 1k-Xmodem. Xmodem transmit data by128-byte block form and 1k-Xmodem byte block is 1k 1024 bytes, both standards all support checksum and CRC verification methods. They all support of retransmission (generally support 10 times) if the transmitting data is mistake. Xmodem CRC checksum requires 128 bytes (or 1024 bytes) packets as a whole. When the receiver receives a data packet, then it send back a confirmation character if the checksum is correct while send back a negative character in order to waiting for retransmission if it is error. The efficiency of Xmodem protocol data transformation is directly impacted by the packet check time. The commonly used data transmission error checking method is parity, cyclic redundancy check code (abbreviated as CRC) and so on. Parity and CRC verification is generally applicable to a byte or a word, while CRC is also suitable for packets of data validation. CRC is essential in the mass data transformation application, such as Xmodem protocol, HEX file, RFID protocol, USB communication protocol, etc.
II. CRC ALGORITHMS PRINCIPLE

Left move the sequence data r-bit, that is multiplied by X r, where r is the highest power of the generator polynomial G (x). M (x) x r = C k1 X k + r - 1 + C k - 2 X k + r - 2 + + C 1 X k+1 + C 0 X k
r

(2)

The results of M (x) x modulo 2 divided by the generator polynomial G (x).

= Q(x) +

(3)

Finally the remainder R (x) is the CRC. Remainder polynomial R (x) can be expressed as: R(x) = dr-1 xr-1++d1 x1+r0 The final data need to be transmitted: M = (C k - 1 , , C 0 , d r - 1 , , d 1 , d 0) (5) From M to M ' is the process of the CRC coding. We can use the typical LFSR (linear feedback shift register) to complete the hardware circuit based on the above formula. As shown in the Fig 1. (4)

First, the basic idea of CRC uses the linear theory, left move r bits of the k-bit binary number, which is need to be transmitted, replenish the right

r15 trigger is 0; and it need right 1-bit after the modulo 2 operation if the output is 1. 3) At last we need continuous move into 16-bit 0 after the data stream M (x) all into the trigger, and end the calculation of this group data CRC The above circuit using the general process of the modulo 2 division operation, its biggest drawback is need continuous input 16 "0" after the data stream M (x) and the CRC of the trigger need to more 16 times calculation. EXAMPLE: An example was shown in figure-3 describing the operation of 16-bit CRC generation using fig - 2

Fig 1. Linear Feedback Shift Register LFSR

Fig 1 is a typical circuit, if the generator polynomial G(x) is 1, the output of the D flipflop connects to the output of the XOR gate; if it is 0, and the output of the D flip-flop connects to the output of the superior flip-flop. Therefore, this figure can be greatly simplified in the case of a fixed generator polynomial. There are some standard generator polynomials in the practical applications, as follows: CRC8: The polynomial is X 8+X 5+X 4+1, and the corresponding number is 0x131;
2

CRC12: The polynomial is X 12+X 11+X 3+X +1, and the corresponding figure is 0x180D;

CCITT CRC16: The polynomial is X16+X +X5+1, and the corresponding number is 0x11021;
12

Fig 3. Hardware Implementation Of 16-Bit CRC

ANSI CRC16: The polynomial is X16+X +X2+1, and the corresponding number is 0x18005;
15

Here the input data bits are 8. As shown in the above fig-3 m0-m7 indicate the input message bits. The basic process involves XOR operation at specified bits depending upon the standard generator polynomial we use. In Xmodem protocol we use CCITT CRC-16 polynomial i.e X 16+X 12+X 5 +1. So we have to perform XOR operation at bits 16, 12, 5, 1. Here 16 bits are appended to input message bits. So we have total 8+16 bits as data stream. So we need 24clock cycles to find out the CRC for 8-bit data. Operations of the last 8 clock cycles are shown in the above figure. Final row indicated the 16 bit CRC. For every clock cycle the last bit of higher nibble is taken as feedback for generation of next cycle. In between feedback bit get XORed with some intermediate bits as shown above. Main drawback of this process is, 24 clock cycles are needed to find out the CRC of 8 bit data. But in parallel implementation of Xmodem protocol clock cycles reduce to very smaller extends.

CRC32: The polynomial is X +X +X +X22+X16+X12+X11+X10+X8+X7+X5X4+X2+X1 +1, and the corresponding number is 0x104C11DB7.
23

32

26

In the Xmodem protocol, we use the standard CCIT CRC16 X 16+X 12+ X5+1 as the generator polynomial and the corresponding number is 0x11021. Therefore, the CRC hardware circuit can be simplified as shown in Figure- 2

Fig 2. The circuit implementation of CCITT CRC16 LFSR

1) We first clear the flip-flop by CR, and move the upper 16 bits (2 bytes) which need to be verified into 16 of the trigger. The upper 16 bits of the data stream will not be changed as the trigger has been cleared. 2) Then we continue flow the data into the trigger, it just need right 1-bit if the output of the

III.

DESIGN OF CRC PARALLEL COMPUTATION

In the Xmodem protocol, each packet is 128 bytes (1024 bits). We need 1040 (1024 +16) cycles

to figure out the CRC using the Figure 2. This design uses a parallel computing and hardware implementations in order to improve the real-time. We main narrative the 8-bit CRC parallel computing. The state of the flip-flop is the remainder of the CRC as shown in Figure 1. The remainder of the CRC is just concerned with the former input and the remainder of the previous state when the serial operation. The calculation of 8-bit parallel operation as follows: Supposed rji as the value of the trigger, i = 1, 2... n, as the input code sequence, j = 0, 1, ..., k-1, as the trigger coding,
i 1 i 1 i 1 i 1 rji = Gj . rk 1 rj 1 + Gj . rj 1 , j = 0 , rj 1 = 0 (6)

8 0 0 r11 = r3 r14 = M6 8 0 0 0 r12 = r4 r8 r12 0 r15 = M0

M4

M7

0 8 0 0 r13 = r5 r9 r13 = M1 0 r14

M5 M6 M7

0 r6

0 r10

0 r14

= M2 = M3

8 0 0 r15 = r7 r11

0 r15

It is easy to achieve 8-bit parallel CCITT CRC-16 mode computing hardware circuit according to the below logic, as shown in Figure 4.

The input data is 8-bit, so the maximum of i is 8. We can transitive launch r08 r158 by CCITT CRC16 (the polynomial is G(x) =X 16+X 12+X 2+1, that is, k = 16) and the equation (6). We need 24-clock to calculate the CRC of the 8-bit data. In the first 16-clock, we move the 8-bit data into the high trigger and the low 8-bit is zeros. And this is the initial moment, we can get the CRC of the 8-bit data after 8 clocks and the input data is zeros. Then the initial moment of the trigger values are: r00 - r70 = 0, r80, r90 r140, r150 = M0,M1 M7

Fig 4. 8-Bit Parallel CCITT CRC16


Hardware Circuit

EXAMPLE:

Let us consider the example seen above. Input bits are 01000001. Therefore M7 = 0, M6 = 1, M5 = 0, M4 = 0, M3 = 0, M2 = 0, M1 = 0, M0 = 1 Substitute the above values in the given equations.
D0 = M0 M4 D1 = M1M5 D2 = M2 M6 D3 = M3 M7 D4 = M4 = 1 0 = 0 0 = 0 1 = 0 0 =0 =1 =0 =1 =0 =0 =1 =1 =1 =0 =0 =0 =1 =1 =0 =1 =0

If rj8 is representing the value after 8 clocks, we substituted the rj8 into equation (6) and get the final expression of rj8.
7 3 8 5 4 3 2 2 r0 = r15 = r13 = r12 = r15 r11 = r14 r10 = 0 0 r12 r8 = M0 M4 2 8 7 4 3 2 0 0 r1 = r0 = r13 = r12 = r11 r15 = r9 r13 = M1 M5

D5 = M0 M4 M5= 1 0 0 D6 = M1 M5 M6= 0 0 1 D7 = M2 M6 M7= 0 1 0 D8 = M3 M7 D9 = M4 D10 = M5 D11 = M6 D13 = M1 M5 D14 = M2 M6 D15 = M3 M7 =00 =0 =0 =1 =00 =01 =00

We can derive from other similar items


8 0 r2 = r10 0 r14 = M2

M6

8 0 0 r3 = r11 r15 = M3
8 r4

M7
M4 M5 M6 M7 M5 M6 M7

0 r12

= M4
0 r13 = M0 0 r14 = M1 0 r15 = M2 0 r15 = M3

8 0 0 r5 = r8 r12 8 0 0 r6 = r9 r13 8 0 r7 = r10

D12 = M0 M4 M7= 1 0 0

0 r14

8 0 0 r8 = r0 r11

8 0 0 r9 = r1 r12 = M4 8 0 0 r10 = r2 r13 = M5

Final 16 bit CRC is 0101100011100101. Which is exact as calculated in the previous example

IV.

THE IMPLEMENTATION OF MULTIBYTE CRC ALGORITHM

The data package of the Xmodem protocol is 128-byte; we need 128 (or 1024) the above 8-bit parallel CRC circuit to complete the agreement. We can analysis the CRC of the multi-byte packet based on the byte because the smallest unit of data package sent is byte. Supposed there are n-byte packet, namely [D n , D n 1, D n - 2 , D 3, D 2, D 1 ]. The implementation steps summarized as follows: (1) Calculate the CRC of the first byte D n. Take the high 8-bit of the CRC with D n - 1modulo 2 operation and the result is the new D n 1 ; take the low 8-bit of the CRC with D n 2 modulo 2 operation and the result is the new D n - 2. And the packet will be [D n - 1, D n - 2, , D 2 , D 1]. 2) Calculate the CRC of the first byte of this packet D n-1.Take the high 8-bit of the CRC with D n2 modulo 2 operation and the result is the new D n - 2 ; take the low 8-bit of the CRC with D n - 3 modulo 2 operation and the result is the new D n - 3. And the packet will be [D n - 2 , D n - 3 , , D 2 , D 1 ]. (3) And so on, until the only two bytes [D 2 , D 1], then make up two-byte word 0 to this two bytes, that is calculate the remainder of [D 2 , D 1 , 0 , 0 ] by the above method. And the last remaining two bytes [C 2 , C 1] is the final CRC. Fig-5 gives a clear idea regarding the multibyte CRC implementation.

We can achieve the CRC of multi-byte using less logic resources in this way. Although increase two operations by make up two-byte word 0, it is in parallel computing each time and the time only relation to the transmission time of the trigger. And the consumption of the time is far less than the LFSR circuit. So it is more obvious advantages to the more number of bytes.
V. SIMULATION RESULTS

The following simulation result is for 8-bit input The CRC is 0101100011100101.

The following simulation result is for 16-bit input The final CRC is 1100111100011000

The following simulation result is for 128 bytes input The final CRC is 1111011101110100

VI.
Fig 5. Multibyte Implementation Of CRC Algorithm By Parallel Computation

CONCLUSION

B1 & B2 are 1st and 2nd bytes of input data. A1 & A2 are newly appended bits. C1, C2, C3, C4 represents the output of 16 bit-CRC. X1 & X2 are outputs of XOR operation.

This paper analysis the principle of the CRC calculation, a general method of parallel computing of CRC and the CRC algorithm solution of the data packet is shown above. Examples designed in this paper will give a detail study regarding the parallel computation process. We implement the Xmodem protocol with CRC check use FPGA based on the above method.

REFERENCES
[1] Yuan Wang, Ming Cheng. How the CRC Algorithm
In Cmodem Protocol Implementation in FPGA

[2] YU Xun The 32-bit cyclic redundancy check


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