YTE - Department of Electrical and Electronics Engineering

EE342 - Digital System Design

Project Topics
All projects will be done by groups of two students. Project topics will be distributed on a first-come, first-served basis. Send an e-mail to barbarosozdemirel@iyte.edu.tr indicating the group members and the selected project topic. Deadline for submission of Verilog source code and simulation test results for the first stage of the project is Friday, 10 May 2013. Deadline for completion of the entire project including the "Next Step" requirements is Friday, 31 May 2013 (end of finals).

EE342 - Digital System Design - Project Topics - Spring 2012

YTE - Department of Electrical and Electronics Engineering

Description of Design Projects

1. Multi-Purpose Timer
You get: 1. 1 MHz clock input. 2. An asynchronous gate input that enables timer indicating beginning and end of each count period. Counting starts at the rising edge of gate signal and stops at the falling edge. Requirements: 1. Time resolution is 1.0 s. 2. Timer must be capable of measuring time durations up to 60 ms. 3. Timer will send a 1-s interrupt pulse to a microprocessor after each count period. 4. Microprocessor will read the count result through an 8-bit data port. Specific problems: 1. How many counter bits are required? 2. Properly handle the asynchronous gate input so that the timer will give the time measurement as accurate as possible. 3. Generate the interrupt output. 4. Make the interface with the microprocessor to send the count results. Next step: 1. Make the timer operate in triggered mode as an alternative to the gated mode implemented before. A 1-bit control input selects the operation mode. Timer starts counting at the rising edge of trigger input. The next rising edge of trigger input stops timer and immediately starts another count period. Gate and trigger signals are received through the same input. Microprocessor reads the last count result while the timer is busy measuring the next time period. 2. Add another option to use the timer in programmable mode. In this mode, microprocessor sets the count limit and starts the counter. An interrupt is generated when the counter reaches the limit.

EE342 - Digital System Design - Project Topics - Spring 2012

YTE - Department of Electrical and Electronics Engineering

2. UART Transmitter
You get: 1. 76800 Hz clock input . 2. 8-bit data in parallel. 3. An active-high pulse of 1 s-duration that indicates "data ready" at the parallel inputs. Requirements: 1. Store data when data ready pulse is received. 2. Serial data output is high when it is idle. 3. Serial output data rate is 9600 baud. 4. Send data sequence is as follows: 1) One active-low start bit 2) Eight data bits 3) One active-high stop bit Specific problems: 1. The 1-s data ready pulse is too short compared to 76800 Hz clock period. 2. Determine the duration of each bit sent out. 3. Arrange the sequence of bits at the output. Next step: Add the following programmable options: 1. Baud rate selectable between 2400, 4800, 9600, and 19200. 2. Even/odd parity or no parity bit. 3. One or two stop bits. These options are entered through the same parallel data input used for data. A control input selects the parallel input type (0=> data to be transmitted, 1=> transmitter options) during the data ready pulse.

EE342 - Digital System Design - Project Topics - Spring 2012

YTE - Department of Electrical and Electronics Engineering

3. UART Receiver
You get: 1. 76800 Hz clock input. 2. Serial data received as follows: 1) One active-low start bit 2) Eight data bits 3) One active-high stop bit Requirements: 1. Serial data input is high when it is idle. 2. Serial input data rate is 9600 baud. 3. Store received data in a shift register. Stored data will be available as 8 parallel bits to be read by a microprocessor. 4. Generate an output pulse after receiving eight data bits and the stop bit. Specific problems: 1. How will you determine the read timing to store the bits received at the input? 2. Describe a method to decide when to stop reading serial data. Next Step: Add the following programmable options: 1. Baud rate selectable between 2400, 4800, 9600, and 19200. 2. Even/odd parity or no parity bit. Generate an output signal indicating the parity errors when parity check is enabled. 3. One or two stop bits. Generate an output signal indicating error conditions when stop bit(s) is not received (data input is low where it is supposed to be high). These options are entered through the same parallel data input used for data. An active-high pulse of 1 s-duration at the write enable input indicates that the receiver options are being written.

EE342 - Digital System Design - Project Topics - Spring 2012

YTE - Department of Electrical and Electronics Engineering

4. Arithmetic and Logic Unit (ALU)

You get: 1. 10 MHz clock input 2. A 16-bit operand input 3. 4-bit operation code input 4. A one-cycle active-high pulse indicating inputs are ready Requirements: 1. A 16-bit accumulator store the result of operations. 2. Accumulator is the first operand in binary operations. 3. Arithmetic operations use signed 2's complement representation. 4. A carry output is generated and stored at the end of an operation when applicable. 5. List of operation codes are given below: Unary Operation Codes: (no operand is required) 0000 Reset accumulator 0001 Reset flag(s) 0010 1's complement 0011 2's complement 0100 Shift left, Acc[0]<=0 0101 Shift left, Acc[0]<=Carry 0110 Shift right, Acc[15]<=0 0111 Shift right, Acc[15]<=Acc[15] Binary Operation Codes: (operand is required) 1000 Load (copy operand to Acc) 1001 Bitwise AND operation 1010 Bitwise OR operation 1011 Bitwise XOR operation 1100 Add 1101 Add with carry 1110 Subtract 1111 Subtract with carry

Specific problems: 1. Organize the ALU control logic according to the operation code for best performance. Next step: 1. An arithmetic overflow condition flag is generated and stored at the end of arithmetic operations. Describe the decision mechanism and the logic circuitry to detect arithmetic overflow condition. Prove that your overflow detection logic works for any number of bits. 2. Update the data interface so that the ALU will receive a 16-bit operand in two consecutive clock cycles, one byte at a time. The least significant byte is received first. ALU should start the arithmetic operations on the least significant byte without waiting for the other byte.

EE342 - Digital System Design - Project Topics - Spring 2012

YTE - Department of Electrical and Electronics Engineering

5. PWM Controller
You get: 1. 10 MHz clock 2. An 8-bit data interface to set the PWM period and ON time (duty cycle). 3. Necessary addressing and control inputs to get the PWM parameters. Requirements: 1. 16-bit count limit to set PWM period. 2. 16-bit count limit to set ON time (duty cycle). 3. Generate PWM waveform. Specific problems: 1. Design the PWM circuitry including the counter and the necessary storage registers for storing PWM period and duty cycle settings. 2. Determine the conditions to obtain 0 % (always low) and 100 % (always high) duty cycle at the PWM output. 3. Make the interface with the microprocessor to get the PWM parameters. Next step: 1. Improve your design to make sure that changing PWM period and duty cycle settings will not cause unwanted changes at the PWM output. 2. Implement a method to obtain a better PWM time resolution that is equal to half of the clock period available at the input.

EE342 - Digital System Design - Project Topics - Spring 2012

YTE - Department of Electrical and Electronics Engineering

6. Transition Detector
You get: 1. 10 MHz clock (ClkIn) 2. A 1-bit signal input Requirements: Generate two outputs as specified below: HCstable: Set to 1 if there are no transitions during high cycle of ClkIn for four consecutive clock cycles. LCstable: Set to 1 if there are no transitions during low cycle of ClkIn for four consecutive clock cycles. Specific problems: 1. Detect asynchronous transitions at the input. 2. Make sure that all clock cycles are checked for transitions. 3. Keep a history of transitions. Next step: 1. Extend the circuit to detect the transitions at eight parallel signal inputs during the high and low cycle of ClkIn. 2. Generate a clock output according to the following conditions: ClkOut = ClkIn if the signal inputs are stable during low cycle of ClkIn. ClkOut = ~ClkIn if the signal inputs are stable during high cycle of ClkIn. ClkOut = 0 if the signal inputs are not stable during high and low cycles of ClkIn.

EE342 - Digital System Design - Project Topics - Spring 2012

YTE - Department of Electrical and Electronics Engineering

7. Interrupt Controller
The interrupt mechanism of a computer allows temporary redirection of program execution initiated by devices outside the processor. These are the steps involved in serving an interrupt: 1. An interrupt source requests service from the processor activating one of the interrupt inputs of the interrupt controller. 2. Interrupt controller sends an interrupt pulse to the processor when it is appropriate according to the previously determined controller options. 3. Processor temporarily stops the regular program and executes an interrupt service routine (ISR) to serve the interrupt source. 4. Processor clears the interrupt flag at the end of ISR to indicate that the interrupt service is completed and returns back to the regular program. Interrupt controller utilizes flags to keep track of interrupt status. An interrupt status flag is set high when the corresponding interrupt input is activated, and it remains high until it is cleared by the processor at the end of ISR. Level-sensitive interrupt flags should behave in a different way under the following conditions: 1. If the interrupt input becomes inactive before the processor is invoked, then the flag is set back to 0 (processor skips the interrupt). However, if an output pulse has already been sent to the processor, then the status flag should remain high until it is cleared by the processor. 2. If the interrupt input is still active when the interrupt flag is cleared, then another pulse is sent to invoke the processor again. Level-sensitive inputs can be driven by multiple interrupt sources, and more than one source may request an interrupt service at the same time. You get: 1. Two interrupt inputs, Int0 and Int1 2. 10 MHz clock 3. An 8-bit data input to get the interrupt controller options: Bit-7,6: Int1En, Int0En: Enable interrupts at the input. Interrupt inputs are ignored when these bits are 0. Bit-5,4: Int1Sns, Int0Sns: Select interrupt sensitivity type. 0=>level-sensitive, 1=>edge-sensitive. Bit-3,2: Int1Pri, Int0Pri: Select interrupt priority. 0=>low, 1=>high. Bit-1,0: Int1Clr, Int0Clr: Setting these bits to 1 clears the corresponding interrupt flag. 4. A one-cycle, active-high write enable pulse that indicates valid controller data at the 8-bit data port. Requirements: A one-cycle (100 ns) pulse is sent to the microprocessor at the corresponding interrupt output when it is necessary to serve an interrupt. Generate two interrupt outputs Int0up and Int1up according to the following rules: 1. A one-cycle (100 ns) pulse is generated at the corresponding interrupt output according to the priority settings after an interrupt input is activated.

EE342 - Digital System Design - Project Topics - Spring 2012

YTE - Department of Electrical and Electronics Engineering

2. If an interrupt is received while the other interrupt flag is still active, then the new interrupt is served only if it has higher priority. Otherwise, the interrupt that arrived later will be ignored. Specific problems: 1. Describe the circuitry to select interrupt sensitivity type. 2. Describe the circuitry to generate two interrupt outputs, Int0up and Int1up, based on the priority settings. Proper generation of interrupt outputs require making decisions instantaneously whenever an interrupt input is activated. Next step: 1. Add the necessary circuitry to make the Int1Clr and Int0Clr control bits "selfresetting" or "self-clearing" (microprocessor should not write to the control register twice to set and reset Int1Clr or Int0Clr). 2. Correct the decision logic to handle the interrupts waiting to be served: If there is a pending interrupt, then the corresponding interrupt pulse is sent after the other interrupt flag is cleared. Decisions for interrupt outputs should be made whenever an interrupt input is activated AND whenever an interrupt flag is cleared. 3. Change the function of interrupt enable control bits, Int1En and Int0En as follows: Interrupt controller holds the interrupt outputs to the microprocessor while the enable control bits are 0. If there are any pending interrupts, then they are sent to the processor after the interrupts are enabled.

EE342 - Digital System Design - Project Topics - Spring 2012

YTE - Department of Electrical and Electronics Engineering

8. CPU Memory Access Controller

You get: 1. 10 MHz clock input. 2. A static RAM with 16-bit address and 8-bit data interface. Timing of memory read and write cycles are described below: Memory Read Cycle:
Addr: nWE: nOE:
>50ns >90ns data read from memory <10ns valid address >150ns >50ns >90ns data written to memory <10ns valid address >150ns

DataIO:

Memory Write Cycle:

Addr: nWE: nOE: DataIO:

Requirements: CPU generates the Addr, nWE, nOE, and DataIO lines according to the operation code (opcode) read from the memory. 1. Program Counter (PC) register stores the instruction address where the opcode is stored in the memory. 2. Bit-1 and bit-0 of the opcode indicates addressing mode: 00: No operand. 01: Immediate addressing. 1-byte operand follows the opcode (operand is stored at the next memory address right after the opcode). 10: Direct addressing. Address of 1-byte operand follows the opcode. 3. Bit-2 of opcode indicates the direction of memory access: 0=> read from memory, 1=> write to memory. 4. Target/source of read/write operations is an 8-bit accumulator register. Specific problems: Make a state machine that performs the following operations: 1. Reads opcode using the address stored in PC. 2. Interprets the opcode to determine the required memory R/W operations. 3. Controls memory interface lines. 4. Increments PC to keep track of instruction addresses. Next step: 1. Add indirect addressing option selected when bit-1 and bit-0 of the opcode are 11. Address of address of 1-byte operand follows the opcode. 2. Bit-3 of opcode indicates target/source register: 0=> accumulator (1 byte), 1=> PC (2 bytes). Writing into PC is a "GOTO" or "CALL" operation that redirects program execution to a different address in the memory.

EE342 - Digital System Design - Project Topics - Spring 2012

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