Jyoti Deshmukh et. al. / International Journal of Engineering Science and Technology Vol.

2(5), 2010, 1250-1252

Implementation and Analysis of SC-LECTOR CMOS Circuit Using Cadence Tool

JYOTI DESHMUKH*, KAVITA KHARE **
*

Research Scholar, Department of Electronics & Communication Engineering, Maulana Azad National Institute of Technology, Bhopal -460051, India (deshmukh_4@yahoo.co.in)

** Associate Professor, Department of Electronics & Communication Engineering, Maulana Azad National Institute of Technology, Bhopal -460051, India (kavita_khare1@yahoo.co.in) Abstract: In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chips total power consumption. We propose a technique called SC-LECTOR which combines leakage control techniques applied at different abstraction levels of the CMOS design. SCCMOS scheme is preferable and applied at block level since it offers better leakage savings when the block is not operating. LECTOR method controls leakage at circuit level by introducing LCTs which causes increase in resistance of the path from VDD to ground within logic gate. By combining SCCMOS and LECTOR, the leakage in standby mode can be reduced while the LECTOR remains at high speed in active mode. I. Introduction:

Most of the functional blocks remain inactive for long time. Leakage still occurs in such inactive mode as a result of reduced threshold voltage from scaling. As the leakage current increases faster, it will become more and more proportional to the total power dissipation. Hence, leakage power reduction has become a key issue in todays CMOS VLSI design. Leakage reduction techniques are broadly classified as per the targeted leakage mechanism for reduction, mode of operation [1] and abstraction level of the design [2] where the technique is applied. Most of the circuit level techniques target the circuit in standby mode and some target the circuit in active mode of operation. LECTOR technique works effectively in both active as well as idle mode of operation. Unlike Dynamic Threshold CMOS [3], it is also easier to fabricate. Leakage current through the LECTOR based circuit can be further decreased by combining it with block level leakage reduction technique. Several power switches are available which cuts off the circuit from the supply rails when circuit is in idle mode. SCCMOS is proven an effective power switch in leakage reduction and can be used in low VDD environment. This paper proposes a low power scheme wherein SCCMOS and LECTOR are combined by means of which standby leakage current can be reduced. In section II, the design of SCCMOS, LECTOR and SC-LECTOR will be explained. Experimental results are discussed in section III. Section IV summarizes the findings. II. Design for Leakage Control:

1. SCCMOS Approach: In this block level leakage reduction technique, a low- VT PMOS (NMOS) switch is used whose gate is over-driven (under-driven) through the use of a MOS charge pump as depicted in figure 1[4]. When the circuit enters in the standby state, leakage power of the circuit can be controlled by disconnecting the design from supply lines and putting it in low power mode through a sleep transistor. This switch works pretty well in low-VDD environment. Another advantage of this switch is its smallest footprint. However, one backup SRAM

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Jyoti Deshmukh et. al. / International Journal of Engineering Science and Technology Vol. 2(5), 2010, 1250-1252 cell is used with each flip-flop for data retention. Secondly, 0.5 V VDD and -0.5V VSS are essential with SRAM cell to enhance the driving capability; but it increases design complexity. Unlike the MTCMOS case, all the transistors, including switch in SCCMOS, are implemented using standard VT transistors. Use of single threshold transistor makes the technique faster and easier for fabrication. 2. LECTOR: As its name implies, LEakage Control TransistOR technique (LECTOR) [5] introduces two leakage control transistors (LCT) in each CMOS gate as shown in figure 2. Since one of the LCTs is always near its cutoff, it causes increase in resistance in the path from VDD to ground leading to decrease in leakage current. LECTOR is single threshold; vector independent method which requires only two transistors for every path in a circuit.

Figure 1. SCCMOS Concept Figure 2. LECTOR Method

3. SC-LECTOR Scheme: Advantages of SCCMOS and LECTOR are combined together to control leakage current. During active mode, PMOS switch is turned on, facilitating normal operation of the circuit whereas resistance in the form of LCTs limits the leakage current. During standby mode of operation, sleep transistor is turned off creating virtual supply rail and cutting off the circuit from supply causing leakage current reduction. By combining SCCMOS and LECTOR, the leakage in standby mode can be reduced while the LECTOR remains at high speed in active mode.

Figure 3. SC-LECTOR Technique

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Jyoti Deshmukh et. al. / International Journal of Engineering Science and Technology Vol. 2(5), 2010, 1250-1252 III. Experimental Results of SC-LECTOR Technique:

The SC-LECTOR technique was implemented with Cadences Virtuso Tool [6] and tested on 2-input NAND gate as a base case. In order to make comparison, SCCMOS, LECTOR and SC-LECTOR techniques are implemented over the base case and simulated with Cadences Spectre simulator and leakage power is calculated using aforementioned tool. An effect of each technique on performance metric is illustrated and a comprehensive evaluation is done. Table I provides the experimental values of average leakage power for the above mentioned techniques.
TABLE I Standby Leakage Power for Two Input NAND Gate

Circuit type

180 nm Process Technology, Supply Voltage = 1V Leakage Power Dissipation in Watts for Input Vector (0,0) (0,1) (1,0) (1,1) 3.329e-10 1.869e-14 3.252e-10 2.439e-14 8.28e-10 2.0966e-14 7.676e-10 2.629e-14 7.68e-10 2.0966e-14 7.617e-10 2.629e-14 8.44e-12 9.3651e-15 2.9412e-9 1.282e-14

Basic NAND SCCMOS NAND LECTOR NAND SC-LECTOR NAND IV Conclusion:

Average Leakage Power (W) 1.937e-9 1.749e-14 1.198e-9 2.2449e-14

Incorporation of more complex functionality while maintaining portability is the trend in todays VLSI design. This leads to increase in leakage power dissipation. We have presented combined efforts to reduce leakage power at block level as well as at circuit level. LECTOR technique gives leakage power reduction in nW range at circuit level wherein we can achieve 99.99 % less leakage power using SC-LECTOR technique as compared to LECTOR technique by combining SCCMOS with LECTOR, but consumes 22% more power than SCCMOS technique. Experimental results show that SC-LECTOR provides efficient power savings and is easier to fabricate due to its standard VT implementation. References:
[1] [2] [3] [4] [5] [6] Farzan Fallah and Massoud Pedram, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, IEICE transactions on electronics, vol. 88, no.4, pp. 509-519, 2005 Walid M. Elgharbawy and Magdy A. Bayoumi, Leakage Sources and Possible Solutions in Nanometer CMOS Technologies IEEE Circuits and Systems Magazine, Forth Quarter, 2005 F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P. K. Ko, and C. Hu, A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation, Dig. Tech. Papers IEEE Int. Electron Devices Meeting, pp. 809812, 1994 H. Kawaguchi, K. Nose, and T. Sakurai, A CMOS scheme for 0.5 V supply voltage with Pico-ampere standby current, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 192193, Feb. 1998. N. Hanchate and N.Ranganathan, LECTOR: A Technique for Leakage Reduction in CMOS Circuits, IEEE Transactions on VLSI Systems, vol. 12, pp. 196-205, Feb., 2004. Cadence Design Systems, Inc. http://www.cadence.com

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