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RDS(on) 60 m
IOUT
VCC
6A
36 V
SO-8
PENTAWATT
CMOS COMPATIBLE INPUT I ON STATE OPEN LOAD DETECTION I OFF STATE OPEN LOAD DETECTION I SHORTED LOAD PROTECTION I UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN I PROTECTION AGAINST LOSS OF GROUND I VERY LOW STAND-BY CURRENT
I I
P2PAK
DESCRIPTION The VN750, VN750S, VN750PT, VN750-B5 are a monolithic device designed in STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient BLOCK DIAGRAM
compatibility table). Active current limitation combined with thermal shutdown and automatic restart protect the device against overload. The device detects open load condition both is on and off state. Output shorted to VCC is detected in the off state. Device automatically turns off in case of ground pin disconnection.
VCC
VCC CLAMP
INPUT LOGIC
STATUS
Rev. 1 1/31
June 2004
CONFIGURATION DIAGRAM (TOP VIEW) & SUGGESTED CONNECTIONS FOR UNUSED AND N.C. PINS
VCC OUTPUT OUTPUT VCC
5 4
5 4 3 2 1
PENTAWATT
Input X Through 10K resistor
VCC
IOUT OUTPUT GND VCC
VOUT
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(1) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. (2) When mounted on a standard single-sided FR-4 board with 2cm2 of Cu (at least 35m thick) connected to all VCC pins. Horizontal mounting and no artificial air flow. (3) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick). Horizontal mounting and no artificial air flow. (4) When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35m thick). Horizontal mounting and no artificial air flow.
SWITCHING (V CC=13V)
Symbol td(on) td(off) dVOUT/dt(on) dVOUT/dt(off) Parameter Turn-on Delay Time Turn-off Delay Time Turn-on Voltage Slope Turn-off Voltage Slope Test Conditions RL=6.5 from VIN rising edge to VOUT=1.3V RL=6.5 from VIN falling edge to VOUT =11.7V RL=6.5 from VOUT=1.3V to VOUT=10.4V RL=6.5 from VOUT=11.7V to VOUT =1.3V Min Typ 40 30 (#) (#) Max Unit s s V/s V/s
INPUT PIN
Symbol VIL IIL VIH IIH Vhyst VICL Parameter Input Low Level Low Level Input Current Input High Level High Level Input Current Input Hysteresis Voltage Input Clamp Voltage Test Conditions VIN=1.25V VIN=3.25V IIN=1mA IIN=-1mA 0.5 6 Min 1 3.25 Typ (#) (#) (#) (#) (#) 6.8 -0.7 Max 1.25 Unit V A V A V V V
10 8
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STATUS PIN
Symbol VSTAT ILSTAT CSTAT VSCL Parameter Status Low Output Voltage Status Leakage Current Status Pin Input Capacitance Status Clamp Voltage Test Conditions ISTAT =1.6mA Normal Operation; VSTAT=5V Normal Operation; VSTAT=5V ISTAT =1mA ISTAT =-1mA 6 6.8 -0.7 Min Typ (#) (#) Max 0.5 10 100 8 Unit V A pF V V
Note 1: To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles. (#) See relative diagram
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VOL tDOL(off)
VIN=0V
1.5
(#)
3.5
V s
1000
OPEN LOAD STATUS TIMING (with external pull-up) IOUT< IOL VOUT > VOL VIN VIN
VSTAT
VSTAT
tDOL(off)
tDOL(on)
tSDL
tSDL
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dVOUT/dt(on)
dVOUT/dt(off)
10%
t
VIN td(on)
td(off)
TRUTH TABLE
CONDITIONS Normal Operation Current Limitation Overtemperature Undervoltage Overvoltage Output Voltage > VOL Output Current < IOL INPUT L H L H H L H L H L H L H L H OUTPUT L H L X X L L L L L L H H L H STATUS H H H (Tj < TTSD) H (Tj > TTSD) L H L X X H H L H H L
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IV C C C C C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
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NORMAL OPERATION INPUT LOAD VOLTAGE STATUS UNDERVOLTAGE VCC VUSD INPUT LOAD VOLTAGE STATUS undefined VUSDhyst
OVERVOLTAGE VCC<VOV VCC INPUT LOAD VOLTAGE STATUS OPEN LOAD with external pull-up INPUT LOAD VOLTAGE STATUS VOUT >VOL VOL VCC>VOV
TTSD TR
OVERTEMPERATURE
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1 1
APPLICATION SCHEMATIC
+5V
+5V
Rprot STATUS
VCC
GND
VGND
RGND
DGND
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / (IS(on)max). 2) RGND (VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the devices datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load.
This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected.
C I/Os PROTECTION:
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k. 9/31
V batt.
VPU
GROUND
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Vin=3.25V
5
Tc (C)
Tc (C)
Iin=1mA
7.6 7.4 7.2 7 6.8 6.6 6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175 0 -50 -25 0 25 50 75 100 125 150 175 0.01 0.02 0.03 0.04
Vstat=5V
Tc (C)
Tc (C)
0.5
Istat=1mA
7.6
Istat=1.6mA
0.4 7.4 7.2 0.3 7 6.8 0.2 6.6 6.4 6.2 0 -50 -25 0 25 50 75 100 125 150 175 6 -50 -25 0 25 50 75 100 125 150 175
0.1
Tc (C)
Tc (C)
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120
100
Iout=2A
100
Tc= 150C
90 80
80
Tc= 125C
70 60 50
60
40
Tc= 25C
40
Tc= - 40C
30
35
40
Tc (C)
Vcc (V)
Vcc=13V Vin=5V
100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 150 175 2.2 2 -50 -25 0 25 50 75 100 125 150 175 2.6 2.4
Tc (C)
Tc (C)
1.8 0.9 1.6 1.4 1.2 1 -50 -25 0 25 50 75 100 125 150 175 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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Vin=0V
Tc (C)
Tc (C)
Vcc=13V Rl=6.5Ohm
Vcc=13V Rl=6.5Ohm
25
50
75
100
125
150
175
Tc (C)
Tc (C)
Ilim Vs T case
Ilim (A)
20 18
Vcc=13V
16 14 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
13/31
10
A B C
1 0.1
A = Single Pulse at TJstart=150C B= Repetitive pulse at T Jstart=100C C= Repetitive Pulse at T Jstart=125C Conditions: VCC=13.5V Values are generated with R L=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization
1 L(mH)
10
100
14/31
10
A B C
1 0.1
A = Single Pulse at TJstart=150C B= Repetitive pulse at T Jstart=100C C= Repetitive Pulse at T Jstart=125C Conditions: VCC=13.5V Values are generated with R L=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization
1 L(mH)
10
100
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Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 0.14cm2, 0.8cm2, 2cm2).
RTHj_amb (C/W)
16/31
Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 0.97cm2, 8cm2).
RTHj_amb (C/W)
55
Tj-Tamb=50C
50 45 40 35 30
0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
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Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: 0.44cm2, 8cm2).
RTHj_amb (C/W)
90 80 70 60 50 40 30 20 10 0 0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
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100
10
0.1
Z TH = R TH + Z THtp ( 1 )
where
= tp T
0.5 0.05 0.8 3.5 21 16 58 0.006 2.60E-03 0.0075 0.045 0.35 1.05 2
Thermal Parameter
Area/island (cm2) R1 (C/W) R2 (C/W) R3 ( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
Tj
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
Pd
28
T_amb
19/31
100
10
Z TH = R TH + Z THtp ( 1 )
where
= tp T
0.5 0.15 0.7 1.6 2 15 61 0.0006 0.0025 0.08 0.3 0.45 0.8 6
Thermal Parameter
Area/island (cm2) R1 (C/W) R2 (C/W) R3 ( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
Tj
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
Pd
24
T_amb
20/31
100
0.5 cm 2 6 cm2
10
Z TH = R T H + Z THtp ( 1 )
where
= tp T
0.5 0.15 0.7 0.7 4 9 37 0.0006 0.0025 0.055 0.4 2 3 6
Thermal Parameter
Area/island (cm2) R1 (C/W) R2 (C/W) R3 ( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
Tj
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
Pd
22
T_amb
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DIM. A a1 a2 a3 b b1 C c1 D E e e3 F L M S L1
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23/31
P010R
24/31
P032T1
25/31
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2
End
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
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TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 24 4 16 1.5 1.5 11.5 6.5 2
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
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1.8
6.7
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 16 4 8 1.5 1.5 7.5 2.75 2
End
Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics. All other names are the property of their respective owners 2004 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States http://www.st.com
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