VLSI DESIGN

UNIT 1-CMOS TECHNOLOGY

Part A

1. What is design hierarchy? What are its ty es? Integrated circuits are quite complex in designing and a!ricating" t#e tas$ is made easier !% !rea$ing t#e pro!lem into design #ierarc#% &#ere pro!lem is 'ie&ed at di erent le'els( T%pes o designs are s%stem design" logic design" circuit design" p#%sical design and c#ip design( !. What is "C? What are di##erent "C $ayers? Integrated Circuit )ICs* are microscopic electronic net&or$s t#at are created in a special t%pe o material called a semiconductor( Silicon is a semiconductor &#ic# is used as a !ase material or ma+orit% o modern electronic s%stem( ,ase or su!strate" -xide la%er" Si- . )insulating* la%er" metal la%er )contact or 'ia* are some o IC la%ers( %. What is &eant 'y h(t($ith(gra hy? /#otolit#ograp#% is an important processing step in'ol'ed in IC a!rication" it is used to create patterned material la%ers to guide electrical signals on t#e c#ip( /#oto mas$ing and p#oto etc#ing are t#e t&o $e% process in'ol'ed in p#otolit#ograp#% or ma$ing patterned materials( ). What is *"E? )0a%12une 13* 4IE is 4eacti'e Ion Etc#ing in &#ic# ioni5ed atoms o an inert gas suc# as argon )6r* are mixed &it# etc#ing assisting c#emicals( T#e mixture is t#en excited &it# a radio requenc% )r * electric ield in a manner t#at dri'es t#e ions1c#emicals in a 'ertical up-do&n motion to etc# a&a% t#e sur ace( +. What is #eat,re si-e? 7eature si5e or minimum eature si5e o an IC is t#e smallest dimension t#at can actuall% !e trans erred to a c#ip( .. What is &eant 'y s,'&icr(n and dee s,'&icr(n? 0odern acilities can manu acture c#ips &it# minimum eature si5es smaller t#an 1 micron &#ic# is $no&n as su!micron tec#nique( 6d'anced state o art a!rication plants can produce integrated circuits &#ere t#e smallest eature si5e is less t#an 3(1 8m &ide &#ic# is called deep su!micron tec#nique( /. 0e#ine as ect rati(. It is t#e ratio !et&een c#annel &idt# )9* and c#annel lengt# )L*( 6spect ratio : 91L

1. 0e#ine thresh($d 2($tage. T#e T#res#old 'oltage" VT or a 0-S transistor can !e de ined as t#e 'oltage applied !et&een t#e gate and t#e source o t#e 0-S transistor !elo& &#ic# t#e drain to source current" IDS e ecti'el% drops to 5ero( T#res#old 'oltage 3. What is se$# a$igned techni4,e?
5" Se&ester ECE 6 Page 1

VLSI DESIGN

UNIT 1-CMOS TECHNOLOGY

In t#e 0-S7ET a!rication process" gate and n; or p; regions automaticall% aligned to eac# ot#er &#ic# is $no&n as sel aligned tec#nique( 17. What is CMP? /lanari5ation is mandator% in c#ips t#at use more t#an t&o or t#ree metal la%ers( T#e most common tec#nique is C#emical-0ec#anical /olis#ing )C0/* &#ic# is capa!le o producing 'er% lat sur aces(

11.

What is &eant 'y d( ing? List s(&e (# d( ants. T#e process o adding impurit% atoms is called doping( Impurities t#emsel'es are called dopants" e(g( - arsenic and silicon( What is L00? )No'1Dec 13* LDD is Lig#tl% Doped Drain structure( T#is structure is used to reduce some small de'ice e ect due to 'er% energetic partials called #ot electrons and #ot #oles(

1!.

1%.

What are generati(ns (# "ntegrati(n Circ,its? SSI )Small Scale Integration*" 0SI )0edium Scale Integration* " LSI )Large Scale Integration* " VLSI )Ver% Large Scale Integration* " ULSI )Ultra Large Scale Integration " GSI)Giga Scale Integration*(

1). Gi2e the 'asic r(cess #(r "C #a'ricati(n. Silicon &a er /reparation" Epitaxial Gro&t#" -xidation" /#otolit#ograp#%" Di usion" Ion Implantation" Isolation tec#nique" 0etalli5ation" 6ssem!l% processing < /ac$aging( 1+. 1.. What are the di##erent $ayers in MOS transist(rs? Drain" Source < Gate

Gi2e the di##erent ty es (# CMOS r(cess? /-&ell process" N-&ell process" Silicon--n-Insulator /rocess" T&intu! /rocess( What are the ste s in2($2ed in t8in9t,' r(cess? Tu! 7ormation" T#in-oxide Construction" Source Implantation" Contact cut de inition" 0etalli5ation( < Drain

1/.

11.

What are the ad2antages (# CMOS r(cess? Lo& po&er Dissipation" =ig# /ac$ing densit%" ,i directional capa!ilit%" Lo& Input Impedance" Lo& dela% Sensiti'it% to load( What is ,$$ d(8n de2ice? 6 de'ice connected so as to pull t#e output 'oltage to t#e lo&er suppl% 'oltage usuall% 3V is called pull do&n de'ice( n0-S is good or logic >3? so it is $no&n as pull do&n de'ice(
5" Se&ester ECE 6 Page .

13.

VLSI DESIGN

UNIT 1-CMOS TECHNOLOGY

!7. What is ,$$ , de2ice? 6 de'ice connected so as to pull t#e output 'oltage to t#e upper suppl% 'oltage usuall% VDD is called pull up de'ice( p0-S is good or logic >1? so it is $no&n as pull up de'ice( !1. What are the c(&&(n &ateria$s ,sed as &as:? /#otoresist" t&in dioxide )Si-.*" /olisilicon )pol%cr%stalline silicon*" Silicon nitrate )SiN*(

!!.

What is Stic: 0iagra&? What are its ,ses? It is used to con'e% in ormation t#roug# t#e use o color code( 6lso it is t#e cartoon o a c#ip la%out( It can !e dra&n muc# easier and aster t#an a complex la%out( T#ese are especiall% important tools or la%out !uilt rom large cells(

!%. Gi2e the 2ari(,s c($(r c(ding ,sed in stic: diagra&? Green @ n-di usion" 4ed- pol%silicon" ,lue @metal" Aello&- implant" ,lac$contact areas(

!).

What are design r,$es? Design rules are t#e communication lin$ !et&een t#e designer speci %ing requirements and t#e a!ricator &#o materiali5es t#em( Design rules are used to produce &or$a!le mas$ la%outs rom &#ic# t#e 'arious la%ers in silicon &ill !e ormed or patterned( What are La&'da ;<= 9 'ased design r,$es? T#ese rules populari5ed !% 0ead and Con&a% are !ased on a single parameter B" &#ic# c#aracteri5es t#e linear eature @ t#e resolution o t#e complete &a er implementation process and permits irst order scaling( T#e% #a'e !een &idel% used" particularl% in t#e educational context and in t#e design o multipro+ect c#ips(

!+.

!.. State any t8( di##erences 'et8een CMOS and >i ($ar techn($(gy. C0-S Tec#nolog% ,ipolar tec#nolog%

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VLSI DESIGN D Lo& dissipation static

UNIT 1-CMOS TECHNOLOGY

po&er D =ig# po&er dissipation D Lo& input impedance )#ig# dri'e current* D Lo& 'oltage s&ing logic D Lo& pac$ing densit% D Lo& dela% sensiti'it% to load D =ig# current output dri'e

D =ig# input impedance )lo& dri'e current* D Scala!le t#res#old 'oltage D =ig# noise margin D =ig# pac$ing densit% D =ig# dela% sensiti'it% to load ) anout limitations* D Lo& output dri'e current D Lo& gm )gm a Vin* D ,idirectional capa!ilit% D 6 near ideal s&itc#ing de'ice

D =ig# gm D =ig# t at lo& current D Essentiall% unidirectional

!/.

List any t8( ty es (# $ay(,t design r,$es. )No'1Dec 3E* B- rule" 8- rule(

!1.

What are the &a?(r ty es (# design r,$es? 0a+or t%pes o design rules are minimum eature rule" minimum spacing rule" surround rule and exact si5e rule( 0e#ine yie$d. A:no( o good die1total no( o die

!3.

%7. What are #(,r generati(ns (# "ntegrati(n Circ,its? SSI )Small Scale Integration* 0SI )0edium Scale Integration* LSI )Large Scale Integration*
5" Se&ester ECE 6 Page F

VLSI DESIGN

UNIT 1-CMOS TECHNOLOGY

VLSI )Ver% Large Scale Integration* %1. Gi2e the ad2antages (# "C? Si5e is less =ig# Speed Less /o&er Dissipation %!.Gi2e the 2ariety (# "ntegrated Circ,its? 0ore Speciali5ed Circuits 6pplication Speci ic Integrated Circuits)6SICs* S%stems--n-C#ips F(Gi'e t#e !asic process or IC a!rication Silicon &a er /reparation Epitaxial Gro&t# -xidation /#otolit#ograp#% Di usion Ion Implantation Isolation tec#nique 0etalli5ation 6ssem!l% processing < /ac$aging G(9#at are t#e 'arious Silicon &a er /reparationH Cr%stal gro&t# < doping Ingot trimming < grinding Ingot slicing 9a er polis#ing < etc#ing 9a er cleaning( I(Di erent t%pes o oxidationH Dr% < 9et -xidation J(9#at is t#e transistors C0-S tec#nolog% pro'idesH n-t%pe transistors < p-t%pe transistors( E(9#at are t#e di erent la%ers in 0-S transistorsH Drain " Source < Gate K(9#at is En#ancement mode transistorH T#e de'ice t#at is normall% cut-o &it# 5ero gate !ias( 13( 9#at is Depletion mode De'iceH T#e De'ice t#at conduct &it# 5ero gate !ias( 11(9#en t#e c#annel is said to !e pinc#ed @o H I a large Vds is applied t#is 'oltage &it# deplete t#e In'ersion la%er (T#is Voltage e ecti'el% pinc#es o t#e c#annel near t#e drain( 1.(Gi'e t#e di erent t%pes o C0-S processH p-&ell process n-&ell process Silicon--n-Insulator /rocess T&in- tu! /roces 1C(9#at are t#e steps in'ol'ed in t&in-tu! processH Tu! 7ormation T#in-oxide Construction
5" Se&ester ECE 6 Page G

VLSI DESIGN

UNIT 1-CMOS TECHNOLOGY

Source < Drain Implantation Contact cut de inition 0etalli5ation( 1F(9#at are t#e ad'antages o Silicon-on-Insulator processH No Latc#-up Due to a!sence o !ul$s transistor structures are denser t#an !ul$ silicon( 1G(9#at is ,iC0-S Tec#nolog%H It is t#e com!ination o ,ipolar tec#nolog% < C0-S tec#nolog%( 1I(9#at are t#e !asic processing steps in'ol'ed in ,iC0-S processH 6dditional mas$s de ining / !ase region N Collector area ,uried Su! collector )SCCD* /rocessing steps in C0-S process 1J(9#at are t#e ad'antages o C0-S processH Lo& po&er Dissipation =ig# /ac$ing densit% ,i directional capa!ilit% 1E(9#at are t#e ad'antages o C0-S processH Lo& Input Impedance Lo& dela% Sensiti'it% to load( 1K(9#at is t#e undamental goal in De'ice modelingH To o!tain t#e unctional relations#ip among t#e terminal electrical 'aria!les o t#e de'ice t#at is to !e modeled(

/64T-, 1( Explain t#e C0-S a!rication tec#niques &it# neat diagram in detail ;n(29 dec !771=. .( Descri!e t#e SC0-S design rule set &it# suita!le diagram( C( Explain t#e /#oto lit#ograp#% and pattern trans er in detail ;n(29dec !773=. F( Explain t#e S/ICE modeling concept &it# its structure in detail(;1 &ar:s= G( Explain t#e su!micron C0-S process in detail( ;1 &ar:s6n(29dec !773=. I( Descri!e t#e electrical c#aracteristics o a c#ip in detail(

5" Se&ester ECE 6 Page I