De Lab Manual

Digital Electronics Lab Manual
Department of BCA, PESIT, Bangalore

BCA I SEMESTER
ELECTRONICS
LABORATORY MANUAL
Digital circit! are "ar#$are component! t"at are implemente# !ing tran!i!tor! an#
interconnection! in comple% !emicon#ctor #e&ice! calle# integrated-circuits' Digital circit!
$or( in )inar* logic #omain $"ic" !e! t$o #i!crete &ale!, TRUE +,ig"- an# FALSE
(Low)' .e can al!o refer to t"e!e &ale! a! 1(High) an# 0 (Low)'
Logic-Gates are )a!ic )il#ing )loc(! of #igital circit!' U!ing t"e!e )il#ing )loc(!,
comple% fnction! or larger #igital circit! can )e )ilt'
Integrated Chip (IC):
Eac" of t"e i! a&aila)le in /0 pin Dal1In1Line pac(age! or DIP!' In a poplar logic famil*
calle# TTL +Tran!i!tor1Tran!i!tor Logic-, t"e lo$ logic le&el i! a!!igne# to 23 an# t"e "ig"
logic le&el i! a!!igne# to 43' Eac" IC or c"ip "a! an ID nm)er'
T"e pin! are nm)ere# a! !"o$n in figre )elo$' Pin / i! !all* i#entifie# a! t"e pin to t"e
left of an in#entation or ctot in one en# of t"e c"ip t"at i! &i!i)le $"en t"e c"ip i! &ie$e#
from t"e top' Occa!ionall*, it i! al!o i#entifie# )* a printe# or in#ente# #ot place# 5!t ne%t to
it'
PES-BCA, PESIT, BSK 3
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PRACTICALS IN ELECTRONICS
Subject Code: BCA!"#P
1. Study of Logic Gates AND, OR, NOT, NOR, NAND, XOR
2. Realisation of AND, OR and NOT Gates using Unie!sal Gates
". Design and !eali#ation of $alf Adde!%Su&t!acto! using NAND gates.
'. Design and !eali#ation of (ull Adde! using Logic gates.
). Design and !eali#ation of ' &it adde!%su&t!acto! using *+ ,'-"
.. Design and !eali#ation of /+D adde! using *+ ,'-"
,. Realisation of R0S (li1 flo1
-. Realisation of 203 (li1 flo1 using *+ ,'44 and *+ ,'14
5. Realisation of T and D (li1 flo1 using *+ ,',.
14. *61le6entation of S*SO S7ift Registe!s using (li10flo1s. 8*+ ,',.9
11. *61le6entation of S*:O S7ift Registe!s using (li10flo1s. 8*+ ,',.9
12. *61le6entation of :*SO S7ift Registe!s using (li10flo1s. 8*+ ,',.9
1". *61le6entation of :*:O S7ift Registe!s using (li10flo1s. 8*+ ,',.9
1'. Design and i61le6entation of odd and een 1a!ity c7ec;e! gene!ato! using *+
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Laborator$ E%erci&e !: Stud$ o' Logic (ate&
Objecti)e&:
To inestigate AND, OR, NOT, NAND and NOT gate o1e!ation.
To study so6e funda6ental la<s of /oolean Alge&!a.
To &eco6e fa6ilia! <it7 logic ci!cuits.
Introduction
T7is is t7e int!oducto!y la&o!ato!y session, to allo< you to &eco6e fa6ilia! <it7 e!y
&asic digital ci!cuits and t7e e=ui16ent t7at you <ill use fo! t7e !e6ainde! of t7e
e>1e!i6ents.
THEORY:
+i!cuit t7at ta;es t7e logical decision and t7e 1!ocess a!e called logic gates. ?ac7
gate 7as one o! 6o!e in1ut and only one out1ut. OR, AND and NOT a!e &asic gates.
NAND and NOR a!e ;no<n as unie!sal gates. /asic gates fo!6 t7ese gates.
AND GATE:
T7e AND gate 1e!fo!6s a logical 6ulti1lication co66only ;no<n as AND function.
T7e out1ut is 7ig7 <7en &ot7 t7e in1uts a!e 7ig7. T7e out1ut is lo< leel <7en any
one of t7e in1uts is lo<.
OR (ATE:
T7e OR gate 1e!fo!6s a logical addition co66only ;no<n as OR function. T7e out1ut
is 7ig7 <7en any one of t7e in1uts is 7ig7. T7e out1ut is lo< leel <7en &ot7 t7e
in1uts a!e lo<.
E*uip+ent
T7e e=ui16ent you !e=ui!e is as follo<s@ *+ ,'4- , *+ ,'"2
,&e'u- Chip .iagra+&:

/#"0(AN.) /#12(OR)
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Section !3 AN. (ate I+p-e+entation
8a9 +onnect one of t7e 20in1ut AND gates 8,'4-9 as s7o<n in (igu!e 1. Re6e6&e! to
1o<e! t7e Acc and GND te!6inals of t7e c7i1. Re6e6&e! also to leae t7e tu!ned
off, until you a!e su!e t7at you! ci!cuit is <i!ed co!!ectly.

4igure !3 T7e 20in1ut AND gate.
8&9 Aa!y t7e in1uts A and / 8i.e. 4 and B)A9 to o&tain all t7e 1ossi&le co6&inations
and co61lete t7e t!ut7 ta&le 8as &elo<9 fo! t7e AND gate. +7ec; t7e out1ut ( at t7e
L?D out1ut.
A B 4
4 4
4 1
1 4
1 1

Section 23 A&&ociati)e La5&
8a9 +onnect AND gates as s7o<n in (igu!e " to i61le6ent t7e /oolean e=uations ( C
A8/+9 and GC8A/9+.
4igure 13 :!oing T7e Associatie La<.
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8&9 Aa!y in1uts A, /, and + to o&tain all of t7e 1ossi&le co6&inations and to c7ec;
t7e associatie la<@ A8/+9 C 8A/9+. (ill in t7e t!ut7 ta&le &elo<@
A B C 4 (
4 4 4
4 4 1
4 1 4
4 1 1
1 4 4
1 4 1
1 1 4
1 1 1
Section 13 La5& o' Boo-ean A-gebra
8a9 To de6onst!ate t7e Dist!i&utie la<, connect AND, OR gates as s7o<n in (igu!e
&elo<. Aa!y t7e in1uts A, / and + to o&tain all 1ossi&le co6&inations and c7ec; t7at
t7e out1uts ( and G a!e identical.
4igure #. T7e Dist!i&utie La<.
Gie t7e out1uts in a t!ut7 ta&le as s7o<n &elo<@
A B C 4 (
4 4 4
4 4 1
4 1 4
4 1 1
1 4 4
1 4 1
1 1 4
1 1 1
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The NOT6 NAN.6NOR and 7OR (ate&:
Objecti)e&:
To inestigate NOT, NAND, NOR and XOR gate o1e!ation.
To study so6e t7e la<s associated <it7 t7e NOT, NAND and NOR o1e!ations.
To inestigate De Do!ganEs T7eo!e6
+o61onents Re=ui!ed @ *+ ,'4- 8AND9, *+ ,'"2 8OR9, *+ ,'4' 8NOT9,
*+ ,'448NAND9, *+ ,'428 NOR9, *+ ,'-. 8XOR9
Digital T!aine! 3it
Theor$
NOT (ATE:
T7e NOT gate is called an ine!te!. T7e out1ut is 7ig7 <7en t7e in1ut is lo<. T7e
out1ut is lo< <7en t7e in1ut is 7ig7.
NAN. (ATE:
T7e NAND gate is a cont!action of AND0NOT. T7e out1ut is 7ig7 <7en &ot7 in1uts a!e
lo< and any one of t7e in1ut is lo< .T7e out1ut is lo< leel <7en &ot7 in1uts a!e
7ig7.
NOR (ATE:
T7e NOR gate is a cont!action of OR0NOT. T7e out1ut is 7ig7 <7en &ot7 in1uts a!e
lo<. T7e out1ut is lo< <7en one o! &ot7 in1uts a!e 7ig7.
7OR (ATE:
An ?>clusie0OR 8XOR9 gate is gate <it7 t<o o! t7!ee o! 6o!e in1uts and one out1ut.
T7e out1ut of a t<o0in1ut XOR gate assu6es a $*G$ state if one and only one in1ut
assu6es a $*G$ state. T7is is e=uialent to saying t7at t7e out1ut is $*G$ if eit7e!
in1ut X o! in1ut F is $*G$ e>clusiely, and LOG <7en &ot7 a!e 1 o! 4
si6ultaneously.
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,&e'u- Chip .iagra+&:

/#""(NOR) /#08(7OR)
The Laborator$:
Section !3 NOT (ate I+p-e+entation
8a9 +onnect one of t7e NOT gates 8,'LS4'9 as s7o<n in (igu!e &elo<. Re6e6&e! to
1o<e! t7e Acc and GND te!6inals of t7e c7i1. Re6e6&e! also to leae t7e Digital
T!aine! 3it tu!ned off, until you a!e su!e t7at you! ci!cuit is <i!ed co!!ectly.
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/#"#(NOT)
/#""(NAN.)

4igure T7e NOT gate
8&9 Aa!y t7e in1ut A to o&tain all t7e 1ossi&le co6&inations and co61lete t7e T!ut7
ta&le fo! t7e NOT gate. +7ec; t7e out1ut L?D.
Section 23 .e 9organ:& Theore+
8a9 +onnect in1uts A and / and t7ei! co61le6ents HA and H/ to AND, OR gates as
s7o<n in (igu!e &elo<. Fou <ill 7ae to use NOT gates to o&tain t7ese states.
4igure3 :!oing De Do!ganEs T7eo!e6.
8&9 Aa!y in1uts A and / and ente! t7e out1ut alues into a t!ut7 ta&le as s7o< &elo<.
A B 4
4 4
4 1
1 4
1 1
Section 13 The i+p-e+entation o' the NAN. gate3
8a9 +onnect one of t7e 20in1ut NAND gates as s7o<n in (igu!e &elo<.
4igure. T7e NAND gate.
?nte! t7e out1ut alues into a t!ut7 ta&le as s7o< &elo<. Aa!y t7e in1uts and !eco!d
t7e out1ut of t7e gate 4 and t7e actual oltage ;. ?>a6ine t7e out1ut of t7e NAND
gate <7en one of t7e in1uts is left floating 8not connected9. $o< can a NAND gate &e
used as an ine!te!I
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A B 4
4 4
4 1
1 4
1 1

Section #3 The i+p-e+entation o' the NOR gate3
?nte! t7e out1ut alues into a t!ut7 ta&le fo! diffe!ent alues fo! A J / as s7o<
&elo<. Aa!y t7e in1uts and !eco!d t7e out1ut of t7e gate 4. <e!e ( is gien &y
( C 8A B /9K
A B 4
4 4
4 1
1 4
1 1
Section <: I+p-e+entation o' 7OR (ate:
?nte! t7e out1ut alues into a t!ut7 ta&le fo! diffe!ent alues fo! A J / as s7o<
&elo<. Aa!y t7e in1uts and !eco!d t7e out1ut of t7e gate 4. <e!e ( is gien &y
( C 8A B /9K
A B 4
4 4
4 1
1 4
1 1
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Laborator$ E%erci&e 23 Rea-i=ation o' Ba&ic (ate& u&ing ,ni)er&a- (ate&
Unie!sal gates a!e t7e ones <7ic7 can &e used fo! i61le6enting any gate li;e AND,
OR and NOT, o! any co6&ination of t7ese &asic gatesL NAND and NOR gates a!e
unie!sal gates.
Theor$
Any logic function can &e i61le6ented using NAND gates. To ac7iee t7is, fi!st t7e
logic function 7as to &e <!itten in Su6 of :!oduct 8SO:9 fo!6. Once logic function is
cone!ted to SO:, t7en is e!y easy to i61le6ent using NAND gate. *n ot7e! <o!ds
any logic ci!cuit <it7 AND gates in fi!st leel and OR gates in second leel can &e
cone!ted into a NAND0NAND gate ci!cuit.
Any logic function can &e i61le6ented using NOR gates. To ac7iee t7is, fi!st t7e
logic function 7as to &e <!itten in :!oduct of Su6 8:OS9 fo!6. Once it is cone!ted to
:OS, t7en itEs e!y easy to i61le6ent using NOR gate. *n ot7e! <o!ds any logic
ci!cuit <it7 OR gates in fi!st leel and AND gates in second leel can &e cone!ted
into a NOR0NOR gate ci!cuit.
NOT > ,&ing NAN.
AN. > ,&ing NAN.
OR > ,&ing NAN.
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NOT > ,&ing NOR
OR > ,&ing NOR
AN. > ,&ing NOR
Truth Tab-e to rea-i=e AN. and OR u&ing ,ni)er&a- (ate&
A B S
4 4
4 1
1 4
1 1
Truth Tab-e to rea-i=e NOT u&ing ,ni)er&a- (ate&
A S
4
4
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Laborator$ E%erci&e 13 ?a-' Adder @ Subtractor
T?EORA:
?AL4 A..ER:
A 7alf adde! 7as t<o in1uts fo! t7e t<o &its to &e added and t<o out1uts one f!o6
t7e su6 M SK and ot7e! f!o6 t7e ca!!y M cK into t7e 7ig7e! adde! 1osition. A&oe ci!cuit
is called as a ca!!y signal f!o6 t7e addition of t7e less significant &its su6 f!o6 t7e
X0OR Gate t7e ca!!y out f!o6 t7e AND gate.
4,LL A..ER:
A full adde! is a co6&inational ci!cuit t7at fo!6s t7e a!it76etic su6 of in1utL it
consists of t7!ee in1uts and t<o out1uts. A full adde! is useful to add t7!ee &its at a
ti6e &ut a 7alf adde! cannot do so. *n full adde! su6 out1ut <ill &e ta;en f!o6 X0OR
Gate, ca!!y out1ut <ill &e ta;en f!o6 OR Gate.
?AL4 S,BTRACTOR:
T7e 7alf su&t!acto! is const!ucted using X0OR and AND Gate. T7e 7alf su&t!acto! 7as
t<o in1ut and t<o out1uts. T7e out1uts a!e diffe!ence and &o!!o<. T7e diffe!ence
can &e a11lied using X0OR Gate, &o!!o< out1ut can &e i61le6ented using an AND
Gate and an ine!te!
Objecti)e&:
To i61le6ent a 7alf adde! using &asic gates
To i61le6ent a 7alf su&t!acto! using Unie!sal gate 8NAND9
E*uip+ent
T7e e=ui16ent you !e=ui!e is as follo<s@ *+ ,'4', *+ ,'44, *+ ,'-"
A 7alf adde! is a logical ci!cuit t7at 1e!fo!6s an addition o1e!ation on t<o one0&it
&ina!y nu6&e!s often <!itten as A and /. T7e 7alf adde! out1ut is a su6 of t7e t<o
in1uts usually !e1!esented <it7 t7e signals +out and Su6
Section !3 The ?a-' Adder

4igure: T7e $alf adde! ci!cuit 8a9Using NAND 8&9 Using X0OR
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8&9 Aa!y t7e in1uts A and / to o&tain all t7e 1ossi&le co6&inations and co61lete a
T!ut7 ta&le fo! t7e su6 out1ut S and t7e ca!!y out1ut +.
A B S C
4 4
4 1
1 4
1 1
Section 23 The ?a-' Subtracror (NAN. (ate&)
T"e "alf1!)tractor i! a co6&inational ci!cuit <7ic7 is used to 1e!fo!6 su&t!action of
t<o &its. *t 7as t<o in1uts, X 86inuend9 and F 8su&t!a7end9 and t<o out1uts D
8diffe!ence9 and / 8&o!!o<9.
4igure: T7e $alf Su&t!acto! ci!cuit 8a9Using NAND 8&9 Using X0OR
Aa!y t7e in1uts A and / to o&tain all t7e 1ossi&le co6&inations and co61lete a T!ut7
ta&le fo! t7e su6 out1ut S and t7e ca!!y out1ut +.
A B . B
4 4
4 1
1 4
1 1
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Laborator$ #3 The 4u-- Adder
Co+ponent& @ *+ ,'-., *+ ,'4-, *+ ,'"2
Theor$:
4,LL A..ER:
A full adde! is a co6&inational ci!cuit t7at fo!6s t7e a!it76etic su6 of in1utL it
consists of t7!ee in1uts and t<o out1uts. A full adde! is useful to add t7!ee &its at a
ti6e &ut a 7alf adde! cannot do so. *n full adde! su6 out1ut <ill &e ta;en f!o6 X0OR
Gate, ca!!y out1ut <ill &e ta;en f!o6 OR Gate.
a9 Using Logic Gates@
8&9 Using Unie!sal Gate 8NAND9
4igure3 T7e (ull Adde! +i!cuit
8&9 Aa!y in1uts A; /; and +;01 and co61lete a T!ut7 ta&le fo! t7e ci!cuit.
A! B! C" S! C!
4 4 4
4 4 1
4 1 4
4 1 1
1 4 4
1 4 1
1 1 4
1 1 1
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Laborator$ < : #bit Adder @ Subtractor
Co+ponent& : *+ ,'-", *+ ,'-.
Theor$
# BIT BINARA A..ER:
A &ina!y adde! is a digital ci!cuit t7at 1!oduces t7e a!it76etic su6 of t<o &ina!y
nu6&e!s. *t can &e const!ucted <it7 full adde!s connected in cascade, <it7 t7e
out1ut ca!!y f!o6 eac7 full adde! connected to t7e in1ut ca!!y of ne>t full adde! in
c7ain. T7e augends &its of MAK and t7e addend &its of M/K a!e designated &y su&sc!i1t
nu6&e!s f!o6 !ig7t to left, <it7 su&sc!i1t 4 denoting t7e least significant &its. T7e
ca!!ies a!e connected in c7ain t7!oug7 t7e full adde!. T7e in1ut ca!!y to t7e adde! is
+4 and it !i11les t7!oug7 t7e full adde! to t7e out1ut ca!!y +'.
# BIT BINARA S,BTRACTOR:
T7e ci!cuit fo! su&t!acting A0/ consists of an adde! <it7 ine!te!s, 1laced &et<een
eac7 data in1ut M/K and t7e co!!es1onding in1ut of full adde!. T7e in1ut ca!!y +4
6ust &e e=ual to 1 <7en 1e!fo!6ing su&t!action.
T7e ,'LS-" is a 7ig7 s1eed '0&it (ull Adde!. *t acce1ts t<o '0&it <o!ds 8A1 to A'9
and 8/1 to /'9 and a ca!!y in1ut 8+49. *t gene!ates t7e &ina!y su6 out1uts 8S1 to S'9
and t7e ca!!y out1ut 8+'9 f!o6 t7e 6ost significant &it. +onnect t7e t<o &ina!y
nu6&e!s s7o<n &elo< to t7e in1uts of t7e '0&it 1a!allel adde!. +onnect t7e ca!!y
in1ut +4 to 4.
4igure. T7e (ou! /it Adde!
T7e addition and su&t!action o1e!ation can &e co6&ined into one ci!cuit <it7 one
co66on &ina!y adde!. T7e 6ode in1ut D cont!ols t7e o1e!ation. G7en DC4, t7e
ci!cuit is adde! ci!cuit. G7en DC1, it &eco6es su&t!acto!.
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PIN .IA(RA9 (IC /#01):
+7ec; t7e o1e!ation of t7e (ou! /it adde! &y adding t7e nu6&e!s@
8a9 4114 B 4141 8&9 1411 B 4411 8c9 1114 B 4144 8d9 1111 B 1111
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Su&
+in
Laborator$ 8: #BIT BC. A..ER:
Co+ponent&: *+ ,'-", *+ ,'4-, *+ ,'"2
+onside! t7e a!it76etic addition of t<o deci6al digits in /+D, toget7e! <it7 an in1ut
ca!!y f!o6 a 1!eious stage. Since eac7 in1ut digit does not e>ceed 5, t7e out1ut
su6 cannot &e g!eate! t7an 15, t7e 1 in t7e su6 &eing an in1ut ca!!y. T7e out1ut of
t<o deci6al digits 6ust &e !e1!esented in /+D and s7ould a11ea! in t7e fo!6 listed
in t7e colu6ns.
A /+D adde! t7at adds 2 /+D digits and 1!oduce a su6 digit in /+D. T7e 2 deci6al
digits, toget7e! <it7 t7e in1ut ca!!y, a!e fi!st added in t7e to1 ' &it adde! to 1!oduce
t7e &ina!y su6.
Objecti)e :
To design and i61le6ent /+D adde! using ' &it &ina!y adde! *+ ,'-".
Apparatu& Re*uired:
Theory:
BC. Addition
/ina!y +oded Deci6al is a 6et7od of using &ina!y digits to !e1!esent t7e deci6al
digits 4 t7!oug7 5. T7e alid /+D nu6&e!s a!e 84444 to 14419/+D. ?ac7 digit of t7e
deci6al nu6&e! <ill &e !e1!esented &y its fou! &it &ina!y e=uialent.
E%: 812,914 0 /+D e=uialent 84441 4414 411192. *n /+D addition t7e follo<ing
t7!ee cases a!e o&se!ed@
1. T7e !esulting /+D nu6&e! e=ual to less t7an 814419/+D.
2. T7e !esulting /+D nu6&e! g!eate! t7an 814419/+D.
". +a!!y is gene!ated in t7e /+D addition.
(o! case 2 and ", t7e !esult is added <it7 co!!ection facto! 841149/+D so t7at t7e
!esult is in alid /+D nu6&e!.
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T7e t<o /+D in1uts to &e added a!e a11lied at in1uts A and / of t7e fi!st &ina!y
adde! *+ ,'-". T7e su6 out1ut of t7e fi!st &ina!y adde! is gien to t7e / in1ut of t7e
second &ina!y adde!. T7e A in1ut of t7e &ina!y adde! is gien 841149/+D <7en a
ca!!y is gene!ated f!o6 t7e fi!st adde! o! <7en su6 f!o6 t7e fi!st &ina!y adde! is
g!eate! t7an 841149/+D, else A in1ut is 844449/+D. T7e follo<ing /oolean
e>1!ession is used to find <7et7e! 841149/+D o! 844449/+D needs to &e a11lied to
t7e A in1ut, +out C +out1 B S' 8S" B S29. G7e!e S', S", S2, S1 a!e t7e su6 of t7e
/+D f!o6 t7e fi!st &ina!y adde! <it7 S' as t7e DS/ and S1 as t7e LS/. +out1 is t7e
ca!!y out1ut f!o6 t7e fi!st &ina!y adde!.
Procedure:
1. Ae!ify t7e gates.
2. Da;e t7e connections as 1e! t7e ci!cuit diag!a6.
". A11ly and e!ify t7e a!ious co6&ination of in1ut acco!ding to t7e t!ut7 ta&le fo!
/+D adde!.
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Laborator$ E%erci&e /: RS 4-ip 4-op
Objecti)e&:
To study t7e funda6entals of &asic 6e6o!y units.
To &eco6e fa6ilia! <it7 a!ious ty1es of fli10flo1s.
To i61le6ent a data !egiste!.
Co+ponent& : *+ ,'44
Introduction
*n t7is la&o!ato!y <e <ill &uild on conce1ts t7at <e e>a6ined in t7e 1!eious
la&o!ato!y sessions. Ge a!e no< e>a6ining fli10flo1s. *t is li;ely t7at <e 7ae not
e>a6ined fli10flo1s in lectu!es at t7is 1oint, &ut 7o1efully t7e la&o!ato!y e>e!cise <ill
7el1 e>1lain t7e conce1ts as <e go along.
A fli10flo1 6aintains a &ina!y state indefinitely 8as long as t7e ci!cuit is 1o<e!ed9
until it !eceies an in1ut signal to s<itc7 states. T7e!e a!e a!ious ty1es of fli1 flo1s
t7at diffe! in t7e nu6&e! of in1uts t7ey 1ossess and 7o< t7e in1uts affect t7e &ina!y
state.
T?EORA
RS fli10flo1 is also called Sync7!onous fli10flo1. T7at 6eans t7at t7is fli10flo1 is
conce!ned <it7 ti6e. Digital ci!cuits can 7ae a conce1t of ti6e using a cloc; signal.
T7e cloc; signal si61ly goes f!o6 lo<0to07ig7 and 7ig70to0lo< in a s7o!t 1e!iod of
ti6e.
E*uip+ent
T7e e=ui16ent you !e=ui!e is as follo<s@ *+ ,'42 8NOR9
Section !3 The A&$nchronou& RS 4-ip4-op
8a9 +onnect t7e t<o NAND gates as s7o<n in (igu!e.
4igure3 An RS (li10(lo1 c!eated using NAND gates.
8&9 Aa!y t7e in1uts R and S to o&tain all t7e 1ossi&le co6&inations fo! N and %N.
R S B CB
4 4
4 1
1 4
1 1
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Section 23 The S$nchronou& 4-ip4-op
8a9 Sync7!onous 6eans t7at t7is fli10flo1 is conce!ned <it7 ti6e. Digital ci!cuits can
7ae a conce1t of ti6e using a cloc; signal. T7e cloc; signal si61ly goes f!o6 lo<0
to07ig7 and 7ig70to0lo< in a s7o!t 1e!iod of ti6e.
4igure3 A ty1ical cloc; signal.
4igure3 T7e Sync7!onous (li1 (lo1 using NAND 8 *+ ,'44 9
*61le6ent t7e ci!cuit in (igu!e . Fou can si6ulate a cloc; signal &y 6oing t7e cloc;
line f!o6 lo< to 7ig7 and &ac; again to lo<.
8&9 Aa!y in1uts R and S and a11ly t7e cloc; 1ulse. G!ite t7e out1ut states into a
ta&le as &elo<@
Bn@Bn R S BnD! @BnD!
4 1 4 4
1 4 4 4
4 1 4 1
1 4 4 1
4 1 1 4
1 4 1 4
4 1 1 1
1 4 1 1
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Laborator$ E%erci&e 0: EF 4-ip4-op
T7e 23 fli10 flo1 is anot7e! 6odification of t7e RS fli10flo1 <7ic7 7as its o<n <ay of
dealing <it7 t7e RS fli10flo1Ks undesi!a&le in1ut co6&ination 8<7en SC 1 and RC 19.
T7e 23 fli10flo1 7as 2 in1uts 2 and 3, eac7 ANDed <it7 t7e cloc; 1ulse and its
co!!es1onding NOR out1ut. T7e sc7e6atic fo! t7e 23 fli10 flo1 is s7o<n &elo<.
Co+ponent&: *+ ,'44, *+ ,'14 8" in1ut NAND gate9
Theor$:
G7at used to &e t7e S and R in1uts a!e no< called t7e 2 and 3 in1uts, !es1ectiely.
T7e old t<o0in1ut AND gates 7ae &een !e1laced <it7 "0in1ut AND gates, and t7e
t7i!d in1ut of eac7 gate !eceies feed&ac; f!o6 t7e N and not0N out1uts. G7at t7is
does fo! us is 1e!6it t7e 2 in1ut to 7ae effect only <7en t7e ci!cuit is !eset, and
1e!6it t7e 3 in1ut to 7ae effect only <7en t7e ci!cuit is set. *n ot7e! <o!ds, t7e t<o
in1uts a!e inte!loc;ed, to use a !elay logic te!6, so t7at t7ey cannot &ot7 &e
actiated si6ultaneously. *f t7e ci!cuit is Oset,O t7e 2 in1ut is in7i&ited &y t7e 4 status
of not0N t7!oug7 t7e lo<e! AND gateL if t7e ci!cuit is O!eset,O t7e 3 in1ut is in7i&ited
&y t7e 4 status of N t7!oug7 t7e u11e! AND gate.
G7en &ot7 2 and 3 in1uts a!e 1, 7o<ee!, so6et7ing uni=ue 7a11ens. /ecause of
t7e selectie in7i&iting action of t7ose "0in1ut AND gates, a OsetO state in7i&its in1ut
2 so t7at t7e fli10flo1 acts as if 2C4 <7ile 3C1 <7en in fact &ot7 a!e 1. On t7e ne>t
cloc; 1ulse, t7e out1uts <ill s<itc7 8OtoggleO9 f!o6 set 8NC1 and not0NC49 to !eset
8NC4 and not0NC19. +one!sely, a O!esetO state in7i&its in1ut 3 so t7at t7e fli10flo1
acts as if 2C1 and 3C4 <7en in fact &ot7 a!e 1. T7e ne>t cloc; 1ulse toggles t7e
ci!cuit again f!o6 !eset to set.
T7e end !esult is t7at t7e S0R fli10flo1Es OinalidO state is eli6inated 8along <it7 t7e
!ace condition it engende!ed9 and <e get a useful featu!e as a &onus@ t7e a&ility to
toggle &et<een t7e t<o 8&ista&le9 out1ut states <it7 ee!y t!ansition of t7e cloc;
in1ut signal.

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Laborator$ E%erci&e G: T and . 4-ip4-op
T 4-ip'-op
T7e toggle, o! T, fli10flo1 is a &i0sta&le deice t7at c7anges state on co66and f!o6 a
co66on in1ut te!6inal.
a) 4ro+ EF 4-ip '-op:
23 ty1e fli10flo1 connected as a toggle ty1e. On eac7 cloc; 1ulse 1ositie going edge,
N <ill go to t7e state &a! N <as &efo!e t7e cloc; 1ulse a!!ied. Re6e6&e! t7at &a! N
is t7e o11osite leel to N. T7e!efo!e N <ill toggle.
E%erci&e:
1. Ae!ify t7e gates.
2. Da;e t7e connections as 1e! t7e ci!cuit diag!a6.
". A11ly and e!ify t7e a!ious co6&ination of in1ut acco!ding to t7e t!ut7 ta&le.
. 4-ip 4-op
a) ,&ing Logic gate&
Since t7e ena&le in1ut on a gated S0R latc7 1!oides a <ay to latc7 t7e N and not0N
out1uts <it7out !ega!d to t7e status of S o! R, <e can eli6inate one of t7ose in1uts
to c!eate a 6ultii&!ato! latc7 ci!cuit <it7 no OillegalO in1ut states. Suc7 a ci!cuit is
called a D latc7.

4igure: T7e D0ty1e fli10flo1 8logic gates9
Note t7at t7e R in1ut 7as &een !e1laced <it7 t7e co61le6ent 8ine!sion9 of t7e old S
in1ut, and t7e S in1ut 7as &een !ena6ed to D. As <it7 t7e gated S0R latc7, t7e D
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Stage, Bangalore Page "" o! "#
latc7 <ill not !es1ond to a signal in1ut if t7e ena&le in1ut is 4 00 it si61ly stays
latc7ed in its last state. G7en t7e ena&le in1ut is 1, 7o<ee!, t7e N out1ut follo<s
t7e D in1ut.
Since t7e R in1ut of t7e S0R ci!cuit!y 7as &een done a<ay <it7, t7is latc7 7as no
OinalidO o! OillegalO state. N and not0N a!e al<ays o11osite of one anot7e!.
b) ,&ing .ua- .'-ip '-op (IC /#/#)
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OPERATING
MODE
INPUTS OUTPUTS
S
D
R
D
P D ! !
A!*n' Set
A!*n' Re!et +Clear-
Un#etermine#
+a-
Loa# 6/6 +Set-
Loa# 626 +Re!et-
L
,
L

,
,
,
L
L

,
,
7
7
7

7
7
7

"
l
,
L
,

,
L
L
,
L

L
,
Laborator$ E%erci&e !" > !1 : Shi't Regi&ter&
S7ift !egiste!s a!e a ty1e of se=uential logic ci!cuit, 6ainly fo! sto!age of digital data.
T7ey a!e a g!ou1 of fli10flo1s connected in a c7ain so t7at t7e out1ut f!o6 one fli10
flo1 &eco6es t7e in1ut of t7e ne>t fli10flo1. Dost of t7e !egiste!s 1ossess no
c7a!acte!istic inte!nal se=uence of states. All fli10flo1s a!e d!ien &y a co66on cloc;,
and all a!e set o! !eset si6ultaneously. T7e sto!age ca1acity of a !egiste! is t7e total
nu6&e! of &its 81 o! 49 of digital data it can !etain. ?ac7 stage 8fli1 flo19 in a s7ift
!egiste! !e1!esents one &it of sto!age ca1acity. T7e!efo!e t7e nu6&e! of stages in a
!egiste! dete!6ines its sto!age ca1acity.
SISO :
+onnect u1 t7e fou! &it data !egiste! as s7o<n in (igu!e &elo<. An n0&it &ina!y <o!d
can &e sto!ed &y n suc7 fli10flo1sL called a n0&it !egiste!.
At t7e sta!t, t7e contents of t7e !egiste! can &e set to #e!o &y 6eans of t7e +L?AR
line. *f a 1 is a11lied to t7e in1ut of t7e fi!st fli10flo1, t7en u1on t7e a!!ial of t7e
fi!st cloc; 1ulse, t7is 1 is t!ansfe!!ed to t7e out1ut of fli10flo1 1 8in1ut of fli10flo1 29.
Afte! fou! cloc; 1ulses t7is 1 <ill &e at t7e out1ut of fli10flo1 '. *n t7is 6anne!, a
fou! &it nu6&e! can &e sto!ed in t7e !egiste!. Afte! fou! 6o!e cloc; 1ulses, t7is data
<ill &e s7ifted out of t7e !egiste!.
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SIPO :
Data is fed into t7e S?R*AL *N%:ARALL?L OUT s7ift !egiste! &it &y &it, in t7e sa6e
<ay as fo! t7e S*SO s7ift !egiste!. $o<ee! t7e fou! &its a!e all s7ifted out
si6ultaneously, in 1a!allel, as one <o!d.
Cloc( Pl!e No 882 88/ 889 88:
2 2 2 2 2
/ / 2 2 2
9 2 / 2 2
: 2 2 / 2
0 2 2 2 /
4 2 2 2 2
PISO
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CLF
Git7 t7e :ARALL?L *N%S?R*AL OUT s7ift !egiste!, fou! &its a!e s7ifted into t7e
!egiste! si6ultaneously, in 1a!allel. T7ey a!e t7en cloc;ed out, one afte! t7e ot7e!,
in se!ial fo!6.
PIPO
T7e :ARALL?L *N%:ARALL?L OUT s7ift !egiste! is loaded <it7 fou! &its
si6ultaneously, in 1a!allel. T7ey a!e also cloc;ed out si6ultaneously, in 1a!allel.
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Laborator$ E%erci&e !#: Odd and E)en Parit$ ChecHer
Co+ponent& : *+ ,'1-4 8- &it 1a!ity c7ec;e!%gene!ato!9
Theor$:
G7en digital data is t!ans6itted f!o6 one location to anot7e!, it is necessa!y
to ;no< at t7e !eceiing end, <7et7e! data !eceied is f!ee f!o6 e!!o!s. To 7el1
6a;e t7e t!ans6ission accu!ate, s1ecial e!!o! detection 6et7ods a!e used. To detect
e!!o!s t7e!e 6ust &e constant c7ec; on t7e data &eing t!ans6itted. To c7ec;
accu!acy of t7e data an e>t!a &it can &e gene!ated and t!ans6itted along <it7 t7e
data. T7is &it is called t7e 1a!ity &it. A 1a!ity &it is used fo! detecting e!!o!s du!ing
t!ans6ission of &ina!y info!6ation.
:a!ity gene!ato!s a!e ci!cuits t7at acce1t an n01 &it data st!ea6 and
gene!ate an e>t!a &it t7at is t!ans6itted <it7 t7e &it st!ea6. T7is e>t!a &it is
!efe!!ed to as 1a!ity &it. *n an een 1a!ity &it sc7e6e, t7e 1a!ity &it is M1K if t7e!e a!e
odd nu6&e! of 1Ks in t7e data st!ea6 and t7e 1a!ity &it is M4K if t7e!e a!e een
nu6&e! of 1Ks in t7e data st!ea6. *n t7e case of odd 1a!ity &it sc7e6e, t7e !ee!se
7a11ens, t7at is t7e 1a!ity &it is M4K fo! odd nu6&e! of 1Ks and M1K fo! een nu6&e! of
1Ks in t7e &it st!ea6.
T7e - in1uts fo! t7e :a!ity c7ec;e! is gien &y A t7!oug7 $ in t7e 1in diag!a6 and
t7e sa6e is !efe!!ed as 4 t7!oug7 , in t7e t!ut7 ta&le.
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Digital Electronics Lab Manual

Department of BCA, PESIT, Bangalore

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