Fundamentals of Electronics

Jomo Kenyatta University of Agriculture
and Technology
Department of Electrical and Electronic Engineering
Lecture Notes for the Course
ICS2200 / BCT 2205
ELECTRONICS
Lecturer: Mr. B. NGOKO
email: ngokobonface@gmail.com
Semester: SEPT DEC 2013
1
ICS 2200 - 2013 1 BASIC DEFINITIONS
1 Basic Denitions
Electric charge - the physical property of matter that causes it to experience a
force when close to other electrically charged matter (measured in Coulombs): - 1
Coulomb of negative change contains 6.241 10
1
8 electrons.
Current movement of electric charge (measured in Amperes): 1 ampere is a steady
ow of 1 Coulomb of charge past a given point in a conductor in 1 second.
I(amperes) =
Q(coulombs)
t(seconds)
for a time varying current
i(t) = lim
t0
q(t + t) q(t)
t
=
q
t
Voltage the electric potential dierence between two points. The work in joules
required to move 1 coulomb of charge from one point to the other.
V (volts) =
W(joules)
Q(coulombs)
Power the rate at which something either absorbs or produces energy. The power
absorbed by an electric element is the product of the voltage and the current.
P(watts) =
W(joules)
t(seconds)
= V (volts) I(amperes)
Electrical conduction the movement of electrically charged particles through a
transmission medium. The movement can form an electric current in response to an
electric eld. The underlying mechanism for this movement depends on the material.
Conduction in metals is well described by Ohms Law, which states that the current
is proportional to the applied electric eld. The ease with which current density
(current per area) J appears in a material is measured by the conductivity , dened
as:
J = E
or its reciprocal resistivity :
J =
E
In terms of voltage and current, Ohms law can be stated as:

V (volts) = I(amperes) R(Ohms)
2
ICS 2200 - 2013 2 CONDUCTION OF ELECTRICITY
2 Conduction of Electricity
2.1 Conduction in Solids
Band Theory
This is a theoretical model describing the states of electrons within a solid structure.
The theory states that electrons can have values of energy only within certain specic
ranges. The ranges of allowed energies of electrons in a solid are called allowed bands.
Certain ranges of energies between two such allowed bands are called forbidden bands -
i.e., electrons within the solid may not possess these energies.
Electrons of an atom may therefore be divided into two groups:
i, Core electrons Consist of electrons which are relatively close to the nucleus and
which occupy energy levels in which they are tightly bound to the atom.
ii, Valence electrons The outermost electrons of the atom and are the least tightly
bound to the atom. The valence electrons may be shared by other atoms in the
formation of molecules. In general, an atom may have up to 8 valence electrons.
The band theory accounts for many of the electrical and thermal properties of solids and
forms the basis of the technology of solid-state electronics.
The band of energies permitted in a solid is related to the discrete allowed energies
- the energy levels - of single, isolated atoms. When the atoms are brought together to
form a solid, these discrete energy levels become perturbed through quantum mechanical
eects, and the many electrons in the collection of individual atoms occupy a band of
levels in the solid called the valence band. Empty states in each single atom also broaden
into a band of levels that is normally empty, called the conduction band.
The valence band is the highest range of electron energies in which electrons are nor-
mally present at absolute zero temperature.
The conduction band is the range of electron energies enough to free an electron from
binding with its atom to move freely within the atomic lattice of the material as a delo-
calized electron. Various materials may be classied by their band gap: this is dened
as the dierence between the valence and conduction bands.
Just as electrons at one energy level in an individual atom may transfer to another
empty energy level, so electrons in the solid may transfer from one energy level in a given
band to another in the same band or in another band, often crossing an intervening gap
of forbidden energies. Studies of such changes of energy in solids interacting with photons
of light, energetic electrons, X-rays, and the like conrm the general validity of the band
theory and provide detailed information about allowed and forbidden energies.
A variety of ranges of allowed and forbidden bands is found in pure elements, alloys,
and compounds. Three distinct groups are usually described: conductors, insulators, and
semiconductors.
3
Figure 1: Electron energy bands
In metals (conductors), forbidden bands do not occur in the energy range of the most
energetic (outermost) electrons. Accordingly, metals are good electrical conductors.
Insulators have wide forbidden energy gaps that can be crossed only by an electron
having an energy of several electron volts. Because electrons cannot move freely in
the presence of an applied voltage, insulators are poor conductors.
Semiconductors have relatively narrow forbidden gaps - which can be crossed by
an electron having an energy of roughly one electron volt and so are intermediate
conductors.
Figure 2: Classication of solids based on electron energy bands
4
2.2 Conduction in Gases
In air, and other ordinary gases below the breakdown eld, the dominant source of elec-
trical conduction is via a relatively small number of mobile electrons and ions produced
by radioactive gases, ultraviolet light, or cosmic rays. Since the electrical conductivity is
extremely low, gases are dielectrics or insulators.
Suppose a free electron exists (caused by some external eect such as radio-activity or
cosmic radiation) in a gas where an electric eld exists. If the eld strength is suciently
high, then it is likely to collide with a neutral gas atom or molecule thereby ionizing it
resulting in 2 free electrons and a positive ion.
These 2 electrons will be able to cause further ionization by collision leading in general
to 4 electrons and 3 positive ions. The process is cumulative, and the number of free
electrons will go on increasing as they continue to move under the action of the electric
eld. The swarm of electrons and positive ions produced in this way is called an electron
avalanche and results in the breakdown of the gas in what is known as an avalanche
breakdown. In the space of a few millimeters, the avalanche may grow until it contains
many millions of electrons as shown in Figure 3.
Figure 3: Electron avalanche
The breakdown process forms a plasma that contains a signicant number of mobile
electrons and positive ions, causing it to behave as an electrical conductor. In the process,
it forms a light emitting conductive path, such as a spark, arc or lightning.
2.3 Conduction in vacuum
A perfect vacuum contains no charged particles. Therefore, vacuums normally behave as
very good insulators. However, metal electrode surfaces can cause a region of the vacuum
to become conductive by injecting free electrons or ions through either eld emission or
thermionic emission.
Thermionic emission occurs when the thermal energy exceeds the metals work func-
tion
1
, while
1
the work function (sometimes spelled workfunction) is the minimum thermodynamic work (i.e. en-
ergy) needed to remove an electron from a solid to a point in the vacuum immediately outside the solid
surface.
5
eld emission occurs when the electric eld at the surface of the metal is high enough
to cause tunneling
2
, which results in the ejection of free electrons from the metal
into the vacuum.
2
the quantum-mechanical eect where a particle crosses through a classically-forbidden potential energy
barrier
6
ICS 2200 - 2013 3 SEMICONDUCTOR DIODES
3 Semiconductor Diodes
3.1 Semiconductors
Materials that permit ow of electrons are called conductors (e.g., gold, silver, cop-
per, etc.).
Materials that block ow of electrons are called insulators (e.g., rubber, glass, Teon,
mica, etc.).
Materials whose conductivity falls between those of conductors and insulators are
called semiconductors. Semiconductors are part-time conductors whose conduc-
tivity can be controlled and are used in many applications in electronics.
3.2 Intrinsic Silicon
Silicon is the most common material used to build semiconductor devices. Si is the main
ingredient of sand and it is estimated that a cubic mile of seawater contains 15,000 tons of
Si. Si is spun and grown into a crystalline structure and cut into wafers to make electronic
devices.
Figure 4 shows the 2-D structure of intrinsic silicon.
Figure 4: Two-dimensional representation of the silicon crystal.
Each atom shares each of its 4 valence electrons with a neighboring atom. These
atoms are held in their positions by covalent bonds which are intact at suciently
low temperatures. Because the bonds are not broken, no free electrons are available
to conduct current in intrinsic (pure) silicon.
7
Covalent bonds may be broken by thermal ionization (Figure 5). Under thermal
ionization, an electron leaves its parent atom due to acquired heat energy; thus, a
positive charge is left with the atom. The ionization results in free electrons and
holes in equal numbers. Because ow of current is due to the movement of electrons
and holes within the material, they are known charge carriers.
Figure 5: Electrons and holes generated by thermal ionization.
At room temperature, silicon has about 1.5 10
10
carriers/cm
3
and about 5 10
22
atoms/cm
3
. The concentration of free electrons n is equal to the concentration of
free holes p.
n = p = n
i
n
i
is the number of free electrons (or holes) per cm
3
in intrinsic silicon at a given
temperature.
An electron from a neighboring atom may be attracted to an existing hole hence
moving and creating a new hole. The ionization rate is therefore equal to the re-
combination rate in thermal equilibrium.
The process repeats as a hole moves through the silicon and conducts current.
The movement of holes and electrons through silicon can be by diusion or drift
mechanisms.
Diusion mechanism - This is random motion due to thermal agitation. Non-uniform
concentrations of free electrons and holes cause a net ow of charge (or diusion
current) (Figure 6).
Drift mechanism - Carrier drift occurs when an electric eld is applied across a piece
of silicon. The free electrons and holes are accelerated by the electric eld and
acquire a drift velocity (superimposed on the velocity of thermal motion).
8
Figure 6: Illustration of the diusion mechanism: (a) a bar of intrinsic silicon, and (b) the
hole concentration prole.
3.3 Doped Silicon
In the crystalline lattice structure of Si, the valence electrons of every Si atom are locked
up in covalent bonds with the valence electrons of four neighboring Si atoms. Therefore
in pure form, Si wafer does not contain any free charge carriers. An applied voltage across
pure Si wafer does not yield electron ow through the wafer and a pure Si wafer is said to
act as an insulator.
In order to make useful semiconductor devices, materials such as phosphorus (P) and
boron (B) are added to Si to change its conductivity.
Such Si is said to be doped. Doping is achieved by introducing a small number of
impurity atoms into the pure Si. This leads to two types of doped Si.
3.3.1 n-type silicon
Pentavalent impurities such as phosphorus, arsenic, antimony, and bismuth have 5 valence
electrons. When phosphorus impurity is added to Si, every phosphorus atoms four valence
electrons are locked up in covalent bond with valence electrons of four neighboring Si
atoms. However, the 5
th
valence electron of the phosphorus atom does not nd a binding
electron and thus remains free to oat. When a voltage is applied across the silicon-
phosphorus mixture, free electrons migrate toward the positive voltage end.
When phosphorus is added to Si to yield the above eect, we say that Si is doped
with phosphorus. The resulting mixture is called n-type silicon (n: negative charge carrier
silicon).
The pentavalent impurities donate electrons to the pure Si structure and are thus
referred to as donor impurities
The majority of carriers in n-type Si are the negatively charged electrons.
9
Figure 7: Doped n-type semiconductor.
3.3.2 p-type silicon
Trivalent impurities e.g., boron, aluminum, indium, and gallium have 3 valence electrons.
When boron is added to Si, every boron atoms three valence electrons are locked up in
covalent bond with valence electrons of three neighboring Si atoms. However, a vacant
spot hole is created within the covalent bond between one boron atom and a neighboring
Si atom. The holes are considered to be positive charge carriers. When a voltage is applied
across the silicon-boron mixture, a hole moves toward the negative voltage end while a
neighboring electron lls in its place.
Figure 8: Doped p-type semiconductor.
When boron is added to Si to yield the above eect, we say that Si is doped with boron.
The resulting mixture is called p-type silicon (p: positive charge carrier silicon).
The trivalent impurities accept electrons from the pure Si structure and are thus
referred to as acceptor impurities.
In p-type silicon, the majority of carriers are the positively charged holes.
10
3.4 The Semiconductor Diode
A diode is a two-lead semiconductor device that acts as a one way gate to electron ow.
The diode allows current to pass in only one direction.
Figure 9: The diode symbol.
A pn-junction diode is formed by joining together n-type and p-type silicon. In practice,
as the n-type Si crystal is being grown, the process is abruptly altered to grow p-type Si
crystal. Finally, a glass or plastic coating is placed around the joined crystal. The p-side
is called the anode and the n-side is called the cathode.
3.4.1 The pn Junction Under Open Circuit
Figure 10 shows the pn junction under open circuit.
Figure 10: (a) The pn junction with no applied voltage (open-circuited terminals). (b)
The potential distribution along an axis perpendicular to the junction.
Electrons diuse across the junction and combine with majority holes. Thus in the
p-type silicon, there will be a region depleted of holes and containing uncovered bound neg-
ative charge. Holes also diuse across the junction and combine with majority electrons.
Hence in the n-type silicon, there will be a region depleted of electrons and containing
uncovered bound positive charge.
11
This creates a region around the junction depleted of charge carriers known as a de-
pletion region. The bound charges on both sides of the depletion region forms a junction
built-in voltage. The built-in voltage V
0
for silicon at room temperature is 0.6 0.8V .
The electric eld acts as a barrier that must be overcome for holes and electrons to
diuse across the junction. The depletion regions exist in both sides with equal among of
charges. However if the doping concentration is dierent, The depletion layer will extend
deeper into the more lightly doped material.
When the anode and cathode of a pn-junction diode are connected to external voltage
such that the potential at anode is higher than the potential at cathode, the diode is
said to be forward biased. Generally, in a forward-biased diode current is allowed to ow
through the device. When potential at anode is smaller than the potential at cathode, the
diode is said to be reverse biased. Generally, in a reverse-biased diode, current is blocked.
3.5 pn junction i v Characteristics
The pn junction i-v characteristics are shown in gure 11
Figure 11: The diode i v relationship with some scales expanded and others compressed.
The forward region of operation is entered when the terminal voltage v is positive.
The i v curve in the forward region is closely approximated by
i = I
S
_
e
v/nV
T
1
_
where I
S
is called the saturation current; V
T
is called thermal voltage, which is 25mV
at room temperature; and n is a value between 1 and 2 which depends on the material
and physical structure of the diode. By default, n = 1 unless otherwise specied.
12
Usually a cut-in voltage of the diode is specied as a consequence of the exponential
i v relationship. When v is less than the cut-in voltage, the current i is negligible. When
v is greater than the cut-in voltage, the current i grows exponentially (fully conducting).
Typically, the cut-in voltage is about 0.5 - 0.7 V. The cut-in voltage varies with temperature
for a given diode.
The reverse region is entered when the terminal voltage v is made negative. The
reverse current is largely due to leakage eects. These leakage currents are proportional
to the junction area. Real diodes exhibit reverse currents that are much larger than I
s
.
As the reverse voltage is increased, the diode enters the breakdown region. The
breakdown region is entered when the reverse voltage exceeds breakdown voltage V
ZK
.
The reverse current i increases rapidly with very small increase in voltage drop. This is a
good property for voltage regulation.
Junction breakdown creates many carriers by Zener or avalanche mechanisms so as
to support any value of reverse current. It is not a destructive process as long as the
maximum power dissipation is not exceeded.
Zener breakdown
It occurs when the breakdown voltage 7V < V
Z
< 5V . The electric eld in the depletion
regions increases to a point where it can break covalent bonds and generate electron-hole
pairs. The holes will be swept into the n side while the electrons will be swept into the p
side. These electrons and holes constitute a reverse current across the junction.
Avalanche breakdown
It occurs when the breakdown voltage V
Z
> 7V . Minority carriers gain sucient energy
by the electric eld to break the covalent bonds. The carriers may have sucient energy
to cause other carriers to be liberated in another ionizing collision.
3.6 Special Diodes
3.6.1 Zener diode
Zener diodes are specically designed to operate in the breakdown region. The steep
i v characteristic is ideal for voltage regulators. Voltage regulators are circuits that
need to provide constant dc output voltages in the face of changes in load current and/or
system power-supply voltage.
The Zener diode model is shown in gure 13. The Zener diode parameters include:
The voltage V
Z
across the diode at a testing current I
ZT
(The operating point).
The incremental resistance r
z
at the operation point.
The knee current I
ZK
.
13
Figure 12: Symbol of Zener diode and its i-v characteristics.
Figure 13: The Zener diode model.
The i v curve for currents greater than I
ZK
is almost a straight line. The model of Zener
diodes in breakdown region is specied by the equation:
V
Z
= V
Z0
+ r
z
I
Z
The above equation holds for I
Z
> I
ZK
and V
Z
> V
Z0
where V
Z0
is the intersection of the
straight line of slope 1/r
z
and the voltage axis.
3.7 Diode Applications
3.7.1 Voltage Regulator
Consider the Zener diode connected as shown in Figure 14. The change in output voltage
V
0
as a result of change in source voltage V can be obtained from:
I = I
Z
+ I
L
14
Figure 14: Symbol of Zener diode and its i-v characteristics.
i.e.
V V
0
R
=
V
0
V
Z0
r
z
+
V
0
R
L
Re-arranging gives
V
0
=
R
L
(r
z
V + RV
Z0
)
R
L
r
z
+ RR
L
+ Rr
z
and the change in V
0
due to a change in V is therefore:
V
0
V
=
R
L
r
z
R
L
r
z
+ RR
L
+ Rr
z
=
r
z
r
z
+ R +
Rr
z
R
L
Example: Given R
L
= 2 k, R = 0.5 k, and r
z
= 20 ; then
V
0
V
=
0.02
0.02 + 0.05 +
0.50.02
2.0
= 38.1 mV/V
without the Zener diode,
V
0
V
=
R
L
R + R
L
=
2.0
2.0 + 0.5
= 800 mV/V
Similarly, a change in load current due to a change in R
L
will result in a change in I
Z
and the change in V
0
due to a change in V is given by:
V
0
I
Z
= r
z
Example
Figure 14 shows the use of a Zener diode as a Shunt Voltage Regulator which appears in
parallel with the load. The 6.8-V Zener diode in Figure 14 is specied to have V
Z
= 6.8 V
at I
Z
= 5 mA, r
Z
= 20 , and I
ZK
= 0.2 mA. The load resistance R
L
= 2k. The
15
supply voltage V
+
is normally 10 V but can vary by 1 V . a) Calculate V
Z0
and the
output voltage V
0
at V
+
= 9V and V
+
= 10V , and V
+
= 11V . What would be V
0
at
V
+
= 9V , V
+
= 10V , and V
+
= 11V without the voltage regulator. b) Calculate V
0
at
a load resistance of R
L
= opencircuit, R
L
= 2k and R
L
= 1k. What is the minimum
value of R
L
so that the Zener diode operates as required?
3.7.2 Diode Rectier
A diode rectier is an essential building block of the dc power supply. Figure 15 depicts
the block diagram of the dc power supply. It has the following components:
Figure 15: Block diagram of a dc power supply.
Power transformer - Steps down the line voltage to the required value. It also
minimizes the risk of electric shock by providing electrical isolation between the
equipment and the power line.
Diode rectier - Converts the input sinusoid to a unipolar output. Two parameters
must be specied in selecting the diodes i.e. the largest current the diode is expected
to conduct and the largest reverse current that is expected to withstand without
breakdown. (Peak Inverse Voltage)
Filter - Converts the pulsating waveform to a constant output.
Voltage regulator - Reduces the voltage ripple. It also stabilizes the dc output as the
load current changes.
Half-Wave Rectier
Figure 16 shows an example of half-wave rectier. It utilizes alternate half-cycles of the
input sinusoid to produce a unipolar output. The Peak Inverse Voltage PIV = V
S
.
v
o
=
_
_
_
0 if V
S
< V
D0
R
R+r
D
(V
S
V
D0
) if V
S
V
D0
16
Figure 16: Half-wave rectier.
Full-Wave Rectier
Figure 17: Full-wave rectier.
17
Figure 17 shows an example of a full-wave rectier. It utilizes both halves of the input
sinusoid. When the input voltage is positive, both of the v
S
signals will be positive. Diode
D
1
will conduct and D
2
will be reverse biased. When the input voltage is negative, both of
the v
S
signals will be negative. Diode D
1
will be reverse biased and D
2
will conduct. v
o
is
unipolar since the current always ows through R in the same direction. PIV = 2V
S
V
D
.
A center-tapped transformer is required.
Figure 18 shows another implementation of the full-wave rectier (known as a bridge
rectier). When the input voltage is positive, the signals v
S
will be positive. Diodes
D
1
and D
2
will conduct; D
3
and D
4
will be reverse biased. When the input voltage
is negative, the signals v
S
will be negative. D
3
and D
4
will conduct; D
1
and D
2
will
be reverse biased. v
o
is unipolar since the current always ows through R in the same
direction. PIV = v
o
+ v
D2
(forward) = V
S
2V
D
+ V
D
= V
S
V
D
.
Figure 18: Full-wave bridge rectier.
The bridge rectier has the following advantages:
1. The PIV is about half the value for the center-tapped implementation.
2. A center-tapped transform is not required.
3. Less turns are required for the secondary winding of the transformer.
3.7.3 Voltage Limiting (Clipping Circuits)
A limiter (also known as clipper) limits the voltage between the two output terminals.
The transfer function of the limiter is given by:
v
o
=
_
_
L
if v
I
< L
/K
Kv
I
if L
/K v
I
L
+
/K
L
+
if v
I
> L
+
/K
Diodes can be combined with resistors to implement limiters.
Figure 20 (a) and (b) are single limiters. Single limiters work for either positive or
negative peaks. Figure 20 (c) is a double limiter. The double limiter works for both
18
Figure 19: Transfer characteristic for a limiter circuit.
positive and negative peaks. Figure 20 (d) shows that the threshold and saturation current
can be controlled by using strings of diodes and/or by connecting a dc voltage in series
with the diode. Figure 20 (e) shows another double limiter using double-anode Zener.
3.7.4 Digital Logic
Diodes can also be used for logic gates as shown in Figure 21.
19
Figure 20: A variety of basic limiting circuits.
Figure 21: Digital logic gates: (a) OR gate; (b) AND gate. (Positive logic system)
20
ICS 2200 - 2013 4 BIPOLAR JUNCTION TRANSISTORS (BJTS)
4 Bipolar Junction Transistors (BJTs)
A transistor is a three lead semiconductor device that is generally used either as an
electrically controlled switch, or a current amplier.
4.1 BJT Structure
The Bipolar Junction Transistor (BJT) is a transistor with three regions and two pn
junctions. The regions are named the emitter, the base, and the collector and each is
connected to a lead. There are two types of BJTs - the npn and the pnp types.
4.1.1 NPN Transistor
Figure 22 depicts a simplied NPN transistor. The emitter (E) is a heavily doped n-type
region. The Base (B) is a lightly doped p-type region and the Collector (C) is a heavily
doped n-type region. It is practically two diodes connected in series on opposite directions.
The mode of operation of the transistor depends on the biasing of the two junctions.
Figure 22: A simplied structure and circuit symbol of the NPN transistor.
4.1.2 PNP Transistor
Figure 23 depicts a simplied PNP transistor. The emitter (E) is a heavily doped p-type
region. The Base (B) is a lightly doped n-type region and the Collector (C) is a heavily
doped p-type region. It is also two diodes connected in series on opposite directions. The
mode of operation of the transistor depends on the biasing of the two junctions.
Figure 23: A simplied structure and circuit symbol of the PNP transistor.
21
4.2 The NPN Transistor i v Characteristics
4.2.1 Common Base Characteristics
The common-base (CB) connection is a two-port transistor arrangement in which the
base shares a common point with the input and output terminals. The independent
input variables are emitter current i
E
and base-to-emitter voltage v
EB
. The corresponding
independent output variables are collector current i
C
and base-to-collector voltage v
CB
.
Figure 24: PNP transistor Common Base connection.
(a) (b)
Figure 25: PNP transistor CB Characteristics.
Practical CB transistor analysis is based on two experimentally determined sets of
curves:
1. Input or transfer characteristics relate i
E
and v
EB
(port input variables), with v
CB
(port output variable) held constant. The method of laboratory measurement is
indicated in Fig. 24 and the typical form of the resulting family of curves is depicted
in Fig. 25 (a).
2. Output or collector characteristics give i
C
as a function of v
CB
(port output variables)
for constant values of i
E
(port input variable) measured as in Fig. 24. Figure 25 (b)
shows the typical form of the resulting family of curves.
22
4.2.2 Common Emitter Characteristics
The common-emitter (CE) connection is a two-port transistor arrangement (widely used
because of its high current amplication) in which the emitter shares a common point with
the input and output terminals. The independent port input variables are base current i
B
and emitter-to-base voltage v
BE
, and the independent port output variables are collector
current i
C
and emitter-to-collector voltage v
CE
. Like CB analysis, CE analysis is based
on:
Figure 26: NPN transistor Common Emitter connection.
(a) (b)
Figure 27: NPN transistor CE Characteristics.
1. Input or transfer characteristics that relate the port input variables i
B
and v
BE
,
with v
CE
held constant. Figure 26 shows the measurement setup, and Fig. 27 (a)
the resulting input characteristics.
2. Output or collector characteristics that show the functional relationship between
port output variables i
C
and v
CE
for constant i
B
, measured as in Fig. 26. Typical
collector characteristics are displayed in Fig. 27 (b).
23
4.2.3 Current Relationships
The two pn junctions of the BJT can be independently biased, to result in four possible
transistor operating modes as summarized in Table 1. A junction is forward-biased if the
n material is at a lower potential than the p material, and reverse-biased if the n material
is at a higher potential than the p material.
Table 1: NPN transistor operation modes for the CE connection
Emitter-Base Bias Collector-Base Bias Operating Mode
forward forward saturation
reverse reverse cut-o
reverse forward inverse
forward reverse linear or active
Saturation denotes operation (with |v
CE
| 0.2 V and |v
BC
| 0.5 V for Si devices)
such that maximum collector current ows and the transistor acts much like a closed
switch from collector to emitter terminals. [See Figures 25 (b) and 27 (b).]
Cuto denotes operation near the voltage axis of the collector characteristics, where
the transistor acts much like an open switch. Only leakage current (similar to I
0
of the
diode) ows in this mode of operation; thus, i
C
0 for CB connection, and i
C
0 for CE
connection. Figures 25 (b) and 27 (b) indicate these leakage currents.
The inverse mode is a little-used, inecient active mode with the emitter and collector
interchanged.
The active or linear mode describes transistor operation in the region to the right of
saturation and above cuto in Figs. 25 (b) and 27 (b); here, near-linear relationships exist
between terminal currents, and the following constants of proportionality are dened for
dc currents:
=
I
C
I
E
=
I
C
I
B
also, by KCL,
I
E
= I
B
+ I
C
hence
=

1
The equation: I
C
= I
B
denotes the dc current amplication characteristic of the
BJT: The base current is essentially increased or amplied times to become the collector
current.
24
4.2.4 Transistor Biasing
Supply voltages and resistors bias a transistor; that is, they establish a specic set of dc
terminal voltages and currents, thus determining a point of active-mode operation (called
the quiescent point or Q point). Usually, quiescent values are unchanged by the application
of an ac signal to the circuit.
Consider the circuit of g 28. The dc currents I
B
, I
C
, and I
E
; the terminal voltages
V
B
, V
E
, V
C
and V
CE
can be obtained using basic electrical circuit laws as follows:
Figure 28: BJT Biasing.
Using KVL in the base-to-emitter loop:
V
BB
I
B
R
B
V
BE
I
E
R
E
= 0
but I
E
= ( + 1)I
B
hence, we can write
I
B
=
V
BB
V
BE
R
B
+ ( + 1)R
E
also I
C
= I
B
or by KCL, I
C
= I
E
I
B
The terminal voltages are:
V
B
= V
BB
I
B
R
B
V
E
= V
B
V
BE
= I
E
R
E
and
V
C
= V
CC
I
C
R
C
The transistor operating point (Q-point) is therefore set by the values of V
BB
, V
CC
,
R
B
, R
C
, and R
E
.
25
Voltage Divider Bias
The universal biasing arrangement is shown in Fig. 29 where only one dc power supply
(V
CC
) is needed to establish active-mode operation.
Figure 29: BJT Voltage Divider Biasing.
Because the base current is small, the voltage divider approximation
V
B
=
_
R
1
R
1
+ R
2
_
V
CC
is accepted for calculating the base voltage.
After calculating V
B
, V
E
can be obtained by subtracting V
BE
(usually 0.7 V):
V
E
= V
B
V
BE
I
E
is then calculated by applying Ohms law to R
E
:
I
E
=
V
E
R
E
The approximation I
C
= I
E
is also valid.
Consequently, the collector voltage can be found from:
V
C
= V
CC
I
C
R
C
and
V
CE
= V
C
V
E
26
4.2.5 DC and AC Load Lines
The Q-point of a transistor can be obtained graphically using the load lines as explained
below:
Applying KVL to the collector-emitter-V
CC
loop in Fig. 29 gives:
V
CC
I
C
R
C
V
CE
I
E
R
E
= 0
but I
E
I
C
and the above equation can therefore be re-arranged as:
I
C
=
V
CE
R
C
+ R
E
+
V
CC
R
C
+ R
E
or
I
C
=
V
CE
R
dc
+
V
CC
R
dc
(1)
where R
dc
= R
C
+ R
E
.
Plotting I
C
against V
CE
as in (1) above gives a straight line curve cutting the I
C
axis
at V
CC
/R
dc
and the V
CE
axis at V
CC
. This I-V curve is known as the dc load line and
the point of intersection between this load line and the collector characteristics as shown
in Fig. 27 (b) dene the Q-point.
A load line is actually an I-V curve that represents the response of a circuit that is
external to a specied load and can be used in any electrical circuit to obtain voltages and
currents pertaining to a specic load.
ac operation
When a signal is applied to a transistor circuit, the output can have a larger amplitude
because the small base current controls a larger collector current. This increase is called
signal amplication.
Usually, for ac operation, capacitors are added to the circuit of Fig. 29 as shown in
Fig. 30. These capacitors have two uses:
1. Coupling capacitors (C
C
) conne dc quantities to the transistor and its bias circuitry.
2. Bypass capacitors (C
E
) eectively remove the gain-reducing emitter resistor R
E
insofar as ac signals are concerned, while allowing R
E
to play its role in establishing
the bias point.
For ac operation, an ac loadline is dened as:
i
C
=
v
CE
R
ac
+
V
CEQ
R
ac
+ I
CQ
(2)
where R
ac
= R
C
R
L
/(R
C
+ R
L
) is the parallel combination of R
C
and R
L
; V
CEQ
and I
CQ
are the dc Q-point values of i
C
and v
CE
.
27
Figure 30: BJT ac Operation.
All excursions of the ac signals i
c
and v
ce
are represented by points on the ac load line,
(2). If the value i
C
= I
CQ
is substituted into (2), we nd that v
CE
= V
CEQ
; thus, the ac
load line intersects the dc load line at the Q point.
4.2.6 The BJT as a switch
BJTs are used in switching applications when it is necessary to provide current drive to a
load.
In switching applications, the transistor is either in cuto or in saturation.
In cuto, the input voltage is too small to forward-bias the transistor. The output
(collector) voltage will be equal to V
CC
as shown in Fig. 31.
Figure 31: BJT in Cuto (OFF switch).
28
Conditions in Cuto: A transistor is in cuto when the base-emitter junction is not
forward biased.
I
B,cutoff
= I
C,cutoff
= 0 and V
CE
V
CC
Saturation occurs when the base current I
B
is sucient to saturate the transistor and
the transistor acts like a closed switch. The output is near 0 V.
Figure 32: BJT in Saturation (ON switch).
Conditions in Saturation: When the base-emitter junction is forward-biased and
there is enough base current to produce a maximum collector current, the transistor is
saturated.
I
C,saturation

V
CC
R
C
The minimum value of base current to produce saturation is thus:
I
B,min
=
I
C,saturation
but,
I
B
=
V
BB
V
BE
R
B
hence, the maximum value of R
B
to produce saturation is given by:
R
B,max
=
V
BB
V
BE
I
B,min
29
ICS 2200 - 2013 5 FIELD-EFFECT TRANSISTORS
5 Field-Eect Transistors
The eld-eect transistor (FET) is a voltage controlled device where the gate voltage
controls the drain current. This is in contrast with the BJT which is a current controlled
device. There are two types of FETs:
Junction Field Eect Transistor (JFET)
Metal-Oxide-Semiconductor Field Eect Transistor (MOSFET)
The operation of the FET can be explained in terms of only majority-carrier (one-
polarity) charge ow; the transistor is therefore called unipolar; again in contrast with the
bipolar BJT.
5.1 The JFET
JFETs can be either n-channel or p-channel. The basic structures for the two are shown
in Fig. 33. Conduction through the JFET is by the passage of charge carriers from source
(S) to drain (D) through the channel between the gate (G) elements. In the n-channel
JFET, conduction is by electrons while in the p-channel device, conduction is by holes;
a discussion of n-channel devices applies equally to p-channel devices if complementary
(opposite in sign) voltages and currents are used.
Figure 33: Basic structure of the JFET.
5.1.1 Basic Operation of the JFET
The basic operation of the JFET is illustrated in Fig. 34 which shows a biased n-channel
JFET. V
DD
is the drain-to-source voltage and provides the drain current I
D
. V
GG
sets
the reverse bias between the gate and the source. The JFET is always operated with the
gate-source pn junction reverse biased. The reverse bias produces a depletion region along
30
the p-n junction and increases the resistance of the channel which controls the current.
Therefore, V
GS
, the gate-source voltage can be changed to control the amount of drain
current I
D
owing in the channel.
Figure 34: Biased n- channel JFET.
Figure 35: Basic operation of the n- channel JFET.
5.1.2 JFET Symbols
The schematic symbols for the n-channel and p-channel JFETs are shown in Figure 36.
The in arrow on the gate indicates an n-channel JFET while the out arrow indicates
p-channel.
31
Figure 36: JFET schematic symbols.
5.1.3 JFET Characteristics
Typical output (drain) characteristic curves for an n-channel JFET are shown in gure
37: The nature of these curves can be explained as follows:
Figure 37: JFET schematic symbols.
Consider the case when gate-to-source voltage V
GS
= 0. Initially, as V
DD
and thus
V
DS
is increased, I
D
will increase. This region of the graph is called the Ohmic
Region and in this region, the channel resistance is constant. After a certain value
of V
DS
, the I
D
curve levels o and enters the active region. In this region, I
D
is
constant and this extends for a wide range of V
DS
values.
32
When V
GS
= 0, there is a small resistance to current ow from the source to drain
across the transistor channel. This is shown by the gure curve corresponding to
V
GS
= 0 which gives the largest value of I
D
.
Applying a negative voltage at the gate terminal reverse biases the gate-to-source
pn junction and results in the formation of a depletion region around the gate. The
depletion region penetrates the channel making it narrower and hence increases the
source-to-drain resistance. This therefore reduces the magnitude of I
D
As V
GS
is increased, the depletion region grows larger until a point reaches when
the entire channel is depleted of charge carries. At this time no amount of V
DS
will
result in the ow of I
D
. This is shown as the pinch o region in the characteristic
curves.
5.1.4 JFET Parameters
At V
GS
= 0V, the value of V
DS
where I
D
becomes constant is called Pinch-O voltage,
V
p0
. A given JFET has xed value of V
p0
given in datasheets.
At V
GS
= 0, the value of the constant drain current is called I
DSS
(Drain-to-Source
current gate-Shorted). I
DSS
is also given in datasheets. I
DSS
is the maximum current
a JFET can produce.
The value of V
GS
that makes I
D
approximately zero is the cuto voltage V
GS(off)
.
A JFET must be operated between V
GS
= 0 and V
GS(off)
.
NOTE: V
GS(off)
and V
p0
are always equal in magnitude but opposite in sign. i.e.
V
GS(off)
= V
p0
. Any one of the two parameters is mentioned in the datasheet but not
both.
5.1.5 JFET Universal Transfer Characteristic
Since V
GS
controls I
D
, it is important to determine the relationship between V
GS
and I
D
.
Fig. 38 shows a general characteristic curve that graphically shows how V
GS
and I
D
are
related. This graph is known as a transconductance curve.
The mathematical relation between the drain current I
D
and V
GS
can be given approx-
imately as:
I
D
= I
DSS
_
1
V
GS
V
GS(off)
_
2
= I
DSS
_
1
V
GS
V
p0
_
2
(3)
The above equation can determine I
D
for any given value of V
GS
if I
DSS
and V
p0
are
known. I
DSS
and V
p0
will be given in the transistor datasheets.
33
Figure 38: JFET universal transfer characteristic curve.
5.1.6 JFET Biasing
The main purpose of dc biasing is to select the proper dc gate-to-source voltage V
GS
to
establish a desired value of drain current I
D
which is the Q-point of the circuit. There are
3 types of bias circuit used with JFETs.
Self Bias
Voltage Divider Bias
Current Source Bias
Self-Bias
Self-bias is the most common type of bias circuit for the JFET. Fig. 39 shows the self-bias
circuits for both the n-channel and p-channel JFETs. The gate terminal being grounded
through R
G
results in V
G
= 0.
34
To set the Q-point for the self-bias circuit, rst either nd I
D
for some V
GS
or vice
versa. Then calculate the required R
S
by the relation:
R
S
=
V
GS
I
D
For a desired value of V

GS
, I
D
can be determined in two ways:
Graphically using the transfer characteristic curve.
Using the equation I
D
= I
DSS
_
1
V
GS
V
p0
_
2
where I
DSS
and V
p0
are given.
To determine the Q-point (I
D
and V
GS
) of a self biased JFET circuit, the transfer
characteristic curve can be used as follows:
1. If the curve is not given, plot the transfer characteristic curve using the equation of
I
D
and using the datasheet values of I
DSS
and V
p0
.
2. The DC load line is then established as follows (illustrated in Fig. 40):
At I
D
= 0 A, V
GS
= I
D
R
S
= 0 V. This gives us the rst point of the load line.
At I
D
= I
DSS
, V
GS
= I
D
R
S
= I
DSS
R
S
. This gives the second point. Con-
necting these two points establishes the load line.
The point where the load line intersects the transfer curve is the Q-point.
3. Note the corresponding values of I
D
and V
GS
at the Q-point.
35
5.2 The MOSFET
The n-channel MOSFET has only a single p region (called the substrate), one side of which
acts as a conducting channel. A metallic gate is separated from the conducting channel by
an insulating metal oxide (usually SiO
2
), hence the name insulated-gate FET (IGFET)
for the device. The p-channel MOSFET, formed by interchanging p and n semiconductor
materials, is described by complementary voltages and currents.
There are two main types of MOSFETs: enhancement type and depletion type each of
which can be manufactured with as n-channel or p-channel.
5.2.1 Enhancement-type MOSFETs
Fig. 41 illustrates an n-channel enhancement type MOSFET.
Figure 41: n-channel enhancement MOSFET.
With no bias voltage applied to the gate terminal, there exist two back-to-back p-n
junctions between the drain and the source hence no current ows from drain to
source.
When a voltage v
GS
is applied between the gate and source, free holes in the p-
type substrate are repelled from the region under the gate. This uncovers bound
negative charge in the channel region. Electrons from the heavily doped n
+
regions
(the drain and source) are attracted under the gate.
These eects create an n-type channel. The enhanced channel allows ow of current
when a voltage is applied between the drain and source.
5.2.2 Depletion-type MOSFETs
Fig. 42 illustrates an n-channel depletion-type MOSFET.
36
Figure 42: n-channel depletion MOSFET.
In the depletion type MOSFET, a thin layer of n-type silicon is deposited just below
the gateinsulating layer, and forms a conducting channel between source and drain.
Therefore even with no bias voltage applied to the gate terminal, current (in the
form of free electrons) can ow between source and drain.
When the gate is made negative with respect to the source, a depletion area free
from charge carriers is created beneath the gate.
This depletion of carries restricts the depth of the conducting channel, so increasing
channel resistance and reducing current ow through the device.
37
ICS 2200 - 2013 6 OPERATIONAL AMPLIFIERS
6 Operational Ampliers
The name operational amplier (op amp) was originally given to an amplier that could
be easily modied by external circuitry to perform mathematical operations (addition,
scaling, integration, etc.) in analog-computer applications. However, with the advent of
solid-state technology, op amps have become highly reliable, miniaturized, temperature-
stabilized, and consistently predictable in performance; they now gure as fundamental
building blocks in basic amplication and signal conditioning, in active lters, function
generators, and switching circuits.
6.1 Ideal and Practical Op Amps
An op amp amplies the dierence v
d
= v
1
v
2
between two input signals (see Fig. 43),
exhibiting the open-loop voltage gain:
A
OL
=
v
o
v
d
Figure 43: The Operational Amplier.
In Fig. 43, terminal 1 is the inverting input (labeled with a minus sign on the actual
amplier); signal v
1
is amplied in magnitude and appears phase-inverted at the output.
Terminal 2 is the noninverting input (labeled with a plus sign); output due to v
2
is phase-
preserved.
In magnitude, the open-loop voltage gain in op amps ranges from 10
4
to 10
7
. The
maximum magnitude of the output voltage from an op amp is called its saturation voltage;
this voltage is approximately 2 V smaller than the power-supply voltage. In other words,
the amplier is linear over the range
(V
CC
2) < v
o
< V
CC
2 V
The ideal op amp has three essential characteristics which serve as standards for as-
38
sessing the goodness of a practical op amp:
1. The open-loop voltage gain A
OL
is negatively innite.
2. The input impedance R
d
between terminals 1 and 2 is innitely large; thus, the input
current is zero.
3. The output impedance R
o
is zero; consequently, the output voltage is independent
of the load.
Figure 43(a) models the practical characteristics.
In application, a large percentage of negative feedback is used with the operational
amplier, giving a circuit whose characteristics depend almost entirely on circuit elements
external to the basic op amp. The error due to treatment of the basic op amp as ideal
tends to diminish in the presence of negative feedback.
6.2 Inverting Amplier
The inverting amplier of Fig. 44 has its noninverting input connected to ground or
common. A signal is applied through input resistor R
1
, and negative current feedback is
implemented through feedback resistor R
F
. The output v
o
has polarity opposite that of
input v
S
as shown below:
Figure 44: The Inverting Amplier.
By KCL at the inverting input,
i
1
= i
F
+ i
in
or
v
S
v
d
R
1
=
v
d
v
o
R
F
+
v
d
R
d
where R
d
is the dierential input resistance. But
v
d
=
v
o
A
OL
39
which, when substituted above, gives
v
S
v
o
/A
OL
R
1
=
v
o
/A
OL
v
o
R
F
+
v
o
/A
OL
R
d
rearranging the above equation gives:
v
S
R
1
=
v
o
A
OL
_
1
R
1
+
1
R
d
+
1
R
F
_
v
o
R
F
In the limit as A
OL
we get:
v
S
R
1
=
v
o
R
F
and the amplier voltage gain:
A
v
=
v
o
v
S
=
R
F
R
1
The above can also be proved using characteristic 2 of the ideal op amp i
in
= 0 as:
If i
in
= 0, v
d
= i
in
R
d
= 0 and i
1
= i
F
= i. We therefore have: v
S
= iR
1
and v
o
= iR
F
hence
A
v
=
v
o
v
S
=
R
F
R
1
6.3 Noninverting Amplier
The noninverting amplier of Fig. 45 is realized by grounding R
1
of Fig. 44 and applying
the input signal at the noninverting op amp terminal. When v
2
is positive, v
o
is positive
and current i is positive. Voltage v
1
= iR
1
then is applied to the inverting terminal as
negative voltage feedback.
Figure 45: The Noninverting Amplier.
40
We obtain the voltage gain of the noninverting amplier as follows:
Assume that the current into the inverting terminal of the op amp is zero, so that
v
d
0 and v
1
v
2
. With zero input current to the basic op amp, the currents through
R
2
and R
1
must be identical; thus,
v
o
v
1
R
2
=
v
1
R
1
and
A
v
=
v
o
v
2
=
v
o
v
1
= 1 +
R
2
R
1
6.4 Summer Amplier
The inverting summer amplier (or inverting adder) of Fig. 46 is formed by adding
parallel inputs to the inverting amplier of Fig. 44. Its output is a weighted sum of the
inputs, but inverted in polarity. In an ideal op amp, there is no limit to the number of
inputs; however, the gain is reduced as inputs are added to a practical op amp.
Figure 46: The Inverting Summer Amplier.
An expression for the output of the inverting summer amplier of Fig. 46 can be
found assuming the basic op amp is ideal as follows: Using the principle of superposition.
With v
S2
= v
S3
= 0, the current in R
1
is not aected by the presence of R
2
and R
3
,
since the inverting node is a virtual ground. Hence, the output voltage due to v
S1
is,
as for an inverting amplier; v
o1
= (R
F
/R
1
) v
S1
. Similarly, v
o2
= (R
F
/R
2
) v
S2
and
v
o3
= (R
F
/R
3
) v
S3
. Then, by superposition,
v
o
= v
o1
+ v
o2
+ v
o3
= R
F
_
v
S1
R
1
+
v
S2
R
2
+
v
S3
R
3
_
6.5 Dierentiating Amplier
The introduction of a capacitor into the input path of an op amp leads to time dier-
entiation of the input signal. The circuit of Fig. 47 represents the simplest inverting
dierentiator involving an op amp. The expression for the output of the inverting dier-
entiator of Fig. 47 assuming the basic op amp is ideal is found as:
41
Figure 47: The Dierentiating Amplier.
Since the op amp is ideal, v
d
0, and the inverting terminal is a virtual ground.
Consequently, v
S
appears across capacitor C:
i
S
= C
dv
s
dt
But the capacitor current is also the current through R (since i
in
= 0). Hence,
v
o
= i
F
R = i
S
R = RC
dv
s
dt
6.5.1 Integrating Amplier
The insertion of a capacitor in the feedback path of an op amp results in an output signal
that is a time integral of the input signal. A circuit arrangement for a simple inverting
integrator is given in Fig. 48.
Figure 48: The Integrating Amplier.
The output of the inverting integrator of Fig. 48 actually is the time integral of the
input signal assuming the op amp is ideal as shown below:
If the op amp is ideal, the inverting terminal is a virtual ground, and v
S
appears across
R. Thus, i
S
= v
S
/R. But, with negligible current into the op amp, the current through R
42
must also ow through C. Then
v
o
=
1
C
_
i
F
dt =
1
C
_
i
S
dt =
1
RC
_
v
S
dt
6.5.2 Other Uses of the Op Amp
The operational amplier can also be used to perform other analog mathematical opera-
tions including log calculations.
However, currently, the most important uses of the op amp are in ltering and signal
conditioning applications.
43

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