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Code No: RR410505

Set No. 1

IV B.Tech I Semester Supplimentary Examinations, May/Jun 2009 VLSI SYSTEMS DESIGN ( Common to Computer Science & Engineering, Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Implement the following gates with p-MOS transistors only and explain its working (a) 2 - Input AND gate. (b) 4 - Input NOR gate.

2. Name dierent IC fabrication technologies with suitable examples. 3. Design a stick diagram for CMOS EX-NOR gate. 4. Design a layout for CMOS inverter.

5. Explain the delay calculation procedure for CMOS inverter.

6. Draw the circuit diagram of Depletion-load NMOS SRAM cell and explain its working principle. [16] 7. Explain clearly the global routing phase of the oor planning of the chip with few examples by considering all constraints. [16] 8. Write a register-transfer description of one four-digit timer.

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[8+8] [16] [16] [16] [16]

[16]

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Code No: RR410505

Set No. 2

IV B.Tech I Semester Supplimentary Examinations, May/Jun 2009 VLSI SYSTEMS DESIGN ( Common to Computer Science & Engineering, Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Implement the following gates with CMOS Logic and explain its working (a) 3 - Input NAND gate. (b) Inverter.

2. Explain clearly about each step of typical design abstraction ladder for digital integrated circuits. [16] 3. Design a stick diagram for CMOS logic shown below. Y = (AB + CD)1 4. Design a layout for CMOS 2-input NAND gate.

5. Explain clearly any one of the testing procedure to Test sequential Systems. [16] 6. Draw the circuit diagram of four transistor DRAM cell with storage nodes and explain its working. [16] 7. Clearly explain about block placement and channel denition with respect to oor planning of the chip. [16] 8. Clearly explain about the generic integrated circuit design ow.

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[8+8]

[16] [16]

[16]

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Code No: RR410505

Set No. 3

IV B.Tech I Semester Supplimentary Examinations, May/Jun 2009 VLSI SYSTEMS DESIGN ( Common to Computer Science & Engineering, Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Implement the following gates with p-MOS transistors only and explain its working (a) 2 - Input NAND gate. (b) 3 - Input NOR gate. 2. (a) Why CMOS technology is most suitable for VLSI ICs? (b) Compare between CMOS and bipolar technologies.

3. Explain details about level-1 modeling of MOS transistor. 4. Design a layout for CMOS 3-input NOR gate.

5. Give tests for struck-open fault for each transistor in a two-input static NOR gate. [16] 6. Draw the basic structure of serial-Parallel multiplier and explain its working principle. [16] 7. Explain about pad design procedure to design input and output pads. 8. With suitable example explain any one of the partitioning algorithm

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[8+8]

[6+10] [16] [16]

[16] [16]

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www.jntuworld.com

Code No: RR410505

Set No. 4

IV B.Tech I Semester Supplimentary Examinations, May/Jun 2009 VLSI SYSTEMS DESIGN ( Common to Computer Science & Engineering, Computer Science & Systems Engineering and Electronics & Computer Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. Implement the following gates with p-MOS transistors only and explain its working (a) 2 - Input AND gate. (b) 4 - Input NOR gate.

2. Dene dierent current parameters of Digital IC and explain their signicance.[16] 3. Explain with neat sketches CMOS fabrication using P - well process. 4. Design a layout for CMOS 3-input NOR gate.

5. Explain how wire delay are calculated using El-more - delay model and RC Trees. [16] 6. Discuss clearly about the following system Design principles. (a) Pipelining

(b) Data-paths.

7. Clearly explain how ASM chart is a useful abstraction for register transfer design. [16] 8. With suitable example explain any one of the scheduling algorithm

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[8+8]

[16] [16]

[8+8]

[16]

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