Code No: 37241/37242

R05

Set No - 1

IV B.Tech I Semester Regular Examinations,Nov/Dec 2009 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Control Engineering, Electronics And Instrumentation Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) What is Conditional Signal Assignment Statement? Write its syntax with example. (b) Explain the method of logic-level simulation for CMOS circuits and name such simulators. [8+8] 2. (a) Dierentiate between nMOS inverter pair delay and CMOS inverter pair delay. (b) Derive the expressions for rise and fall time of CMOS inverter delay. (c) What is the total input capacitance value oered by the inverter to achieve symmetrical operation? [6+8+2] 3. (a) Explain how a Booth recoded multiplier reduces the number of adders. (b) Draw circuit diagram of a one transistor with transistor capacitor dynamic RAM and also draw its layout. [8+8] 4. (a) Calculate body factor of threshold for the given parameters NA =3 1016 cm3 , tox = 200A0 , ox =3.9 8.85 1014 F/cm, si =11.7 8.85 1014F/cm, Electron charge =1.6 1019 coulombs.

5. What is an LUT? Explain how an 4 to 1 multiplexer is implemented using LUT? [16] 6. Distinguish between thin lm resistors and thin lm capacitors in all aspects. [16] 7. Briey discuss the limits of scaling. Why scaling is necessary for VLSI circuits? [16] 8. (a) Draw the basic structure of parallel scan and explain how it reduces the long scan chains. (b) Draw the state diagram of TAP Controller and explain how it provides the control signals for test data and instruction register. [8+8]

w w

n j . w

w tu

r o

. ld

m co

(b) Mention the parameters on which the threshold voltage depends.

[8+8]

Code No: 37241/37242

R05

Set No - 2

IV B.Tech I Semester Regular Examinations,Nov/Dec 2009 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Control Engineering, Electronics And Instrumentation Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. (a) Draw the typical architecture of PAL and explain the operation of it. (b) What is CPLD? Draw its basic structure and give its applications.

2. Describe the two commonly used methods for obtaining integrated capacitor.

3. (a) Write a architecture for a 4- bit Counter in both behavioral and structural styles. (b) Explain with example how mixed mode simulator are more for CMOS circuits testing. [8+8] 4. (a) Explain how the cost of chip can eect with the testing levels, (b) Explain how observability is used to test the output of a gate within a larger circuit. (c) How the Iterative Logic Array Testing can be reduced number of tests. [5+6+5] 5. (a) Discuss the rule for n well and VDD and Vss contacts (2m CMOS). (b) Discuss the rule for pad and over glass geometry (2m CMOS). 6. Describe the following briey Cascaded inverters as drivers. [8+4+4] [8+8]

w w

n j . w

w tu

r o

. ld

m co

[8+8] [16]

(b) (a) Super buers. (c) BiCMOS drivers.

7. Develop a model for the read time of a ROM with 2n rows and 2m columns analogous to that of SRAM. Assume the wire capacitance in the ROM array is negligible compared to the gate and diusion capacitance. Assume the ROM cells are laid out such that two cells share a single diusion contact and hence each contributes only C/2 of diusion capacitance. [16] 8. A CMOS process produces gate oxides with a thickness of tox = 100A0 . The FET carriers mobility values are given as n =550cm2 /V-Sec, p =210cm2 /V-Sec. (a) Calculate the oxide capacitance per unit area in units of pF/m2 . (b) Find the process transconductance values for nFET and pFET.Place your answer in units of A/V 2 . [16] 2

Code No: 37241/37242

R05

Set No - 2

w w

n j . w

w tu

r o

. ld

m co

Code No: 37241/37242

R05

Set No - 3

IV B.Tech I Semester Regular Examinations,Nov/Dec 2009 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Control Engineering, Electronics And Instrumentation Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Two NMOS inverters are cascaded to drive a capacity load CL = 14Cg as shown in gure 1. Calculate the pair delay Vin to Vout in terms of for the given data inverter-A. [16] Lpu =12, Wpu =4, Lpd =1, Wpd =8 Inverter-B Lpu =4, Wpu =4, Lpd =2, Wpd =8

2. Draw the stick diagram and a translated mask layout for nMOS inverter circuit. [16] 3. Explain the following: (a) Thermal oxidation technique (b) Kinetics of thermal oxidation. [8+8]

w w

n j . w

w tu

r o

. ld

m co

Figure 1

4. (a) What is the dierence between Flop-Flop and Latch? Write a VHDL program for a latch. (b) Why logic-level simulators are suitable for testing a fast and large CMOS circuits and how to calculate the delay of the gate? [8+8] 5. (a) Draw and explain the schematic of Pseudo-nMOS comparator. (b) Draw and explain the structure of multiplier which computes the partial products in a radix-2 manner. [8+8]

Code No: 37241/37242

R05

Set No - 3
[10+6]

6. (a) What is BIST? Explain in detail. (b) Write the advantages of BIST. 7. (a) Discuss the nFET resistance with relevant equations. (b) Calculate the linearized drain source resistance of an nFET with following parameters. W=8m, L=0.5m, kn =180 A/V2 , Vtn =0.7V and VDD =3.3V. [8+8] 8. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/O structure. (b) Explain any one chip architecture that used the antifuse and give its advantages. [8+8]

w w

n j . w

w tu

r o

. ld

m co

Code No: 37241/37242

R05

Set No - 4

IV B.Tech I Semester Regular Examinations,Nov/Dec 2009 VLSI DESIGN Common to Electronics And Computer Engineering, Electronics And Control Engineering, Electronics And Instrumentation Engineering, Electrical And Electronics Engineering Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks

1. Explain (a) Propagation delay (b) Wiring capacitance.

2. (a) Discuss fabrication dierences between NMOS and CMOS technologies. Which fabrication is preferred and why? (b) Explain the various steps in PMOS fabrication. 3. Write briey about: (a) Channelled gate arrays

(b) Channelless gate arrays with neat sketches.

4. (a) Compare the number of simulation cycles in serial and parallel fault simulation processes.

5. Compare the relative merits of three dierent forms of pull up for an inverter circuits. What is the best choice for realization in (a) nMOS technology [16]

w w

(b) Explain the method of delay fault testing with suitable CMOS circuit. [8+8]

n j . w

w tu

r o

. ld

m co

[8+8]

[8+8]

[8+8]

(b) CMOS technology. 6. (a) Draw the following transistors using lambda based design rules i. NMOS enhancement ii. NMOS depletion iii. PMOS enhancement.

(b) Discuss the design rules for wires (both NMOS and CMOS) using lambda based design rules. [2+2+2+10] 7. (a) What is the importance of operator precedence in VHDL? Is the AND operation takes place before OR operation? (b) What is mean by Hierarchy in VHDL? Write a program for 4 input multiplexer from 2 input multiplexers. [8+8] 6

Code No: 37241/37242

R05

Set No - 4

8. (a) Compare dierent types of CMOS subsystem Adders. (b) Draw the mask layout for 6 transistor static RAM used in ASIC memories. [8+8]

w w

n j . w

w tu

r o

. ld

m co