Rammian

Internal Memory (RAM and ROM) User Guide
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2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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1. About Internal Memory Blocks
This user guide describes the megafunctions that implement the following memory modes:

RAM:1-PortSingle-port RAM RAM:2-PortDual-port RAM ROM:1-PortSingle-port ROM ROM:2-PortDual-port ROM
Altera provides two megafunctions to implement the memory modesthe ALTSYNCRAM and ALTDPRAM megafunctions. The Quartus II software automatically selects one of these megafunctions to implement the memory modes. The selection depends on the target device, memory modes, and features of the RAM and ROM. f This user guide assumes that you are familiar with megafunctions and how to create them. If you are unfamiliar with Altera megafunctions or the MegaWizard Plug-In Manager, refer to the Introduction to Megafunctions User Guide.
Features
The internal memory blocks provide the following features:

Memory Modes Configuration Memory Block Types Write and Read Operations Triggering Port Width Configuration Mixed-width Port Configuration Maximum Block Depth Configuration Clocking Modes and Clock Enable Address Clock Enable Byte Enable Asynchronous Clear Read Enable Read-During-Write Power-Up Conditions and Memory Initialization Error Correction Code
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Chapter 1: About Internal Memory Blocks Device Support
Device Support
Altera internal memory blocks are available for Arria, Cyclone, HardCopy, MAX, and Stratix device series. However, ROM memory blocks are not available for MAX device series.
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2. Parameter Settings
This section describes the parameter settings for the memory modes that you can configure through the parameter editors. You can find the parameter editors under the Memory Compiler category when you launch the MegaWizard Plug-In Manager. 1 Altera recommends that you use the parameter editor to configure and build your RAM and ROM memory blocks to ensure that the combination of your selected options are valid. Table 21 lists the parameter settings for the RAM:1-Port.
Table 21. RAM:1-Port Parameter Settings Option Parameter Settings: Widths/Blk Type/Clks Specifies the width of the q output bus. For more information, refer to Port Width Configuration on page 37. Specifies the number of <X>-bit words. Specifies the memory block type. The types of memory block that are available for selection depends on your target device. For more information refer to Memory Block Types on page 34. Specifies the maximum block depth in words. Auto For more information refer to Maximum Block Depth Configuration on page 39. Specifies the clocking method to use. Single clockA single clock and a clock enable controls all registers of the memory block. Single clock What clocking method would you like to use? or Dual Clock: use separate input and output clocks Dual Clock: use separate input and output clocksAn input and an Single clock output clock controls all registers related to the data input and output to/from the memory block including data, address, byte enables, read enables, and write enables. For more information, refer to Clocking Modes and Clock Enable on page 310. Legal Values Default value Description
How wide should the q output bus be?
How many <X>-bit words of memory?
Auto, M-RAM, M4K, M512, M9K, M10K, M144K, MLAB, M20K, LCs Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192,16384, 32768, 65536
256
What should the memory block type be?
Auto
Set the maximum block depth to
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Chapter 2: Parameter Settings
Table 21. RAM:1-Port Parameter Settings Option Legal Values Default value Description
Parameter Settings: Regs/Clken/Byte Enable/Aclrs Which ports should be registered? The following options are available:

data and wren input ports address input port q output port
On/Off
On
Specifies whether to register the input and output ports.
Create one clock enable signal for each clock signal. Note: All registered ports are controlled by the enable signal(s) Use clock enable for port A input registers Use clock enable for port A output registers More Options Create an addressstall_a input port.
On/Off
Off
Specifies whether to turn on the option to create one clock enable signal for each clock signal. Specifies whether to use clock enable for port A input registers. Specifies whether to use clock enable for port A output registers. Specifies whether to create a addressstall_a input port. You can create this port to act as an extra active low clock enable input for the address registers. For more information, refer to Address Clock Enable on page 312. Specifies whether to create a byte enable for port A. Turn on this option if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written. For more information, refer to Byte Enable on page 313.
On/Off
Off
On/Off
Off
On/Off
Off
Create byte enable for port A
On/Off
Off
What is the width of a byte for byte enables?
MLAB: 5 or 10 Other memory block types: 8 or 9 M10K and M20K: 8, 9, or 10
MLAB: 5 Other memory block types: 8
Specifies the byte width of the byte enable port. The width of the data input port must be divisible by the byte size. For more information, refer to Byte Enable on page 313. Specifies whether to create an asynchronous clear port for the registered data, wren, address, q, and byteena_a ports. For more information, refer to Asynchronous Clear on page 314. Turn on this option for the q port to be affected by the asynchronous clear signal. The disabled ports are not affected by the asynchronous clear signal.
Create an aclr asynchronous clear for the registered ports.
On/Off
Off
More Options
q port
On/Off
Off
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Table 21. RAM:1-Port Parameter Settings Option Legal Values Default value Description Specifies whether to create a read enable signal. For more information, refer to Read Enable on page 315. Specifies the output behavior when read-during-write occurs. New DataNew data is available on the rising edge of the same clock cycle on which it was written. Dont CareThe RAM outputs don't care or unknown values for read-during-write operation. For more information, refer to ReadDuring-Write on page 316. Turn on this option to obtain X on the masked byte. Get xs for write masked bytes instead of old data when byte enable is used On/Off On For M10K and M20K memory block, this option is not available if you specify New Data as the output behavior when RDW occurs. Specifies the initial content of the memory. No, leave it blank Do you want to specify the initial content of the memory? or Yes, use this file for the memory content data No, leave it blank To initialize the memory to zero, select No, leave it blank. To use a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex), select Yes, use this file for the memory content data. For more information, refer to PowerUp Conditions and Memory Initialization on page 318. Allow In-System Memory Content Editor to capture and update content independently of the system clock The Instance ID of this RAM is Specifies whether to allow In-System Memory Content Editor to capture and update content independently of the system clock. Specifies the RAM ID.
Create a rden read enable signal
On/Off
Off
Parameter Settings: Read During Write Option
What should the q output be when reading from a memory location being written to?
New data, Dont Care
New data
Parameter Settings: Mem Init
On/Off
Off
None
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Table 22 lists the parameter settings for the RAM:2-Port.

Table 22. RAM:2-Port Parameter Settings Option Parameter Settings: General With one read port and one write port How will you be using the dual port RAM? or With two read /write ports As a number of words How do you want to specify the memory size? Parameter Settings: Widths/ Blk Type How many <X>-bit words of memory? Use different data widths on different ports When you select With one read port and one write port, the following options are available:

Legal Values
Default values
Description
With one read port and one write port As a number of words
Specifies how you use the dual port RAM.
or As a number of bits
Determines whether to specify the memory size in words or bits.
On/Off
256 Off
Specifies the number of <X>-bit words. Specifies whether to use different data widths on different ports.
How wide should the q_a output bus be? How wide should the data_a input bus be? How wide should the q output bus be? 8
Specifies the width of the input and output ports. For more information, refer to Port Width Configuration on page 37.
When you select With two read/write ports, the following options are available:

How wide should the q_a output bus be? How wide should the q_b output bus be? Specifies the memory block type. The types of memory block that are available for selection depends on your target device. For more information refer to Memory Block Types on page 34. Use default logic cell style Specifies the logic cell implementation options. This option is enabled only when you choose LCs memory type.
Auto, M-RAM, M4K, M512, M9K, M10K, M144K, MLAB, M20K, LCs
Auto
Use default logic cell style How should the memory be implemented? or Use Stratix M512 emulation logic cell style
25
Table 22. RAM:2-Port Parameter Settings Option Legal Values Default values Description Specifies the maximum block depth in words. This option is enabled only when you set the memory block type to Auto. For more information refer to Maximum Block Depth Configuration on page 39. Specifies the clocking method to use. Single clockA single clock and a clock enable controls all registers of the memory block. Dual Clock: use separate input and output clocksAn input and an output clock controls all registers related to the data input and output to/from the memory block including data, address, byte enables, read enables, and write enables. Dual clock: use separate read and write clockA write clock controls the data-input, writeaddress, and write-enable registers while the read clock controls the data-output, readaddress, and read-enable registers. Dual clock: use separate clocks for A and B portsClock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively. For more information, refer to Clocking Modes and Clock Enable on page 310.
Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096
Auto
Parameter Settings: Clks/Rd, Byte En
When you select With one read port and one write port, the following values are available:

Single clock Dual clock: use separate input and output clocks Dual clock: use separate read and write clock
What clocking method would you like to use?

Single clock
Single clock Dual clock: use separate input and output clocks Dual clock: use separate clocks for A and B ports
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Table 22. RAM:2-Port Parameter Settings Option When you select With one read port and one write port, the following option is available: Create a rden read enable signal When you select With two read/write ports, the following option is available: Create a rden_a and rden_b read enable signal Create byte enable for port A Off Legal Values Default values Description Specifies whether to create a read enable signal for port B. For more information, refer to Read Enable on page 315. Specifies whether to create a read enable signal for port A and B. For more information, refer to Read Enable on page 315. Specifies whether to create a byte enable for port A and B. Turn on these options if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written. Off The option to create a byte enable for port B is only available when you select two read/write ports. For more information, refer to Byte Enable on page 313. Specifies whether to enable the ECC feature that corrects single bit errors and detects double errors at the output of the memory. On/Off Off This option is only available in devices that support M144K memory block type. For more information, refer to Error Correction Code on page 319. Specifies whether to enable the ECC feature that corrects single bit errors, double adjacent bit errors, and detects triple adjacent bit errors at the output of the memory. On/Off Off This option is only available in devices that support M20K memory block type. For more information, refer to Error Correction Code on page 319.
Create byte enable for port B
Enable error checking and correcting (ECC) to check and correct single bit errors and detect double errors
Enable error checking and correcting (ECC) to check and correct single bit errors, double adjacent bit errors, and detect triple adjacent bit errors
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Table 22. RAM:2-Port Parameter Settings Option Parameter Settings: Regs/Clkens/Aclrs Which ports should be registered? When you select With one read port and one write port, the following options are available:
Legal Values
Default values
Description
data, wraddress, and wren write input ports raddress and rden read input port Read output port(s) q On/Off On Specifies whether to register the read or write input and output ports.
data_a, wraddress_a, and wren_a write input ports Read output port(s) q_a and q_b When you select With one read port and one write port, the following options are available:

data port wraddress port wren port raddress port q_b port The read and write input ports are turned on by default. You only need to specify whether to register the Q output ports.
More Options
When you select With two read /write ports, the following options are available:

On/Off
On
data_a port data_b port wraddress_a port wraddress_b port wren_a port wren_b port q_a port q_b port
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Table 22. RAM:2-Port Parameter Settings Option Legal Values Default values Description Specifies whether to turn on the option to create one clock enable signal for each clock signal. For more information, refer to Clocking Modes and Clock Enable on page 310.
Create one clock enable signal for each clock signal.
On/Off
Off
When you select With one read port and one write port, the following option is available: Use clock enable for write input registers When you select With two read /write ports, the following options are available:
More Options
On/Off
Off
Use clock enable for port A input registers Use clock enable for port B input registers Use clock enable for port A output registers Use clock enable for port B output register
Clock enable for port B input and output registers are turned on by default. You only need to specify whether to use clock enable for port A input and output registers. For more information, refer to Clocking Modes and Clock Enable on page 310.
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Table 22. RAM:2-Port Parameter Settings Option When you select With one read port and one write port, the following options are available:
Legal Values
Default values
Description
Create an wr_addressstall input port. Create an rd_addressstall input port.
More Options
On/Off
Off
Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers. For more information, refer to Address Clock Enable on page 312.
Create an addressstall_a input port. Create an addressstall_b input port. Specifies whether to create an asynchronous clear port for the registered ports. For more information, refer to Asynchronous Clear on page 314.
On/Off
Off
When you select With one read port and one write port, the following options are available:
rdaddress port q_b port On/Off Off
More Options

Specifies whether the raddress, q_a, and q_b ports are cleared by the aclr port.
q_a port q_b port
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Table 22. RAM:2-Port Parameter Settings Option Parameter Settings: Output 1 Specifies the output behavior when read-during-write occurs. Old memory contents appear The RAM outputs reflect the old data at that address before the write operation proceeds. I do not careThis option functions differently when you turn it on depending on the following memory block type you select:
Legal Values
Default values
Description
When you select With one read port and one write port, the following option is available: How should the q output behave when reading a memory location that is being written from the other port? When you select With two read /write ports, the following option is available: How should the q_a and q_b outputs behave when reading a memory location that is being written from the other port? Old memory contents appear or I do not care
I do not care
When you set the memory block type to Auto, M144K, M512, M4K, M9K, M10K, M20K or any other block RAM, the RAM outputs don't care or unknown values for read-during-write operation without analyzing the timing path. When you set the memory block type to MLAB (for LUTRAM), the RAM outputs dont care or unknown values for read-during-write operation but analyzes the timing path to prevent metastability.
For more information, refer to Read-During-Write on page 316. Turn on this option when you want the RAM to output dont care or unknown values for read-during-write operation without analyzing the timing path. This option is only available for LUTRAM and is enabled when you set memory block type to MLAB.
Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time.
On/Off
Off
211
Table 22. RAM:2-Port Parameter Settings Option Legal Values Default values Description
Parameter Settings: Output 2 (This tab is only available when you select two read/ write ports) What should the q_a output be when reading from a memory location being written to? Specifies the output behavior when read-during-write occurs. New DataNew data is available on the rising edge of the same clock cycle on which it was written. What should the q_b output be when reading from a memory location being written to? New data, Old Data New data Old DataThe RAM outputs reflect the old data at that address before the write operation proceeds. For more information, refer to Read-During-Write on page 316. Get xs for write masked bytes instead of old data when byte enable is used Parameter Settings: Mem Init Specifies the initial content of the memory. To initialize the memory to zero, select No, leave it blank. No, leave it blank Do you want to specify the initial content of the memory? or Yes, use this file for the memory content data No, leave it blank To use a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex), select Yes, use this file for the memory content data. For more information, refer to Power-Up Conditions and Memory Initialization on page 318. On/Off On Turn on this option to obtain X on the masked byte.
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Table 23 lists the parameter settings for the ROM:1-Port.

Table 23. ROM:1-Port Parameter Settings Option Parameter Settings: General Page Specifies the width of the q output bus. How wide should the q output bus be? 8 For more information, refer to Port Width Configuration on page 37. Specifies the number of <X>-bit words. Specifies the memory block type. The types of memory block that are available for selection depends on your target device. For more information, refer to Memory Block Types on page 34. Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096 Specifies the maximum block depth in words. Auto For more information, refer to Maximum Block Depth Configuration on page 39. Specifies the clocking method to use. Single clockA single clock and a clock enable controls all registers of the memory block Single clock or What clocking method would you like to use? Dual clock: use separate input and output clocks Dual clock (Input and Output clock)The input clock Single clock controls the address registers and the output clock controls the data-out registers. There are no write-enable, byte-enable, or data-in registers in ROM mode. For more information, refer to Clocking Modes and Clock Enable on page 310. Parameter Settings: Regs/Clken/Aclrs Which ports should be registered? q output port Create one clock enable signal for each clock signal. Note: All registered ports are controlled by the enable signal(s) On/Off On Specifies whether to register the q output port. Specifies whether to turn on the option to create one clock enable signal for each clock signal. Legal Values Default values Description
256
Auto, M4K, M9K, M144K, M10K, M20K
Auto
On/Off
Off
213
Table 23. ROM:1-Port Parameter Settings Option Use clock enable for port A input registers Use clock enable for port A output registers More Options Create an addressstall_a input port. Legal Values Default values Off Description Specifies whether to use clock enable for port A input registers. Specifies whether to use clock enable for port A output registers. Specifies whether to create a addressstall_a input port. You can create this port to act as an extra active low clock enable input for the address registers. For more information, refer to Address Clock Enable on page 312. Specifies whether to create an asynchronous clear port for the registered ports. For more information, refer to Asynchronous Clear on page 314. Specifies whether the address port should be affected by the aclr port. Specifies whether the q port should be affected by the aclr port. Specifies whether to create a read enable signal. For more information, refer to Read Enable on page 315. Specifies the initial content of the memory. In ROM mode you must specify a memory initialization file (.mif) or a hexadecimal Yes, use (Intel-format) file (.hex). The this file for Yes, use this file for the the memory memory content data option is content data turned on by default. For more information, refer to Power-Up Conditions and Memory Initialization on page 318.
On/Off
On/Off
Off
On/Off
Off
On/Off
Off
address port More Options q port
On/Off
Off
On/Off
Off
Create a rden read enable signal
On/Off
Off
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
Yes, use this file for the memory content data
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Table 23. ROM:1-Port Parameter Settings Option Legal Values Default values Description Specifies whether to allow In-System Memory Content Editor to capture and update content independently of the system clock Specifies the ROM ID.
Allow In-System Memory Content Editor to capture and update content independently of the system clock The Instance ID of this ROM is
On/Off
Off
None
Table 24 lists the parameter settings for the ROM:2-Port.

Table 24. ROM:2-Port Parameter Settings Option Parameter Settings: Widths/Blk Type As a number of words How do you want to specify the memory size? or As a number of bits 32, 64, 128, 256, 512, 1024, 2048, 4096, 8192, 16384, 32768, 65536 As a number of words Determines whether to specify the memory size in words or bits. Specifies the number of <X>-bit words. Specifies whether to use different data widths on different ports. For more information, refer to Mixed-width Port Configuration on page 38. Specifies the width of the q_a and q_b output ports. 8 For more information, refer to Port Width Configuration on page 37. Specifies the memory block type. The types of memory block that are available for selection depends on your target device For more information, refer to Memory Block Types on page 34. Specifies the maximum block depth in words. This option is enabled only when you choose Auto as the memory block type. For more information, refer to Maximum Block Depth Configuration on page 39. Legal Values Default values Description
256
Use different data widths on different ports
On/Off
Off
How wide should the q_a output bus be?
How wide should the q_b output bus be?
Auto, M4K, M9K, M144K, M10K, M20K, MLAB
Auto
Auto, 128, 256, 512, 1024, 2048, 4096
Auto
215
Table 24. ROM:2-Port Parameter Settings Option Parameter Settings: Clks/Rd, Byte En Specifies the clocking method to use. Single clockA single clock and a clock enable controls all registers of the memory block Dual Clock: use separate input and output clocksThe input clock controls the address registers and the output clock controls the data-out registers. There are no write-enable, byte-enable, or data-in registers Single clock in ROM mode. Dual clock: use separate clocks for A and B portsClock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively. For more information, refer to Clocking Modes and Clock Enable on page 310. Create a rden_a and rden_b read enable signals Parameter Settings: Regs/Clkens/Aclrs Read output port(s) q_a and q_b q_a port More Options q_b port Create one clock enable signal for each clock signal. On/Off On On/Off On/Off On On Specifies whether to register the q_a and q_b output ports. Specifies whether to register the q_a output port. Specifies whether to register the q_b output port. Specifies whether to turn on the option to create one clock enable signal for each clock signal. Specifies whether to create read enable signals. For more information, refer to Read Enable on page 315. Legal Values Default values Description
Single clock or Dual Clock: use separate input and output clocks or Dual clock: use separate clocks for A and B ports
What clocking method would you like to use?
Off
On/Off
Off
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Table 24. ROM:2-Port Parameter Settings Option Use clock enable for port A input registers Use clock enable for port A output registers Create an addressstall_a input port. On/Off Off Legal Values On/Off Default values Off Description Specifies whether to use clock enable for port A input registers. Specifies whether to use clock enable for port A output registers. Specifies whether to create addressstall_a and addressstall_b input ports. You can create these ports to act as an extra active low clock enable input for the address registers. For more information, refer to Address Clock Enable on page 312. Specifies whether to create an asynchronous clear port for the registered ports. For more information, refer to Asynchronous Clear on page 314. Specifies whether the q_a port should be cleared by the aclr port. Specifies whether the q_b port should be cleared by the aclr port. Specifies the initial content of the memory. In ROM mode you must specify a memory initialization file (.mif) Yes, use or a hexadecimal (Intel-format) this file for file (.hex). The Yes, use this file the memory for the memory content data content data option is turned on by default. For more information, refer to Power-Up Conditions and Memory Initialization on page 318. PORT_A The initial content file should conform to which ports dimensions? or PORT_B PORT_A Specifies whether the initial content file conforms to port A or port B.
On/Off
Off
More Options
Create an addressstall_b input port.
On/Off
Off
q_a port More Options q_b port Parameter Settings: Mem Init
On/Off
Off
On/Off
Off
Do you want to specify the initial content of the memory?
Yes, use this file for the memory content data
3. Functional Description
This section describes the features and functionality of the internal memory blocks and the ports of the ALTSYNCRAM and ALTDPRAM megafunctions.
Memory Modes Configuration

A memory block contains two address ports (port A and port B) with their respective output data ports, and you can use them for read and write operations depending on the memory mode you choose. The input and output ports shown in the block diagrams refer to the ports of the wrapper that contains the memory megafunction instantiated in it. The ports of the wrapper are mapped to the ports of either the ALTSYNCRAM or the ALTDPRAM megafunction depending on your memory configuration, and the port name reflects the memory features you create. For example, the name of the wrapper port clockena maps to the clock_enable_input_a port of the ALTSYNCRAM megafunction, which relates to the clock enable feature. For more information about the ports of the ALTSYNCRAM and ALTDPRAM megafunctions, refer to ALTSYNCRAM and ALTDPRAM Megafunction Ports on page 320.
Single-port RAM
In a single-port RAM, the read and write operations share the same address at port A, and the data is read from output port A. Figure 31 shows a block diagram of a typical single-port RAM.
Figure 31. Single-port RAM
data[] address[] wren byteena[] addressstall inclock clockena rden aclr q[] outclock
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Chapter 3: Functional Description Memory Modes Configuration
Simple Dual-port RAM

In simple dual-port RAM mode, a dedicated address port is available for each read and write operation (one read port and one write port). A write operation uses write address from port A while read operation uses read address and output from port B. Figure 32 shows the block diagram of a simple dual-port RAM.
Figure 32. Simple Dual-Port RAM
data[] wraddress[] wren byteena[] wr_addressstall wrclock wrclocken aclr
rdaddress[] rden q[] rd_addressstall rdclock rdclocken ecc_status[]
True Dual-port RAM

In true dual-port RAM mode, two address ports are available for read or write operation (two read/write ports). In this mode, you can write to or read from the address of port A or port B, and the data read is shown at the output port with respect to the read address port. Figure 33 shows the block diagrams of a true dual-port RAM.
Figure 33. True Dual-port RAM
data_a[] address_a[] wren_a byteena_a[] addressstall_a clock_a rden_a aclr_a q_a[]
data_b[] address_b[] wren_b byteena_b[] addressstall_b clock_b rden_b aclr_b q_b[]
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Single-port ROM
In single-port ROM, only one address port is available for read operation. Figure 34 shows the block diagram of a single-port ROM.
Figure 34. Single-port ROM
address[] addressstall_a inclock inclocken outclock outclocken q[] outaclr
Dual-port ROM
The dual-port ROM has almost similar functional ports as single-port ROM. The difference is dual-port ROM has an additional address port for read operation. Figure 34 shows the block diagram of a dual-port ROM.
Figure 35. Dual-port ROM
address_a[] address_b[] addressstall_a q_a[] inclock inclocken aclr_a outclock outclocken addressstall_b q_b[] aclr_b
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Chapter 3: Functional Description Memory Block Types
Memory Block Types

Altera provides various sizes of embedded memory blocks for various devices. The parameter editor allows you to implement your memory in the following ways:
Select the type of memory blocks available based on your target device. Refer to Table 31 on page 35. To select the appropriate memory block type for your device, obtain more information about the features of your selected internal memory block in your target device, such as the maximum performance, supported configurations (depth width), byte enable, power-up condition, and the write and read operation triggering. Use logic cells. As compared to internal memory resources, using logic cells to create memory reduces the design performance and utilizes more area. This implementation is normally used when you have used up all the internal memory resources. When logic cells are used, the parameter editor provides you with the following two types of logic cell implementations:
Default logic cell stylethe write operation triggers (internally) on the rising edge of the write clock and have continuous read. This implementation uses less logic cells and is faster, but it is not fully compatible with the Stratix M512 emulation style. Stratix M512 emulation logic cell stylethe write operation triggers (internally) on the falling edge of the write clock and performs read only on the rising edge of the read clock.
Select the Auto option, which allows the software to automatically select the appropriate internal memory resource. When you set the memory block type to Auto, the compiler favors larger block types that can support the memory capacity you require in a single internal memory block. This setting gives the best performance and requires no logic elements (LEs) for glue logic. When you create the memory with specific internal memory blocks, such as M9K, the compiler is still able to emulate wider and deeper memories than the block type supported natively. The compiler spans multiple internal memory blocks (only of the same type) with glue logic added in the LEs as needed. 1 To obtain proper implementation based on the memory configuration you set, allow the Quartus II software to automatically choose the memory type. This gives the compiler the flexibility to place the memory function in any available memory resources based on the functionality and size.
Chapter 3: Functional Description Memory Block Types
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Table 31 lists the options available for you to implement your memory blocks in various device families.
Table 31. Internal Memory Blocks in Altera Devices Memory Block Types Device Family M512 (1) (512 bits) v v M4K (4 Kbits) v v v v M-RAM (2) (512 Kbits) v v v MLAB (3) (4) (640 bits) v v v v v v v M9K (9 Kbits) v v v v v M144K (144 Kbits) v v v M10K (10 Kbits) v v M20K (20 Kbits) v Logic Cell (LC) v v v v v v v v v v v v
Arria GX Arria II GX Arria II GZ Arria V Cyclone, Cyclone II Cyclone III, Cyclone IV Cyclone V HardCopy II HardCopy III, HardCopy IV Max V, Max II, Max 3000A, Max 7000 Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, Stratix IV Stratix V
Notes to Table 38:
(1) M512 blocks are not supported in true dual-port RAM mode, and dual-port ROM mode (2) M-RAM blocks are not supported in ROM mode. (3) For Stratix III devices, MLAB blocks are 320-bit in RAM mode and 640-bit in ROM mode. (4) MLAB blocks are not supported in simple dual-port RAM mode with mixed-width port feature, true dual-port RAM mode, and dual-port ROM mode.
To identify the type of memory block that the software selects to create your memory, refer to the fitter report after compilation.
f For more information about internal memory blocks and the specifications, refer to the memory related chapters in your target device handbook.
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Chapter 3: Functional Description Write and Read Operations Triggering
Write and Read Operations Triggering

The internal memory blocks vary slightly in its supported features and behaviors. One important variation is the difference in the write and read operations triggering. Table 32 lists the write and read operations triggering for various internal memory blocks.
Table 32. Write and Read Operations Triggering for internal Memory Blocks internal Memory Blocks M10K M20K M144K M9K MLAB M-RAM M4K M512
Notes to Table 32:
(1) Write operation triggering is not applicable to ROMs. (2) MLAB supports continuos reads. For example, when you write a data at the write clock rising edge and after the write operation is complete, you see the written data at the output port without the need for a read clock rising edge.
Write Operation
(1)
Read Operation Rising clock edges Rising clock edges Rising clock edges Rising clock edges Rising clock edges
(2)
Rising clock edges Rising clock edges Rising clock edges Rising clock edges Falling clock edges Rising clock edges (in Arria V, Cyclone V, and Stratix V devices only) Rising clock edges Falling clock edges Falling clock edges
Rising clock edges Rising clock edges Rising clock edges
It is important that you understand the write operation triggering to avoid potential write contentions that can result in unknown data storage at that location.
Chapter 3: Functional Description Port Width Configuration
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Figure 36 and Figure 37 show the valid write operation that triggers at the rising and falling clock edge, respectively.
Figure 36. Valid Write Operation that Triggers at Rising Clock Edges Figure 37. Valid Write Operation that Triggers at Falling Clock Edge
clock_a
clock_a
address_a
01
address_a
01
wren_a
wren_a
data_a
05 twc
06 Valid Write
data_a
05 twc
06 Valid Write Actual Write
clock_b
clock_b
address_b
01
address_b
01
wren_b
wren_b
data_b
02
03
04
05
data_b
02
03
04
05
Figure 36 assumes that twc is the maximum write cycle time interval. Write operation of data 03 through port B does not meet the criteria and causes write contention with the write operation at port A, which result in unknown data at address 01. The write operation at the next rising edge is valid because it meets the criteria and data 04 replaces the unknown data. Figure 37 assumes that twc is the maximum write cycle time interval. Write operation of data 04 through port B does not meet the criteria and therefore causes write contention with the write operation at port A that result in unknown data at address 01. The next data (05) is latched at the next rising clock edge that meets the criteria and is written into the memory block at the falling clock edge. 1 Data and addresses are latched at the rising edge of the write clock regardless of the different write operation triggering.
Port Width Configuration

The port width configuration is defined by the following equation: Memory depth (number of words) Width of the data input bus f For more information about the supported port width configuration for various internal memory blocks, refer to the memory related chapters in your target device handbook.
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Chapter 3: Functional Description Mixed-width Port Configuration
If your port width configuration (either the depth or the width) is more than the amount an internal memory block can support, additional memory blocks (of the same type) are used. For example, if you configure your M9K as 512 36, which exceeds the supported port width of 512 18, two M9Ks are used to implement your RAM. In addition to the supported configuration provided, you can set the memory depth to a non-power of two, but the actual memory depth allocated can vary. The variation depends on the type of resource implemented. If the memory is implemented in dedicated memory blocks, setting a non-power of two for the memory depth reflects the actual memory depth. If the memory is implemented in logic cells (and not using Stratix M512 emulation logic cell style that can be set through the parameter editor), setting a non-power of two for the memory depth does not reflect the actual memory depth. In this case, you write to or read from up to 2 address_width memory locations even though the memory depth you set is less than 2 address_width . For example, if you set the memory depth to 3, and the RAM is implemented using logic cells, your actual memory depth is 4. When you implement your memory using dedicated memory blocks, you can check the actual memory depth by referring to the fitter report.
Mixed-width Port Configuration

Only dual-port RAM and dual-port ROM support mixed-width port configuration for all memory block types except when they are implemented with LEs. The support for mixed-width port depends on the width ratio between port A and port B. In addition, the supporting ratio varies for various memory modes, memory blocks, and target devices. 1 MLABs do not have native support for mixed-width operation, thus the option to select MLABs is disabled in the parameter editor. However, the Quartus II software can implement mixed-width memories in MLABs by using more than one MLAB. Therefore, if you select AUTO for your memory block type, it is possible to implement mixed-width port memory using multiple MLABs.
f For more information about width ratio that supports mixed-width port, refer to your relevant device handbook. Memory depth of 1 word is not supported in simple dual-port and true dual-port RAMs with mixed-width port. The parameter editor prompts an error message when the memory depth is less than 2 words. For example, if the width for port A is 4 bits and the width for port B is 8 bits, the smallest depth supported by the RAM is 4 words. This configuration results in memory size of 16 bits (4 4) and can be represented by memory depth of 2 words for port B. If you set the memory depth to 2 words that results in memory size of 8 bits (2 4), it can only be represented by memory depth of 1 word for port B, and therefore the width of the port is not supported.
Chapter 3: Functional Description Maximum Block Depth Configuration
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Maximum Block Depth Configuration

You can limit the maximum block depth of the dedicated memory block you use. The memory block can be sliced to your desired maximum block depth. For example, the capacity of an M9K block is 9,216 bits, and the default memory depth is 8K, in which each address is capable of storing 1 bit (8K 1). If you set the maximum block depth to 512, the M9K block is sliced to a depth of 512 and each address is capable of storing up to 18 bits (512 18). You can use this option to save power usage in your devices. However, this parameter might increase the number of LEs and affects the design performance. Table 33 lists the estimated dynamic power usage for different slice type that is applied to an 8K 36 (M9K RAM block) design in a Stratix III EP3SE50 device.
Table 33. Power Usage Setting for 8K 36 (M9K) Design of a Stratix III Device M9K Slice Type 8K 1 (default setting) 4K 2 2K 4 1K 9 512 18 256 36 Dynamic Power (mW) 51.49 20.28 (39%) 10.80 (21%) 6.08 (12%) 4.51 (9%) 6.36 (12%) ALUT Usage 0 38 44 125 212 467 M9Ks 36 36 36 32 32 32
When the RAM is sliced shallower, the dynamic power usage decreases. However, for a RAM block with a depth of 256, the power used by the extra LEs starts to outweigh the power gain achieved by shallower slices. You can also use this option to reduce the total number of memory blocks used (but at the expense of LEs). From Table 33, the 8K 36 RAM uses 36 M9K RAM blocks with a default slicing of 8K 1. By setting the maximum block depth to 1K, the 8K 36 RAM can fit into 32 M9K blocks. The maximum block depth must be in a power of two, and the valid values vary among different dedicated memory blocks.
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Chapter 3: Functional Description Clocking Modes and Clock Enable
Table 34 lists the valid range of maximum block depth for various internal memory blocks.
Table 34. Valid Range of Maximum Block Depth for Various internal Memory Blocks internal Memory Blocks M10K M20K M144K M9K MLAB M512 M4K M-RAM
Notes to Table 34:
(1) The maximum block depth must be in a power of two. (2) The maximum block depth setting (64) for MLAB is not available for Arria V, Cyclone V, and Stratix III devices.
Valid Range 2568K 51216K 2K16K 2568K 3264

(2)
(1)
32512 1284K 4K64K
The parameter editor prompts an error message if you enter an invalid value for the maximum block depth. Altera recommends that you set the value to Auto if you are not sure of the appropriate maximum block depth to set or the setting is not important for your design. This setting enables the compiler to select the maximum block depth with the appropriate port width configuration for the type of internal memory block of your memory.
Clocking Modes and Clock Enable

Altera internal memory supports various types of clocking modes depending on the memory mode you select. Table 35 lists the internal memory clocking modes.
Table 35. Clocking Modes Clocking Modes Single clock Read/Write Input/Output Independent Single-port RAM Simple Dual-port RAM v v v v v True Dual-port RAM v v v Single-port ROM v v Dual-port ROM v v v
Asynchronous clock mode is only supported in MAX series of devices, and not supported in Stratix and newer devices. However, Stratix III and newer devices support asynchronous read memory for simple dual-port RAM mode if you choose MLAB memory block with unregistered rdaddress port. The clock enable signals are not supported for write address, byte enable, and data input registers on Arria V, Cyclone V, and Stratix V MLAB blocks.
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Single Clock Mode

In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory block.
Read/Write Clock Mode

In the read/write clock mode, a separate clock is available for each read and write port. A read clock controls the data-output, read-address, and read-enable registers. A write clock controls the data-input, write-address, write-enable, and byte enable registers.
Input/Output Clock Mode

In input/output clock mode, a separate clock is available for each input and output port. An input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.
Independent Clock Mode

In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side. 1 You can create independent clock enable for different input and output registers to control the shut down of a particular register for power saving purposes. From the parameter editor, click More Options (beside the clock enable option) to set the available independent clock enable that you prefer.
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Chapter 3: Functional Description Address Clock Enable
Address Clock Enable

The address clock enable (addressstall) port is an active high asynchronous control signal that holds the previous address value for as long as the signal is enabled. When the memory blocks are configured in dual-port RAMs or dual-port ROMs, you can create independent address clock enable for each address port. To configure the address clock enable feature, click More Options located beside the clock enable option on the parameter editor. Turn on Create an addressstall_a input port or Create an addressstall_b input port to create an addressstall port. Figure 38 and Figure 39 show the results of address clock enable signal during the read and write operations, respectively.
Figure 38. Address Clock Enable During Read Operation
inclock rdaddress rden addressstall latched address (inside memory) an a0 doutn dout0 dout0 dout1 a1 dout1 dout4 a4 a5 dout4 dout5 a0 a1 a2 a3 a4 a5 a6
q (synch) doutn-1 q (asynch) doutn
Figure 39. Address Clock Enable During Write Operation

inclock wraddress data wren addressstall latched address (inside memory) contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 XX XX an XX XX 01 02 XX XX 04 05 a0 a1 00 03 a4 a5 a0 00 a1 01 a2 02 a3 03 a4 04 a5 05 a6 06
Chapter 3: Functional Description Byte Enable
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Byte Enable
All internal memory blocks that are implemented as RAMs support byte enables that mask the input data so that only specific bytes, nibbles, or bits of data are written. The unwritten bytes or bits retain the previously written value. The least significant bit (LSB) of the byte-enable port corresponds to the least significant byte of the data bus. For example, if you use a RAM block in x18 mode and the byte-enable port is 01, data [8..0] is enabled and data [17..9] is disabled. Similarly, if the byte-enable port is 11, both data bytes are enabled. You can specifically define and set the size of a byte for the byte-enable port. The valid values are 5, 8, 9, and 10, depending on the type of internal memory blocks. The values of 5 and 10 are only supported by MLAB. To create a byte-enable port, the width of the data input port must be a multiple of the size of a byte for the byte-enable port. For example, if you use an MLAB memory block, the byte enable is only supported if your data bits are multiples of 5, 8, 9 or 10, that is 10, 15, 16, 18, 20, 24, 25, 27, 30, and so on. If the width of the data input port is 10, you can only define the size of a byte as 5. In this case, you get a 2-bit byte-enable port, each bit controls 5 bits of data input written. If the width of the data input port is 20, then you can define the size of a byte as either 5 or 10. If you define 5 bits of input data as a byte, you get a 4-bit byte-enable port, each bit controls 5 bits of data input written. If you define 10 bits of input data as a byte, you get a 2-bit byte-enable port, each bit controls 10 bits of data input written. Figure 310 shows the results of the byte enable on the data that is written into the memory, and the data that is read from the memory.
Figure 310. Byte Enable Functional Waveform
inclock wren address an a0 a1 a2 a0 a1 a2
data
XXXX
ABCD
XXXX
byteena
XX
10
01
11
XX
contents at a0
FFFF
ABFF
contents at a1
FFFF
FFCD
contents at a2
FFFF
ABCD
don't care: q (asynch)
doutn doutn
ABXX ABFF
XXCD FFCD
ABCD ABCD
ABFF ABFF
FFCD FFCD
ABCD ABCD
current data: q (asynch)
When a byte-enable bit is deasserted during a write cycle, the corresponding masked byte of the q output can appear as a Don't Care value or the current data at that location. This selection is only available if you set the read-during-write output behavior to New Data. f For more information about the masked byte and the q output, refer to Read-DuringWrite on page 316.
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Chapter 3: Functional Description Asynchronous Clear
Asynchronous Clear
The internal memory blocks in the Arria II GX, Arria II GZ, Cyclone III, HardCopy III, HardCopy IV, Stratix III, Stratix IV, Stratix V, and newer device families support the asynchronous clear feature used on the output latches and output registers. Therefore, if your RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear. The asynchronous clear feature allows you to clear the outputs even if the q output port is not registered. However, this feature is not supported in MLAB memory blocks. The outputs stay cleared until the next clock. However, in Arria V, Cyclone V, and Stratix V devices, the outputs stay cleared until the next read. 1 You cannot use the asynchronous clear port to clear the contents of the internal memory. Use the asynchronous clear port to clear the contents of the input and output register stages only. Table 36 lists the asynchronous clear effects on the input ports for various devices in various memory settings.
Table 36. Asynchronous Clear Effects on the Input Ports for Various Devices in Various Memory Settings Arria GX, Cyclone II, HardCopy II, Stratix II, and Stratix II GX Arria II GX, Arria II GZ, Arria V, Cyclone III, Cyclone V, HardCopy III, HardCopy IV, Stratix III, Stratix IV, Stratix V, and newer devices
Memory Mode
Cyclone, Stratix, and Stratix GX
All registered input ports can be affected except for the following ports and conditions: Single-port RAM

wren port for M512 data/wren/address ports for MRAM (byteena port can be affected) LCs are implemented
(1)
All registered input ports are not affected. (1)
All registered input ports are not affected. (1)
Single dual-port RAM and True dual-port RAM Single-port ROM Dual-port ROM
Note to Table 36:
All input registered ports can be affected except for MRAM. Registered address input port can be affected. Registered address input port can be affected.
All registered input ports are not affected. All registered input ports are not affected. All registered input ports are not affected.
Only registered input read address port can be affected. Registered input address port can be affected. All registered input ports are not affected.
(1) When LCs are implemented in this memory mode, registered output port is not affected.
During a read operation, clearing the input read address asynchronously corrupts the memory contents. The same effect applies to a write operation if the write address is cleared.
Chapter 3: Functional Description Read Enable
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Beginning from Arria V, Cyclone V, and Stratix V devices onwards, an output clock signal is needed to successfully recover the output latch from an asynchronous clear signal. This implies that in a single clock mode true dual-port RAM, setting clock enabled on the registered output may affect the recovery of the unregistered output because they share the same output clock signal. To avoid this, provide an output clock signal (with clock enabled) to the output latch to deassert an asynchronous clear signal from the output latch.
Read Enable
Support for the read enable feature depends on the target device, memory block type, and the memory mode you select. Table 37 lists the memory configurations for various device families that support the read enable feature.
Table 37. Read-Enable Support in Various Device Families Arria II GX, Cyclone III, HardCopy III, Stratix III and newer devices M9K, M144K, M10K, M20K Single-port RAM Simple dualport RAM True dualport RAM Tri-port RAM Single-port ROM Dual-port ROM v v v v v v MLAB Other Cyclone and Stratix Devices
Memory Modes
M512, M4K v v
M-RAM
If you create the read-enable port and perform a write operation (with the read enable port deasserted), the data output port retains the previous values that are held during the most recent active read enable. If you activate the read enable during a write operation, or if you do not create a read-enable signal, the output port shows the new data being written, the old data at that address, or a Don't Care value when readduring-write occurs at the same address location. f For more information about the read-during-write output behavior, refer to the Read-During-Write on page 316.
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Chapter 3: Functional Description Read-During-Write
Read-During-Write
The read-during-write (RDW) occurs when a read and a write target the same memory location at the same time. The RDW operates in the following two ways:

Same-port Mixed-port
Same-Port RDW
The same-port RDW occurs when the input and output of the same port access the same address location with the same clock. The same-port RDW has the following output choices:
New DataNew data is available on the rising edge of the same clock cycle on which it was written. Old DataThe RAM outputs reflect the old data at that address before the write operation proceeds. 1 Old Data is not supported for M10K and M20K memory blocks in single-port RAM and true dual-port RAM.
Don't CareThe RAM outputs don't care values for the RDW operation.
Mixed-Port RDW
The mixed-port RDW occurs when one port reads and another port writes to the same address location with the same clock. The mixed-port RDW has the following output choices:
Old DataThe RAM outputs reflect the old data at that address before the write operation proceeds. 1 Old Data is supported for single clock configuration only.
Don't CareThe RAM outputs don't care or unknown values for RDW operation without analyzing the timing path. 1 For LUTRAM, this option functions differently whereby when you enable this option, the RAM outputs dont care or unknown values for RDW operation but analyzes the timing path to prevent metastability. Therefore, if you want the RAM to output dont care values without analyzing the timing path, you have to turn on the Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time option.
Chapter 3: Functional Description Read-During-Write
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Selecting RDW Output Choices for Various Memory Blocks

The available output choices for the RDW behavior vary, depending on the types of RDW and internal memory block in use. Table 38 lists the available output choices for the same-port, and mixed-port RDW for various internal memory blocks.
Table 38. Output Choices for the Same-Port and Mixed-Port Read-During-Write Memory Block Types M512 M4K M-RAM MLAB M9K M144K M10K M20K LCs
Notes to Table 38:
(1) Single-port RAM only supports same-port RDW, and the clocking mode must be either single clock mode, or input/output clock mode. (2) Simple dual-port RAM only supports mixed-port RDW, and the clocking mode must be either single clock mode, or input/output clock mode. (3) The clocking mode must be either single clock mode, input/output clock mode, or independent clock mode. (4) The clocking mode must be either single clock mode, or input/output clock mode. (5) There is no option page available from the parameter editor in this mode. By default, the new data flows through to the output. (6) There are two types of new data behavior for same-port RDW that you can choose from the parameter editor. When byte enable is applied, you can choose to read old data, or X on the masked byte. The respective parameter values are:
NEW_DATA_WITH_NBE_READ NEW_DATA_NO_NBE_READ
Single-port RAM Same port RDW
(1)
Simple dual-port RAM

(2)
True dual-port RAM Same port RDW

(3)
Mixed-port RDW Old Data
Mixed-port RDW NA Old Data
(4)
No parameter editor (5)
Dont Care Dont Care
No parameter editor
(5)
Dont Care Dont Care
Dont Care Dont Care New Data (6) Old Data
Old Data Dont Care Old Data Dont Care New Data (6) Dont Care Old Data Dont Care Old Data Dont Care
NA MLAB is not supported in true dual-port RAM New Data

(6)
Old Data Dont Care
Old Data
No parameter editor (5)
NA
for old data on masked byte.
for x on masked byte.
The RDW old data mode is not supported when the Error Correction Code (ECC) is engaged. If you are not concerned about the output when RDW occurs and would like to improve performance, you can select Don't Care. Selecting Don't Care increases the flexibility in the type of memory block being used, provided you do not assign block type when you instantiate the memory block.
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Chapter 3: Functional Description Power-Up Conditions and Memory Initialization
Power-Up Conditions and Memory Initialization

Power-up conditions depend on the type of internal memory blocks in use and whether or not the output port is registered. Table 39 lists the power-up conditions in the various types of internal memory blocks.
Table 39. Power-Up Conditions for Various internal Memory Blocks internal Memory Blocks M512 M4K M-RAM MLAB M9K M144K M10K M20K Power-Up Conditions Outputs cleared Outputs cleared Outputs cleared if registered, otherwise unknown Outputs cleared if registered, otherwise reads memory contents Outputs cleared Outputs cleared Outputs cleared Outputs cleared
The outputs of M512, M4K, M9K, M144K, M10K, and M20K blocks always power-up to zero, regardless of whether the output registers are used or bypassed. Even if a memory initialization file is used to pre-load the contents of the memory block, the output is still cleared. MLAB and M-RAM blocks power-up to zero only if output registers are used. If output registers are not used, MLAB blocks power-up to read the memory contents while M-RAM blocks power-up to an unknown state. 1 When the memory block type is set to Auto in the parameter editor, the compiler is free to choose any memory block type, in which the power-up value depends on the chosen memory block type. To identify the type of memory block the software selects to implement your memory, refer to the fitter report after compilation. All memory blocks (excluding M-RAM) support memory initialization via the Memory Initialization File (.mif) or Hexadecimal (Intel-format) file (.hex). You can include the files using the parameter editor when you configure and build your RAM. For RAM, besides using the .mif file or the .hex file, you can initialize the memory to zero or X. To initialize the memory to zero, select No, leave it blank. To initialize the content to X, turn on Initialize memory content data to XX..X on power-up in simulation. Turning on this option does not change the power-up behavior of the RAM but initializes the content to X. For example, if your target memory block is M4K, the output is cleared during power-up (based on Table 39 on page 318). The content that is initialized to X is shown only when you perform the read operation. 1 The Quartus II software searches for the altsyncram init_file in the project directory, the project db directory, user libraries, and the current source file location.
Chapter 3: Functional Description Error Correction Code
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Error Correction Code

Error correction code (ECC) allows you to detect and correct data errors at the output of the memory. The Stratix III and Stratix IV M144K memory blocks have built-in ECC support of up to x64-wide simple dual-port mode while the Stratix V M20K memory blocks have built-in ECC support of x32-wide simple dual-port mode. The ECC in Stratix III and IV can perform single-error-correction double-error detection (SECDED), in which it can detect and fix a single-bit error or detect two-bit errors (without fixing). The Stratix V ECC feature can perform single error correction, double adjacent error correction, and triple adjacent error detection, in which it can detect and fix a single bit error event or a double adjacent error event, or detect three adjacent errors without fixing the errors. However, the Stratix V ECC feature cannot detect four or more errors. The ECC feature is not supported in the following conditions:

mixed-width port feature is used byte-enable feature is engaged
The Mixed-port RDW for old data mode is not supported when the ECC feature is engaged. The result for RDW is Don't Care. The M144K ECC status is communicated via a three-bit status flag eccstatus[2..0]. while the M20K ECC status is communicated with a two-bit ECC status flag eccstatus[1..0] where eccstatus[1] corresponds to the signal e (error) and eccstatus[0] corresponds to the signal ue (uncorrectable error). Table 310 lists the truth table for the ECC status flags.
Table 310. Truth Table for ECC Status Flags M144K Status eccstatus[2..0] No error Single error and fixed Double error and no fix 000 011 101 001 Illegal 010 100 11X A correctable error occurred and the error has been corrected at the outputs; however, the memory array has not been updated. An uncorrectable error occurred and uncorrectable data appears at the output. 0 1 M20K eccstatus[1..0] eccstatus[1] e 0 eccstatus[0] ue 0
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Chapter 3: Functional Description ALTSYNCRAM and ALTDPRAM Megafunction Ports
f You can also use the ALTECC_ENCODER and the ALTECC_DECODER megafunctions to implement the ECC external to your memory blocks. For more information, refer to the Integer Arithmetic Megafunctions User Guide.
ALTSYNCRAM and ALTDPRAM Megafunction Ports

Table 311 lists the input and output ports for the ALTSYNCRAM megafunction.
Table 311. ALTSYNCRAM Megafunction Input and Output Ports Description Port Name Type Required Description Data input to port A of the memory. The data_a port is required if the operation_mode is set to any of the following values: data_a Input Optional

SINGLE_PORT DUAL_PORT BIDIR_DUAL_PORT
address_a
Input
Yes
Address input to port A of the memory. The address_a port is required for all operation modes. Write enable input for address_a port. The wren_a port is required if the operation_mode is set to any of the following values:
wren_a
Input
Optional
SINGLE_PORT DUAL_PORT BIDIR_DUAL_PORT
Read enable input for address_a port. rden_a Input Optional The rden_a port is supported depending on your selected memory mode and memory block. For more information about the read enable feature, refer to Read Enable on page 315. Byte enable input to mask the data_a port so that only specific bytes, nibbles, or bits of the data are written. The byteena_a port is not supported in the following conditions: byteena_a Input Optional

If implement_in_les parameter is set to ON If operation_mode parameter is set to ROM
For more information about byte enable feature and the criterion that you must follow to use the feature correctly, refer to Byte Enable on page 313. Address clock enable input to hold the previous address of address_a port for as long as the addressstall_a port is high. For more information about address clock enable feature, refer to Address Clock Enable on page 312.
addressstall_a
Input
Optional
321
Table 311. ALTSYNCRAM Megafunction Input and Output Ports Description Port Name Type Required Description Data output from port A of the memory. The q_a port is required if the operation_mode parameter is set to any of the following values: q_a Output Yes

SINGLE_PORT BIDIR_DUAL_PORT ROM
The width of q_a port must be equal to the width of data_a port. Data input to port B of the memory. data_b Input Optional The data_b port is required if the operation_mode parameter is set to BIDIR_DUAL_PORT. Address input to port B of the memory. address_b Input Optional The address_b port is required if the operation_mode parameter is set to the following values:

DUAL_PORT BIDIR_DUAL_PORT
Write enable input for address_b port. wren_b Input Yes The wren_b port is required if operation_mode is set to BIDIR_DUAL_PORT. Read enable input for address_b port. rden_b Input Optional The rden_b port is supported depending on your selected memory mode and memory block For more information about the read enable feature, refer to Read Enable on page 315. Byte enable input to mask the data_b port so that only specific bytes, nibbles, or bits of the data are written. The byteena_b port is not supported in the following conditions:
If implement_in_les parameter is set to ON If operation_mode parameter is set to SINGLE_PORT, DUAL_PORT, or ROM
byteena_b
Input
Optional
For more information about byte enable feature and the criterion that you must follow to use the feature correctly, refer to Byte Enable on page 313. Address clock enable input to hold the previous address of address_b port for as long as the addressstall_b port is high. For more information about address clock enable feature, refer to Address Clock Enable on page 312. Data output from port B of the memory. The q_b port is required if the operation_mode is set to the following values: q_b Output Yes

addressstall_b
Input
Optional
DUAL_PORT BIDIR_DUAL_PORT
The width of q_b port must be equal to the width of data_b port.
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Table 311. ALTSYNCRAM Megafunction Input and Output Ports Description Port Name Type Required Description The following table describes which of your memory clock must be connected to the clock0 port, and port synchronization in different clocking modes: Clocking Mode Single clock
Descriptions Connect your single source clock to clock0 port. All registered ports are synchronized by the same source clock. Connect your write clock to clock0 port. All registered ports related to write operation, such as data_a port, address_a port, wren_a port, and byteena_a port are synchronized by the write clock. Connect your input clock to clock0 port. All registered input ports are synchronized by the input clock. Connect your port A clock to clock0 port. All registered input and output ports of port A are synchronized by the port A clock
Read/Write
clock0
Input
Yes
Input Output
Independent clock
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Table 311. ALTSYNCRAM Megafunction Input and Output Ports Description Port Name Type Required Description The following table describes which of your memory clock must be connected to the clock1 port, and port synchronization in different clocking modes: Clocking Mode Single clock
Descriptions Not applicable. All registered ports are synchronized by clock0 port. Connect your read clock to clock1 port. All registered ports related to read operation, such as address_b port, rden_b port, and q_b port are synchronized by the read clock. Connect your output clock to clock1 port. All the registered output ports are synchronized by the output clock. Connect your port B clock to clock1 port. All registered input and output ports of port B are synchronized by the port B clock.
Read/Write Input Optional
clock1
Input Output
Independent clock
clocken0 clocken1 clocken2 clocken3
Input Input Input Input
Optional Optional Optional Optional
Clock enable input for clock0 port. Clock enable input for clock1 port. Clock enable input for clock0 port. Clock enable input for clock1 port.
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Table 311. ALTSYNCRAM Megafunction Input and Output Ports Description Port Name Type Required Description Asynchronously clear the registered input and output ports. The aclr0 port affects the registered ports that are clocked by clock0 clock. while the aclr1 port affects the registered ports that are clocked by clock1 clock. aclr0 aclr1 Input Optional The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as outdata_aclr_a,address_aclr_a, and so on. For more information about the asynchronous clear parameters, refer to Asynchronous Clear on page 314. A 3-bit wide error correction status port. Indicate whether the data that is read from the memory has an error in single-bit with correction, fatal error with no correction, or no error bit occurs. In Stratix V devices, the M20K ECC status is communicated with two-bit wide error correction status port. The M20K ECC detects and fixes a single bit error event or a double adjacent error event, or detects three adjacent errors without fixing the errors. eccstatus Output Optional The eccstatus port is supported if all the following conditions are met:

operation_mode parameter is set to DUAL_PORT ram_block_type parameter is set to M144K or M20K width_a and width_b parameter have the same value Byte enable is not used
For more information about the ECC features, restrictions, and the output status definitions, refer to Error Correction Code on page 319.
Table 312 lists the input and output ports for the ALTDPRAM megafunction.
Table 312. ALTDPRAM Megafunction Input and Output Ports Description Port Name data Type Input Required Data input to the memory. Yes The data port is required and the width must be equal to the width of the q port. Write address input to the memory. wraddress Input Yes The wraddress port is required and must be equal to the width of the raddress port. Write enable input for wraddress port. The wren port is required. Read address input to the memory. raddress Input Yes The rdaddress port is required and must be equal to the width of wraddress port. Description
wren
Input
Yes
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Table 312. ALTDPRAM Megafunction Input and Output Ports Description Port Name Type Required Description Read enable input for rdaddress port. The rden port is supported when the use_eab parameter is set to OFF. The rden port is not supported when the ram_block_type parameter is set to MLAB. Instantiate the ALTSYNCRAM megafunction if you want to use read enable feature with other memory blocks. Byte enable input to mask the data port so that only specific bytes, nibbles, or bits of data are written. The byteena port is not supported when use_eab parameter is set to OFF. It is supported in Arria II GX, Stratix III, Cyclone III, and newer devices with the ram_block_type parameter set to MLAB. For more information about byte enable feature and the criterion that you must follow to use the feature correctly, refer to Byte Enable on page 313. Write address clock enable input to hold the previous write address of wraddress port for as long as the wraddressstall port is high. For more information about address clock enable feature, refer to Address Clock Enable on page 312. Read address clock enable input to hold the previous read address of rdaddress port for as long as the wraddressstall port is high. rdaddressstall Input Optional The rdaddressstall port is only supported in Stratix II, Cyclone II, Arria GX, and newer devices except when the rdaddress_reg parameter is set to UNREGISTERED. For more information about address clock enable feature, refer to Address Clock Enable on page 312. q Output Yes Data output from the memory. The q port is required, and must be equal to the width data port.
rden
Input
Optional
byteena
Input
Optional
wraddressstall
Input
Optional
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Table 312. ALTDPRAM Megafunction Input and Output Ports Description Port Name Type Required Description The following table describes which of your memory clock must be connected to the inclock port, and port synchronization in different clocking modes: Clocking Mode Single clock
Descriptions Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock. Connect your write clock to inclock port. All registered ports related to write operation, such as data port, wraddress port, wren port, and byteena port are synchronized by the write clock. Connect your input clock to inclock port. All registered input ports are synchronized by the input clock.
inclock
Input
Yes
Read/Write
Input/Output
The following table describes which of your memory clock must be connected to the outclock port, and port synchronization in different clocking modes: Clocking Mode Single clock
Descriptions Connect your single source clock to inclock port and outclock port. All registered ports are synchronized by the same source clock. Connect your read clock to outclock port. All registered ports related to read operation, such as rdaddress port, rdren port, and q port are synchronized by the read clock. Connect your output clock to outclock port. The registered q port is synchronized by the output clock.
outclock
Input
Yes Read/Write
Input/Output
inclocken
Input
Optional
Clock enable input for inclock port.
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Table 312. ALTDPRAM Megafunction Input and Output Ports Description Port Name outclocken Type Input Required Optional Description Clock enable input for outclock port. Asynchronously clear the registered input and output ports. The asynchronous clear effect on the registered ports can be controlled through their corresponding asynchronous clear parameter, such as indata_aclr, wraddress_aclr, and so on. For more information about the asynchronous clear parameters, refer to Asynchronous Clear on page 314.
aclr
Input
Optional
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4. Design Example
This section describes the design example provided with this user guide. You can download design examples from the following locations:
On the Quartus II Development Software Literature page, in the Using Megafunctions section under Memory Compiler On the Literature: User Guides webpage, with this user guide
The following design files can be found in Internal_Memory_DesignExample.zip:

ecc_encoder.v ecc_decoder.v true_dp_ram.v top_dpram.v true_dp_ram.vt true_dp.do true_dp.qar (Quartus II design file)
Simulate the designs using the ModelSim-Altera software to generate a waveform display of the device behavior. For more information about the ModelSim-Altera software, refer to the ModelSim-Altera Software Support page on the Altera website. The support page includes links to such topics as installation, usage, and troubleshooting.
External ECC Implementation with True-Dual-Port RAM

The ECC features are only supported internally in simple dual-port RAM by Stratix III and Stratix IV devices when the M144K is implemented or by Stratix V when the M20K is implemented. Therefore, this design example describes how ECC features can be implemented in other RAM modes, regardless of the type of device memory block you use. It also demonstrates the features of the same-port and mixedport read-during-write behaviors. This design example uses a true dual-port RAM and illustrates how the ECC feature can be implemented external to the RAM. The ALTECC_ENCODER and ALTECC_DECODER megafunctions are required as the ALTECC_ENCODER megafunction encodes the data input before writing the data into the RAM, while the ALTECC_DECODER megafunction decodes the data output from the RAM before transferring the data out to other parts of the logic. In this design example, the raw data width is 8 bits and is encoded by the ALTECC_ENCODER megafunction block to produce a 13-bit width data that is written into the true dual-port RAM when write-enable signal is asserted. Because the RAM mode has two dedicated write ports, another encoder is implemented for the other RAM input port.
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Chapter 4: Design Example External ECC Implementation with True-Dual-Port RAM
Two ALTECC_DECODER megafunction blocks are also implemented at each of the data output ports of the RAM. When the read-enable signal is asserted, the encoded data is read from the RAM address and decoded by the ALTECC_DECODER megafunction blocks, respectively. The decoder shows the status of the data as no error detected, single-bit error detected and corrected, or fatal error (more than 1-bit error). This example also includes a "corrupt zero bit" control signal at port A of the RAM. When the signal is asserted, it changes the state of the zero-bit (LSB) encoded data before it is written into the RAM. This signal is used to corrupt the zero-bit data storing through port A, and examines the effect of the ECC features. 1 This design example describes how ECC features can be implemented with the RAM for cases in which the ECC is not supported internally by the RAM. However, the design examples might not represent the optimized design or implementation.
Generating the ALTECC_ENCODER and ALTECC_DECODER Megafunctions with Dual-Port-RAM

To generate the ALTECC_ENCODER and ALTECC_DECODER megafunctions with the dual-port-RAM, follow these steps: 1. Open the Internal_Memory_DesignExample.zip file and extract true_dp.qar. 2. In the Quartus II software, open the true_dp.qar file and restore the archive file into your working directory. 3. On the Tools menu, click MegaWizard Plug-In Manager. Page 1 of the MegaWizard Plug-In Manager appears. 4. Select Create a new custom megafunction variation. 5. Click Next. Page 2a of the MegaWizard Plug-In Manager appears. 6. In the MegaWizard Plug-In Manager pages, select or verify the configuration settings shown in Table 41. Click Next to advance from one page to the next.
Table 41. Configuration Settings for the ALTECC_ENCODER Megafunction MegaWizard Plug-In Manager Page Option Currently selected device family: How wide should the data be? Do you want to pipeline the functions? Create an 'aclr' asynchronous clear port Create a 'clocken' clock enable clock Stratix III 8 bits Yes, I want an output latency of 1 clock cycle Not selected Not selected Value
How do you want to configure this module? Configure this module as an ECC encoder 3
7. Click Finish. The ecc_encoder.v module is built. 8. Repeat steps 3 to 5.
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9. In the MegaWizard Plug-In Manager pages, select or verify the configuration settings shown in Table 41. Click Next to advance from one page to the next.
Table 42. Configuration Settings for the ALTECC_DECODER Megafunction MegaWizard Plug-In Manager Page Option Currently selected device family: How wide should the data be? Do you want to pipeline the functions? Create an 'aclr' asynchronous clear port Create a 'clocken' clock enable clock Stratix III 13 bits Yes, I want an output latency of 1 clock cycle Not selected Not selected Value
How do you want to configure this module? Configure this module as an ECC decoder 3
10. Click Finish. The ecc_decoder.v module is built. f For more information about the options available from the ALTECC MegaWizard Plug-In Manager, refer to Integer Arithmetic Megafunctions User Guide. 11. Repeat steps 3 to 5. 12. In the MegaWizard Plug-In Manager pages, select or verify the configuration settings shown in Table 41. Click Next to advance from one page to the next.
Table 43. Configuration Settings for the RAM:2-Port Megafunction (Part 1 of 2) MegaWizard Plug-In Manager Page Megafunction Which device family will you be using? 2a Which type of output file do you want to create? What name do you want for the output file? Return to this page for another create operation Currently selected device family: Parameter Settings (General) How will you be using the dual port ram? How do you want to specify the memory size? How many 8-bit words of memory? Parameter Settings (Widths/Blk Type) Use different data widths on different ports How wide should the 'q_a' output bus be? What should the memory block type be? Set the maximum block depth to Option Value Under the Memory Compiler category, select RAM:2-Port Stratix IV Verilog HDL true_dp_ram Turned off Stratix III With two read/write ports As a number of words 16 Not selected 13 M9K Auto
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Table 43. Configuration Settings for the RAM:2-Port Megafunction (Part 2 of 2) MegaWizard Plug-In Manager Page Option Which clocking method do you want to use? Create 'rden_a' and 'rden_b' read enable signals Byte Enable Ports Which ports should be registered? Parameter Settings (Regs/Clkens.Aclrs) Create one clock enable signal for each signal Create an 'aclr' asynchronous clear for the registered ports Mixed Port Read-During-Write for Single Input Clock RAM Port A Read-During-Write Option Port B Read-During-Write Option Do you want to specify the initial content of the memory? Generate netlist Variation file (.vhd) AHDL Include file (.inc) Summary VHDL component declaration file (.cmp) Quartus II symbol file (.bsf) Instantiation template file(.vhd) Turned off Turned on Turned off Turned on Turned off Turned off Single clock Not selected Not selected All write input ports and read output ports Not selected Not selected Old memory contents appear New Data Old Data Value
Parameter Settings (Clks/Rd, Byte En)
Parameter Settings (Output 1) Parameter Settings (Output 2) Parameter Settings (Mem Init) EDA
13. Click Finish. The true_dp_ram.v module is built. The top_dpram.v is a design variation file that contains the top level file that instantiates two encoders, a true dual-port RAM, and two decoders. To simulate the design, a testbench, true_dp_ram.vt, is created for you to run in the ModelSim-Altera software.
Simulating the Design

To simulate the design in the ModelSim-Altera software, follow these steps: 1. Unzip the Internal_Memory_DesignExample.zip file to any working directory on your PC. 2. Start the ModelSim-Altera software. 3. On the File menu, click Change Directory. 4. Select the folder in which you unzipped the files. 5. Click OK 6. On the Tools menu, point to TCL and click Execute Macro. The Execute Do File dialog box appears.
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7. Select the true_dp.do file and click Open. The true_dp.do file is a script file that automates all the necessary settings, compiles and simulates the design files, and displays the simulation waveform. 8. Verify the result shown in the Waveform Viewer window. You can rearrange signals, remove signals, add signals, and change the radix by modifying the script in true_dp.do accordingly.
Simulation Results
The top-level block contains the input and output ports shown in Table 44.
Table 44. Top-level Input and Output Ports Representations Ports Name clock corrupt_dataa_bit0 address_a data_a wren_a rden_a address_b data_b wren_b rden_b rdata1 err_corrected1 err_detected1 err_fatal1 rdata2 err_corrected2 err_detected2 err_fatal2
Notes to Table 44:
(1) For input ports, only data signal goes through the encoder; others bypass the encoder and go directly to the RAM block. Because the encoder uses one pipeline, signals that bypass the encoder require additional pipelines before going to the RAM. This has been implemented in the top level. (2) The encoder and decoder each use one pipeline while the RAM uses two pipelines, making the total pipeline equal to four. Therefore, read data is only shown at output ports four clock cycles after the read enable is initiated.
Ports Type Input Input
Descriptions System Clock for the encoders, RAM, and decoders. Registered active high control signal that 'twist' the zero bit (LSB) of input encoded data at port A before writing into the RAM. (1)
Input
Address input, data input, write enable, and read enable to port A of the RAM. (1)
Input
Address input, data input, write enable, and read enable to port B of the RAM. (1)
Output
Output data read from port A of the RAM, and the ECC-status signals reflecting the data read. (2)
Output
Output data read from port B of the RAM, and the ECC-status signals reflecting the data read. (2)
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Figure 41 shows the expected simulation waveform results in the ModelSim-Altera software.
Figure 41. Simulation Results
Figure 42 shows the timing diagram of when the same-port read-during-write occurs for each port A and port B of the RAM.
Figure 42. Same-Port Read-During-Write
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At 2500 ps, same-port read-during-write occurs for each port A and port B. Because the true dual-port RAM configured to port A is reading the new data and port B is reading the old data when the same-port read-during-write occurs, the rdata1 port shows the new data aa and the rdata2 port shows the old data 00 after four clock cycles at 17500 ps. When the data is read again from the same address at the next rising clock edge at 7500 ps, the rdata2 port shows the recent data bb at 22500 ps. Figure 43 shows the timing diagram of when the mixed-port read-during-write occurs.
Figure 43. Mixed-Port Read-During-Write
At 12500 ps, mixed-port read-during-write occurs when data cc is both written to port A, and is reading from port B, simultaneously targeting the same address 1. Because the true dual-port RAM that is configured to mixed-port read-during-write is showing the old data, the rdata2 port shows the old data bb after four clock cycles at 27500 ps. When the data is read again from the same address at the next rising clock edge at 17500 ps, the rdata2 port shows the recent data cc at 32500 ps.
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Figure 44 shows the timing diagram of when the write contention occurs.
Figure 44. Write Contention
At 22500 ps, the write contention occurs when data dd and ee are written to address 0 simultaneously. Besides that, the same-port read-during-write also occurs for port A and port B. The setting for port A and port B for same-port read-during-write takes effect when the rdata1 port shows the new data dd and the rdata2 port shows the old data aa after four clock cycles at 37500 ps. When the data is read again from the same address at the next rising clock edge at 27500 ps, rdata1 and rdata2 ports show unknown values at 42500 ps. Apart from that, the unknown data input to the decoder also results in an unknown ECC status.
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Figure 45 shows the timing diagram of the effect when an error is injected to twist the LSB of the encoded data at port A by asserting corrupt_dataa_bit0.
Figure 45. Error Injection Asserting corrupt_dataa_bit0
At 32500 ps, same-port read-during-write occurs at port A while mixed-port readduring-write occurs at port B. The corrupt_dataa_bit0 is also asserted to corrupt the LSB of encoded data at port A; therefore, the storing data has the LSB corrupted, in which the intended data ff is corrupted, becomes fe, and stored at address 0. After four clock cycles at 47500 ps, the rdata1 port shows the new data ff that has been corrected by the decoder, and the ECC status signals, err_corrected1 and err_detected1, are asserted. For rdata2 port, old data (which is unknown) is shown and the ECC-status signal remains unknown. 1 The decoders correct the single-bit error of the data shown at rdata1 and rdata2 ports only. The actual data stored at address 0 in the RAM remains corrupted, until new data is written. At 37500 ps, the same condition happens to port A and port B. The difference is port B reads the corrupted old data fe from address 0. After four clock cycles at 52500 ps, the rdata2 port shows the old data ff that has been corrected by the decoder and the ECC status signals, err_corrected2 and err_detected2, are asserted to show the data has been corrected.
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Chapter 4: Design Example Document Revision History
Document Revision History

Table 45 lists the revision history for this document.
Table 45. Document Revision History Date November 2013 May 2013 Version 4.3 4.2 Changes Updated Table 38 on page 317 to update M20K block information. Updated Table 34 on page 310 to fix a typographical error.
Added a note to the Asynchronous Clear on page 314 to state that internal contents cannot be cleared with the asynchronous clear signal. Updated note in Clocking Modes and Clock Enable on page 310 to include Stratix V devices. Added a note to the Asynchronous Clear on page 314 to clarify that clear deassertion on output latch is dependent on output clock. Updated the RAM2:Port parameter settings. Updated the Read-During-Write section. Added M10K memory block information. Added support information for Arria V and Cyclone V.
November 2012
4.1
January 2012
4.0
Added a note to Power-Up Conditions and Memory Initialization section.

November 2011
3.0
March 2011 November 2009
2.0 1.0
Added new features for M20K memory block. Initial release

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Internal Memory (RAM and ROM) User Guide

Internal Memory (RAM and ROM) User Guide

101 Innovation Drive San Jose, CA 95134 www.altera.com UG-01068-4.3

ISO 9001:2008 Registered

Internal Memory (RAM and ROM) User Guide

1. About Internal Memory Blocks

RAM:1-PortSingle-port RAM RAM:2-PortDual-port RAM ROM:1-PortSingle-port ROM ROM:2-PortDual-port ROM

Internal Memory (RAM and ROM) User Guide

Chapter 1: About Internal Memory Blocks Device Support

Internal Memory (RAM and ROM) User Guide

November 2013 Altera Corporation

How wide should the q output bus be?

How many <X>-bit words of memory?

What should the memory block type be?

Set the maximum block depth to

Internal Memory (RAM and ROM) User Guide

Chapter 2: Parameter Settings

Specifies whether to register the input and output ports.

Create byte enable for port A

What is the width of a byte for byte enables?

MLAB: 5 or 10 Other memory block types: 8 or 9 M10K and M20K: 8, 9, or 10

MLAB: 5 Other memory block types: 8

Create an aclr asynchronous clear for the registered ports.

Internal Memory (RAM and ROM) User Guide

November 2013 Altera Corporation

Chapter 2: Parameter Settings

Create a rden read enable signal

Parameter Settings: Read During Write Option

New data, Dont Care

Parameter Settings: Mem Init

Internal Memory (RAM and ROM) User Guide

Chapter 2: Parameter Settings

Table 22 lists the parameter settings for the RAM:2-Port.

Specifies how you use the dual port RAM.

Determines whether to specify the memory size in words or bits.

What should the memory block type be?

Internal Memory (RAM and ROM) User Guide

November 2013 Altera Corporation

Chapter 2: Parameter Settings

Set the maximum block depth to

Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096

Parameter Settings: Clks/Rd, Byte En

What clocking method would you like to use?

Internal Memory (RAM and ROM) User Guide

Chapter 2: Parameter Settings

Create byte enable for port B

Internal Memory (RAM and ROM) User Guide

November 2013 Altera Corporation

Chapter 2: Parameter Settings

Internal Memory (RAM and ROM) User Guide

Chapter 2: Parameter Settings

Create one clock enable signal for each clock signal.

Internal Memory (RAM and ROM) User Guide

November 2013 Altera Corporation

Chapter 2: Parameter Settings

Create an wr_addressstall input port. Create an rd_addressstall input port.

Create an aclr asynchronous clear for the registered ports.

rdaddress port q_b port On/Off Off

q_a port q_b port

Internal Memory (RAM and ROM) User Guide

Chapter 2: Parameter Settings

Internal Memory (RAM and ROM) User Guide

November 2013 Altera Corporation

Chapter 2: Parameter Settings