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6.1. Introduction to Memory Interface 6.2. Memory Interface 6.3. Memory Devices 6.4. Memory Decoding
Memory Connection
The connections that all memory devices have in common are Address inputs, Data Outputs and / or Inputs, some type of Selection Input and at least one Control Input to Read or Write Data.
Dr. Ridha Jemal EE353: Introduction to Microprocessor 1431-1432 2
RAM ( Random Access Memory ). Memory is Erased when DC Power is Off. SRAM ( Static Random Access Memory ) DRAM ( Dynamic Random Access Memory ) ROM ( Read Only Memory ). Memory is Permanently Stored even Power is Off. PROM ( Programmable Read Only Memory ) EPROM ( Erasable Programmable Read Only Memory ) EEPROM ( Electrically Erasable Programmable Read Only Memory )
Memory Interface
Memory Pin Connections
Address Connections
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
O0 O1 O2 O3 O4 O5 O6 O7
Data Connections
Write Enable
WE CS OE
Chip Select
Output Enable
memory device. Not all memory devices are 8 bits wide, there are 4 bits or even 1 bit wide memory devices also. It is often mentioned as 2 K x 8.
An 8-bit-wide memory device is often called a byte-wide memory.
o most devices are currently 8 bits wide, o some are 16 bits, 4 bits, or just 1 bit wide
Selection Connections
Each memory device has an Input ( sometimes more then one ) that Selects or Enables memory device. This kind of Input is called CS (Chip Select or G2A) or CE (Chip Enable) input. RAM memory has at least one CS input. ROM memory has at least one CE input. Logic 0 activates CE or CS and memory can Read or Write Logic 1 Deactivates CE or CS and memory can not Read or Write since it is turned Off or Disabled.
The OE input actually Enables and Disables a Set of Three-State buffer located within the memory device. RAM has One or Two Control inputs.
o If there is One Control input it is often called R/W to select a Read operation or Write operation provided CS (Chip Select is also active). o If RAM has Two Control inputs, they are labeled as WE and OE . WE must be active to perform a memory Write operation and OE must be active to perform a memory Read operation. Both must not be active at the same time.
If both WE and OE are inactive ( Logic 1 ), then Data can neither be Read nor Written
Dr. Ridha Jemal EE353: Introduction to Microprocessor 1431-1432 8
Memory Devices
ROM Memory
Read-only memory (ROM) permanently stores programs/data resident to the system.
o and must not change when power disconnected
Often called nonvolatile memory, because its contents do not change even if power is disconnected. A device we call a ROM is purchased in mass quantities from a manufacturer.
o programmed during fabrication at the factory
PROM Memory
PROM memory devices are also available, although they are not as common today. The PROM (programmable read-only memory) is also programmed in the field by burning open tiny Nichrome or silicon oxide fuses. Once it is programmed, it cannot be erased.
Dr. Ridha Jemal EE353: Introduction to Microprocessor 1431-1432 9
EPROM Programmer
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Static RAM
Basic six-transistor static Memory cell These transistor are connected to form a simple RS flip-flop.
Dr. Ridha Jemal EE353: Introduction to Microprocessor 1431-1432 14
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Memory Interfaces
SRAM Interface Example
To interface means to connect in a compatible manner. When interfacing memory, all the three system buses the address, control and data buses are involved.
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Memory Interfaces
Interfacing the 8088p.
64K x 8 8088 SRAM interface. Only a single memory chip is required.
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Memory Interfaces
Address Decoding
In order to attach a memory device to the microprocessor, it is necessary to decode the address sent from the microprocessor. Decoding makes the memory function at a unique section or partition of the memory map. Without an address decoder, only one memory device can be connected to a microprocessor, which would make it virtually useless.
Memory Interfaces
Simple NAND Gate Decoder
When the 64K x 8 SRAM is used, address connections A15A0 of 8088 are connected to address inputs A15A0 of the SRAM. the remaining four address pins (A19A16) are connected to a NAND gate decoder The decoder selects the SRAM from one of the 64K-byte sections of the 1M-byte memory system in the 8088 microprocessor. In this circuit a NAND gate decodes the memory address, as seen in the following figure. If the 20-bit binary address, decoded by the NAND gate, is written so that the leftmost nine bits are 1s and the rightmost 11 bits are dont cares (X), the actual address range of the SRAM can be determined. a dont care is a logic 1 or a logic 0, whichever is appropriate Because of the excessive cost of the NAND gate decoder and inverters often required, this option requires an alternate be found.
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Memory Interfaces
Simple NAMD Gate Decoder Example
Example of an address decoder for the 8088 memory interface in previous figure. The memory will be enabled only when A19-A16 = 1110.
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Memory Interfaces
Memory Mapping
Memory map for the 8088 interface and decoder. The 64K SRAM is mapped to the address range E0000H to EFFFFH.
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Memory Interfaces
Example of Memory Decoding with NAND Gates
Design a Decoder to map the SRAM to the range C0000- CFFFFH using NAND gates.
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Memory Interfaces
Interface Between Memory and 8086 Microprocessor
Even and Odd Memory bank SRAM for even (D0-D7) and SRAM for odd (D8-D15)
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Memory Interfaces
3-to-8-line decoder (74LS138)
Decoder and Function Table
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Memory Interfaces
A0
2764 EPROM
A12 O0
O7 OE CE
The decoder selects eight 8K-byte blocks of memory for a total capacity of 64K bytes The outputs of the decoder in the figure, are connected to eight different 2764 Ridha EPROM memory devices. Dr. Jemal EE353: Introduction to Microprocessor 1431-1432 25
Memory Interfaces
Example of Memory Decoding with 3-to-8-line decoder
The outputs of the decoder in the figure, are connected to eight different 2764 EPROM memory devices. This figure also illustrates the address range of each memory device and the common connections to the memory devices. all address connections from the 8088 are connected to this circuit. the decoders outputs are connected to the CE inputs of the EPROMs,
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Memory Interfaces
Example of Memory Decoding with 3-to-8-line decoder
the RD signal from the 8088 is connected to the OE inputs of the EPROMs In this circuit, a three-input NAND gate is connected to address bits A19A17. When all three address inputs are high, the output of this NAND gate goes low and enables input G2B of the 74LS138. Input G1 is connected directly to A16. In order to enable this decoder, the first four address connections (A19A16) must all be high. Address inputs C, B, and A connect to microprocessor address pins A15A13. These three address inputs determine which output pin goes low and which EPROM is selected whenever 8088 outputs a memory address within this range to the memory system.
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Memory Interfaces
Example of Memory Decoding with 2-to-8 line decoder 74LS138
1Mbyte Memory Interface (512K Memory Bank + 512 K memory Bank) for 8086
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Memory Interfaces
Example of 8086 Interface (EPROM and SRAM)
To 32KxEPROM (F0000H-FFFFFH) and 8Kx16 SRAM (00000H-03FFFH)
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Other Decoders
The Dual 2-to-4 line decoder (74LS139)
pin-out and the truth table for the 74LS139 dual 2-to-4 line decoder. 74LS139 contains two separate 2-to-4 line decoderseach with its own address, enable, and output connections. A more complicated decoder using the 74LS139 decoder appears in the figure
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