B. E.

Boser 1
Analog Design Using
g
m
/I
d
and f
t
Metrics
Bernhard E. Boser
boser@eecs.berkeley.edu

Copyright 2011 Bernhard Boser
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 2
Overview
Traditional analog design methodologies typically require iteration
Square Law design equations are inaccurate for submicron devices
Depend on poorly defined parameters: C
ox
, V
th
, V
dsat
,

Difficult to achieve an optimum (e.g. minimum power)

g
m
/I
d
-based design
Links design variables (g
m
, f
t
, I
d
, ) to specification (bandwidth, power)
Employs design charts to accurately size transistors

Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 3
Motivation: A design example
Specifications:
Small signal gain: a
v
= v
o
/v
i
= 5
Bandwidth: B 10MHz
Source resistance: R
s
= 1MO
Load capacitance: C
L
= 5pF
Minimum power dissipation
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 4
Design Approaches
Design equations (Square-Law model)




Difficulties
Sub-micron transistors are not well
described by these equations
Non-obvious relation of model
parameters to design specification
Leads to many iterations
What is the minimum power, anyway?


Analog design using g
m
/I
d
and f
t
metrics
( )
( )
2
1
2
. ...
W
d ox GS TH L
W
m ox GS TH L
GS ox
I C V V
g C V V
C C WL
etc
=
=
=

B. E. Boser 5
Natural Variables for Analog Design
I
d
V
DS
V
GS
i
d
v
gs
v
ds C
gs
Transconductance g
m
Current I
d
Efficiency g
m
/I
d
Capacitance C
gs
,
Transit frequency f
t
= g
m
/2tC
gs
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 6
Example
Specifications:
Small signal gain: a
v
= v
o
/v
i
= 5
Bandwidth: B 10MHz
Source resistance: R
s
= 1MO
Load capacitance: C
L
= 5pF
Minimum power dissipation
Design constraints
Low frequency gain
Pole at input
Pole at output
Analog design using g
m
/I
d
and f
t
metrics
a
v
L
g
m
R =
1 1
2
s gs
p
in
C R B t
= >
1 1
2
L L
p
out
B R C
= >
t
2
1
2
minimize
m
GS
d
L
s
g
BR
C
I
BC t
t
>
s
B. E. Boser 7
Design Constraints and Objectives
Design constraints
Analog design using g
m
/I
d
and f
t
metrics
Design objectives
1. High current efficiency
to minimize power

2. Small C
gs
high f
T

to meet bandwidth
constraint

2 1.57 mS
1
16 fF
2
minimize
m
s
GS
d
L
g
R
I
BC
B
C
t
t
> =
= s
m
d
g
I
2
m
t
gs
g
f
C t
=
B. E. Boser 8
Transit Frequency f
T
Analog design using g
m
/I
d
and f
t
metrics
NMOS (simulation)
f
T
versus g
m
/I
d
tradeoff
Compromise
high g
m
/I
d
for low power
high f
t
for low C
gs

Design choice
Maximum C
gs
to meet
specification at
minimum power:
minimum f
t
minimum L
maximum g
m
/I
d

,min
,min
,max
15.7 GHz
2
m
t
gs
g
f
C t
= =
15.7 GHz
14 V
-1
B. E. Boser 9
Transistor Current Efficiency g
m
/ I
d
Analog design using g
m
/I
d
and f
t
metrics

Weak Inversion

Good current efficiency

High output voltage range

Low f
t
Large transistors
(low )
sat
d
V
Strong Inversion

Poor current efficiency
Low output voltage range


High f
t
Small transistor

5 10 15 20
400m 200m 133m 100m
1
[ V ]
m d
g I

2
[ V ]
m d
g I
Low
g
m
/I
d
High
g
m
/I
d
B. E. Boser 10
Completing the Design: Transistor Sizing
Analog design using g
m
/I
d
and f
t
metrics
1
14 V and 16 GHz
112 A
A
12.4 (from chart)
m
9 m
m
T
d
m
d
m d
d
d
d
g
f
I
g
I
g I
I
W
I
W
I W

= =
= =
=
= =
12.4 A/m
14 V
-1
B. E. Boser 11
Verification: (1) Bias
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 12
Verification: (2) Specification
Bias is as designed
Gain and bandwidth
slightly below spec
Design ignored
transistor r
o
and self-
loading
Adjust by choosing a
slightly higher f
t

Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 13
Summary
Analog design using g
m
/I
d
and f
t
metrics
Silicon
Square Law
based design
SPICE Model
g
m
/I
d

based design

Simple
Square Law
Equations

Complicated
Equations
(BSIM, PSP, )

Complicated
Physics


g
m
/I
d
& f
t
Charts
(process specific)
Accurate
Good for verification
Unsuitable for
design
Popular (textbooks)
Poor accuracy
Requires iterations
Difficult to achieve
optima
Good accuracy
Simple equations
Transistor data
from charts
B. E. Boser 14
NMOS Transit Frequency f
T
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 15
PMOS Transit Frequency f
T
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 16
Extrinsic Capacitances C
gd
and C
dd
Analog design using g
m
/I
d
and f
t
metrics
NMOS PMOS
B. E. Boser 17
NMOS Current Density
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 18
PMOS Current Density
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 19
NMOS Intrinsic Gain g
m
r
o
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 20
PMOS Intrinsic Gain g
m
r
o
Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 21
Intrinsic Gain g
m
r
o
Analog design using g
m
/I
d
and f
t
metrics
NMOS PMOS
B. E. Boser 22
OTA Design Example

Specifications
Voltage gain A
v
= 2
Dynamic range DR 72dB
Settling accuracy c
d
100ppm
Settling time t
s
10ns
Analog design using g
m
/I
d
and f
t
metrics
+
v
id
-
+
v
od
-
C
s
C
s
C
f
C
f
C
L
C
L
Switched capacitor gain stage
(switches not shown)

Applications: A/D converters, filters,
B. E. Boser 23
Circuit Topology

Analog design using g
m
/I
d
and f
t
metrics
v
id
v
od
vi
Ro
Gmvx
Co
Cx
vo
CL
Cf
Cs
vx
V
DD
V
ip
V
im
V
om
- V
od
+
V
op
I
T
I
T
/2
MN1a MN1b
MP1a MP1b
MPB
Fully differential OTA
Common mode and
cascodes (for gain) not shown
Differential mode half circuit
Large & small signal models
B. E. Boser 24
Design Flow
1. Determine feedback factor
2. Determine C
L
to meet dynamic range requirement
3. Determine g
m
to meet settling requirement
4. Pick transistor characteristics based on analysis
Channel length L
Current efficiency g
m
/I
D
(or f
t
)
5. Determine bias currents and transistor sizes
I
D
(from g
m
and g
m
/I
D
)
W (from I
D
/W, current density chart)

Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 25
(1) Feedback Factor
Open feedback loop
C
x
is amplifier input capacitance (C
gs
+ )
Small C
x
large feedback factor |
Large C
x
low transistor f
t
requirement higher g
m
/I
d
reduced current
Typically C
x
= ( 1) x (C
s
+ C
f
) (shallow optimum)
Analog design using g
m
/I
d
and f
t
metrics
1
1
x f
x
o f s x
v
f
v C
C
v C C C
A
C
| = = =
+ +
+ +
v
i
R
o
G
m
v
x
C
o
C
x
v
o
C
L
C
f
C
s
v
x
B. E. Boser 26
(2) Dynamic Range
Dynamic range:

Minimum load capacitance:
Analog design using g
m
/I
d
and f
t
metrics
C
Ltot
|v
o
v
o
MP
MN
4kT
p
g
mp
4kT
n
g
mn
R
1
mn
R
g
~
|
2
2
,
4 1
1
mp d o n
mn
mn d Ltot
g I v
R
kT g
f g I j RC

e
| |
= +
|
A +
\ .
( )
2
,
1
1
with 1
mp
o n
mn
Ltot L f
Ltot
g
k
C
C
T
v
g
C C
| |
= +
|
|
\ .
= + |
Output resistance:
Noise density:
Sampled noise:
2
,max
2 1
mp
Ltot
mn
o
g
DR
C kT
g
V
| |

> +
|
|
\ .
2
1
,max
2
2
,
o
o n
V
DR
v
=
choose for low noise
mp
mn
d d
g
g
I I
<
PMOS
B. E. Boser 27
(3) Settling
Analog design using g
m
/I
d
and f
t
metrics
G
m
V
out
C
f
C
s
C
in
V
step
C
L
V
in
(t)
0
0 2 4 6 8 10
0
0.2
0.4
0.6
0.8
1
t/t
V
o
u
t
/
V
o
u
t
,
id
e
a
l
Dynamic Error c
d
(t) Static Error c
0
Settling time t
s
( )
/
0
0
Step response: ( ) 1 with
1
t
s Ltot
out step
f mn
C T C
v t V e
C T g
t
t
|

= =
+
/
s
t
d
e
t
c =
for single pole
response
Solve for transconductance:
ln
Ltot d
mn
s
C
g
t
c
>
|
ideal
response
static
error
dynamic
error
B. E. Boser 28
(4) Transistor Channel Length, g
m
/I
d
and f
t
Analog design using g
m
/I
d
and f
t
metrics
NMOS PMOS
L 180 nm 250 nm L
n,min
reduces power
g
m
/I
d
12 V
-1
8 V
-1
g
mp
/I
d
< g
mn
/I
d
(noise)
f
t
19.7 GHz 3.78 GHz C
gsn
< C
s
+ C
f
I
d
/W 18.7 A/m 7.06 A/m
Reduce g
m
/I
d
of NMOS if C
gsn
< C
s
+ C
f

f
t
and I
d
/W obtained from charts
B. E. Boser 29
(5) Bias Currents and Transistor Sizes
Analog design using g
m
/I
d
and f
t
metrics
ota1.mcd
B. E. Boser 30
Verification: (1) Test Bed
Analog design using g
m
/I
d
and f
t
metrics
OTA OTA in Feedback Loop
B. E. Boser 31
Verification: (2) Bias
Analog design using g
m
/I
d
and f
t
metrics
So far, so good
B. E. Boser 32
Verification: (3) Dynamic Range
Analog design using g
m
/I
d
and f
t
metrics
perfect!
B. E. Boser 33
Verification: (4) Settling Time
Analog design using g
m
/I
d
and f
t
metrics
Dynamic settling error target met
Large static error ~10%
B. E. Boser 34
Openloop Gain
Analog design using g
m
/I
d
and f
t
metrics
Openloop gain only A
vo
~ 50

T
o
= | A
vo
= 11



Add cascodes to increase
low frequency gain
B. E. Boser 35
Generic g
m
/I
d
-based Design Flow
1. Determine g
m
from design objectives (dynamic range, bandwidth, )
2. Pick L
Short channel high f
t
(high speed)
Long channel high intrinsic gain, good matching,
3. Pick g
m
/I
D
or f
t

Large g
m
/I
D
low power, large signal swing
Small g
m
/I
D
high f
t
(high speed)
4. Determine I
D
(from g
m
and g
m
/I
D
)
5. Determine W (from I
D
/W, current density chart)

Adapt to design specifics

Analog design using g
m
/I
d
and f
t
metrics
B. E. Boser 36
Acknowledgements
Prof. Boris Murmann
Prof. Paul Gray
Prof. Ali Niknejad
Prof. Elad Alon

Many generations of students
Analog design using g
m
/I
d
and f
t
metrics