BECCEC502R01/ MCSCEC502R01 Unit I

MICROPROCESSORS

2 Mark Questions and Answers

1. Mention any five data types supported by 80386 Signed byte: Signed byte data. Sign of the operand depends upon its most significant bit. If it is 0, then the number is positive. else it is negative. Range is from -128 to 127., Unsigned byte: Unsigned byte data.Range from 0 to 255., Integer: Signed 16-bit data. Range from -32,768 to 32,767. Long integer: 32-bit signed data that is represented in 2's complement form. Range is from -2,147,483,648 to 2,147,483,647. BCD - Decimal digits from 0-9 represented by unpacked bytes. 2. What are the 8, 16 and 32 bit main registers available in 80386 AL, BL, CL and DL are the 8 bit registers, AX, BX, CX and DX are the 16 bit registers and EAX, EBX, ECX and EDX are the 32 bit registers available in 80386 3. What are the 16 and 32 bit index registers available in 80386 SI, DI, BP and SP are the 16 bit index registers, ESI, EDI, EBP and ESP are the 32 bit index registers available in 80386 4. What are the 16 and 32 bit Instruction pointers available in 80386 IP and EIP the 16 and 32 bit Instruction pointers available in 80386 5. What are the segment selectors available in 80386? CS, DS, ES, SS, FS AND GS are the segment selectors available in 80386 6. What are the three sections available with the Internal Architecture of 80386 It is divided into 3 sections. Central processing unit, Memory management unit and Bus interface unit 7. What are the sections available with CPU Central processing unit is divided into Execution unit and Instruction unit 8. How many General purpose and Special purpose registers available with execution unit of 80386 8 General purpose and Special purpose registers are available in the execution unit and is used for handling data or calculating offset addresses. 9. What is the function of instruction unit ? The Instruction unit decodes the opcode bytes received from the 16-byte instruction

code queue and arranges them in a 3- instruction decoded instruction queue.After decoding them pass it to the control section for deriving the necessary control signals. The barrel shifter increases the speed of all shift and rotate operations. The multiply / divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time. 10. What is the function of Memory management unit ? The Memory management unit consists of a Segmentation unit and a Paging unit. Segmentation unit allows the use of two address components, viz. segment and offset for relocability and sharing of code and data. Segmentation unit allows segments of size 4Gbytes at max. The Paging unit organizes the physical memory in terms of pages of 4kbytes size each. Paging unit works under the control of the segmentation unit, i.e. each segment is further divided into pages. The Paging unit organizes the physical memory in terms of pages of 4kbytes size each. Paging unit works under the control of the segmentation unit, i.e. each segment is further divided into pages. 11. What are the functions of the signals BE 0 to BE3? The 4 byte enable lines BE 0 to BE3 , may be used for enabling these 4 blanks. Using these 4 enable signal lines, the CPU may transfer 1 byte / 2 / 3 / 4 byte of data simultaneously. 12. What is the function of the pin HOLD ? The bus hold input pin enables the other bus masters to gain control of the system bus if it is asserted. 13. What is the function of the pin HLDA ? The bus hold acknowledge output indicates that a valid bus hold request has been received and the bus has been relinquished by the CPU. 14. What is the function of the pin BUSY? The busy input signal indicates to the CPU that the coprocessor is busy with the allocated task. 15. What is the function of the pin ERROR? The error input pin indicates to the CPU that the coprocessor has encountered an error while executing its instruction. 16. What is the function of the pin PEREQ The processor extension request output signal indicates to the CPU to fetch a data word for the coprocessor.

17. What is the function of the pin INTR? The interrupt pin is a maskable interrupt, that can be masked using the IF of the flag register. 18. What is the function of the pin NMI ? A valid request signal at the non-maskable interrupt request input pin internally generates a non- maskable interrupt of type2. 19. What is the function of the pin RESET ? A high at this input pin suspends the current operation and restart the execution from the starting location. 20. What is the function of extended register? A 32 - bit register known as an extended register, is represented by the register name with prefix E. Ex: A 32 bit register corresponding to AX is EAX, similarly BX is EBX 21. Define the flag register of 80386 The Flag register of 80386 is a 32 bit register. Out of the 32 bits, Intel has reserved bits D18 to D31, D5 and D3, while D1 is always set at 1.Two extra new flags are added to the 80286 flag to derive the flag register of 80386. They are VM and RF flags. 22. Define VM flag Virtual Mode Flag: If this flag is set, the 80386 enters the virtual 8086 mode within the protection mode. This is to be set only when the 80386 is in protected mode. In this mode, if any privileged instruction is executed an exception 13 is generated. This bit can be set using IRET instruction or any task switch operation only in the protected mode. 23. Define RF flag RF- Resume Flag: This flag is used with the debug register breakpoints. It is checked at the starting of every instruction cycle and if it is set, any debug fault is ignored during the instruction cycle. The RF is automatically reset after successful execution of every instruction, except for IRET and POPF instructions. Also, it is not automatically cleared after the successful execution of JMP, CALL and INT instruction causing a task switch. These instruction are used to set the RF to the value specified by the memory data available at the stack. 24. What are the four descriptor tables available with 80386? The 80386 supports four types of descriptor table, viz. global descriptor table (GDT), interrupt descriptor table (IDT), local descriptor table (LDT) and task state segment

descriptor (TSS). 25. What will be the memory location and the addressing mode when 80386 is being reset? After reset, the 80386 starts from memory location FFFFFFF0H under the real address mode. In the real mode, 80386 works as a fast 8086 with 32-bit registers and data types. 26. What is meant Descriptor ? The 80386 descriptors have a 20-bit segment limit and 32-bit segment address. The descriptor of 80386 is 8-byte quantities access right or attributes bits along with the base and limit of the segments. 27. What is meant by page descriptor base register? Paging Descriptor Base Register: The control register CR2 isused to store the 32-bit linear address at which the previous page fault was detected.The CR3 is used as page directory physical base address register, to store the physical starting address of the page directory. The lower 12 bit of the CR3 are always zero to ensure the page size aligned directory. A move operation to CR3 automatically loads the page table entry caches and a task switch operation, to load CR0 suitably. 28. What is meant by Page directory? Page Directory : This is at the most 4Kbytes in size. Each directory entry is of 4 bytes, thus a total of 1024 entries are allowed in a directory.The upper 10 bits of the linear address are used as an index to the corresponding page directory entry. The page directory entries point to page tables. 29. What is meant by Page table? Page Tables: Each page table is of 4Kbytes in size and many contain a maximum of 1024 entries. The page table entries contain the starting address of the page and the statistical information about the page 30. What is the function of LOCK pin in 80386? The LOCK output pin enables the CPU to prevent the other bus masters from gaining the control of the system bus. 31. How many addressing modes are there in 80386? There are eleven addressing modes to facilitate efficient execution of higher level language programs 32. What are the different scaled modes available with 80386?

Scaled indexed mode, Based scaled indexed mode, Based scaled indexed mode with displacement. 33. Define Scaled indexed mode The Contents of the an index register are multiplied by a scale factor that may be added further to get the operand offset. 34. Define Based scaled indexed mode Based Scaled Indexed Mode: Contents of the index register are multiplied by a scale factor and then added to base register to obtain the offset. 35. Define Based scaled indexed mode with displacement The Contents of the an index register are multiplied by a scaling factor and the result is added to a base register and a displacement to get the offset of an operand 36. What will be the memory location allocated to the interrupt vector table? The interrupt vector table of 80386 has been allocated 1Kbyte space starting from 00000H to 003FFH. 37. Define Linear and physical address The effective address (offset) is added with segment base address to calculate linear address. This linear address is further used as physical address, if the paging unit is disabled; Otherwise the paging unit converts the linear address into physical address. 38. What are the five types of descriptors available with 80386? Code or Data Segment Descriptors, System Descriptors, Local descriptors, TSS (Task State Segment) Descriptors, GATE Descriptors. 39. What is the function of D bit in paging? The D bit ( Dirty bit) is set before a write operation to the page is carried out. The D-bit is undefined for page director entries. 40. What is the function of OS reserved bits in paging? The OS reserved bits are defined by the operating system software 41. What is the function of U/S and R/W bits in paging? The User / Supervisor (U/S) bit and read/write bit are used to provide protection. These bits are decoded to provide protection under the 4 level protection model. 42. What is protected mode in 80386?

In its protected mode of operation, 80386DX provides a virtual 8086 operating environment to execute the 8086 programs. The real mode can also used to execute the 8086 programs along with the capabilities of 80386, like protection and a few additional instructions. Once the 80386 enters the protected mode from the real mode, it cannot return back to the real mode without a reset operation. Thus, the virtual 8086 mode of operation of 80386, offers an advantage of executing 8086 programs while in protected mode. 43. Give the format of 32 bit Linear address in 80386 31 ...... 22 21 ...... 12 11 ...... 0 DIR TABLE OFFSET

44. How the physical address is computed in the Hardware of 80386? CR3 + DIR table_base TABLE + points to the table_base. points to the page_base.

physical_address page_base + OFFSET =

45. Give the format for Page directory 31 ...... 12 11 .. 9 8 7 6 5 4 3 2 ADDRESS OS 1 0

0 0 D A 0 0 U/S R/W P

D=1 means page is dirty (undefined for page directory entry). R/W= 0 means readonly for user. U/S =1 means user page.P1 means page is present in memory. A=1 means page has been accessed (set to 0 by aging). OS bits can be used for LRU etc, and are defined by the OS. 46. What is the function of segments in 80386? Segment registers are used in address translation to generate a linear address from a logical (virtual) address.linear_address = segment_base + logical_address.The linear address is then translated into a physical address by the paging hardware.Each segment in the system is described by a 8 byte segment descriptor which contains all pertinent information (base, limit, type, privilege). 47. What are the segments available in 80386?

The segments are regular segments - code and data segments and System segments - Task State Segments (TSS), Local Descriptor Tables (LDT).

48. Mention any two characteristics of system segments? System segments are task specific.There is a Task State Segment (TSS) associated with each task in the system. It contains the tss_struct (sched.h). The size of the segment is that of tss_struct excluding the i387_union (232 bytes). It contains all the information necessary to restart the task.The LDT's contain regular segment descriptors that are private to a task. In Linux there is one LDT per task 49. Give the format of segment selector 15 ...... 3 2 1 0 index TI RPL TI Table indicator: 0 means selector indexes into GDT, 1 means selector indexes into LDT RPL Privelege level. Linux uses only two privelege levels.0 means kernel 3 means user 50. Give the format of segment descriptor in 80386 There is a segment descriptor used to describe each segment in the system. There are regular descriptors and system descriptors. Here's a descriptor in all its glory. The strange format is essentially to maintain compatibility with the 286. Note that it takes 8 bytes. 63-54 55 54 53 52 51-48 47 46 45 44-40 39-16 15-0

Base Limit Segment Base Segment Limit G D R U P DPL S TYPE 31-24 19-16 23-0 15-0 reserved (0) DPL 0 means kernel, 3 means user 1 means 4K granularity (Always set in Linux) G D U P S 1 means default operand size 32bits programmer definable 1 means present in physical memory 0 means system segment, 1 means normal code or data segment.

Type There are many possibilities. Interpreted differently for system and normal descriptors.

51. Define Microprocessor. A microprocessor (P) is a digital electronic component with miniaturized transistors on a single semiconductor integrated circuit (IC).
52. Define microcomputer. A microcomputer contains a CPU on a microchip (the microprocessor), a memory system (typically ROM and RAM), a bus system and I/O ports, typically housed in a motherboard. 53. What is the function of Program counter? To point the address of next instruction to be executed. 54. Define Central processing unit. CPU is the heart of the computer; this is the component that actually executes instructions. 55. Define Stack. A reserved set of memory locations in RAM memory locations, for the purpose of storing temporary data and return addresses during the time of function call and interrupt. It poses the property of LIFO. 56. Give the differences between CISC and RISC architecture.
CISC Emphasis on hardware Includes multi-clock complex instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Small code sizes, high cycles per second Transistors used for storing complex instructions RISC Emphasis on software Single-clock, reduced instruction only Register to register: "LOAD" and "STORE" are independent instructions Low cycles per second, large code sizes Spends more transistors on memory registers

57. Give the differences between Harvard and Von-neumann architecture. Von Neumann Architecture: The computer has single storage system(memory) for storing data as well as program to be executed. Processor needs two clock cycles to complete an instruction.Pipelining the instructions is not possible with this architecture. In the first clock cycle the processor gets the instruction from memory and decodes it. In the next clock cycle the required data is taken from memory. For each instruction this cycle repeats and hence needs two cycles to complete an instruction.

Harvard Architecture: The computer has two separate memories for storing data and program. Processor can complete an instruction in one cycle if appropriate pipelining strategies are implemented. In the first stage of pipeline the instruction to be executed can be taken from program memory.In the second stage of pipeline data is taken from the data memory using the decoded instruction or address. Most of the modern computing architectures are based on Harvard architecture.But the number of stages in the pipeline varies from system to system.

58. Define Super Harvard architecture. Super Harvard Architecture means having more than one set of address and data busses for accessing data. The Super Harvard Architecture Single-Chip Computer (SHARC) is a high performance floatingpoint and fixed-point DSP from Analog Devices.