BENM 1143 (LOGIC CIRCUITS)

CHAPTER 4

4 Types Of Combinational Logic Circuits

Arithmetic circuits are the one, which perform arithmetic operations like addition,
subtraction, multiplication, division, and parity calculation. Most of the time, designing
these circuits is same as designing mux, encoders and decoders.

4.1 Adders

Adders are the basic buliding blocks of all the arthmetic circuits, adders add two binary
numbers and give out sum and carry as output. Basically we have two types of adders.
• Half Adder.
• Full Adder.

 Half Adder

Adding two single-bit binary values, X, Y produces a sum S bit and a carry out C-out bit.
This operation is called half addition and the circuit to realize it is called a half adder.

Table 9.3:Truth Table of the half adder

X Y SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
S (X,Y) = ∑(1,2)
S = X’Y + XY’
S = X ⊕Y
CARRY (X,Y) = ∑(3)
CARRY = XY

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Figure 4.1: Symbol of the half adder

Figure 4.2: Circuit of the half adder

 Full Adder

Full adder takes three bit input. Adding two single-bit binary values, X, Y with a carry input
bit C-in produces a sum bit S and a carry out C-out bit.

Table 4.1: Truth Table of the full adder

X Y Z SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Boolean Algebra:
SUM (X,Y,Z) = (1,2,4,7) CARRY (X,Y,Z) = Σ(3,5,6,7)
SUM = Σ X Y Z

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SUM = X'Y'Z + XY'Z' + X'YZ'

CARRY = XY ⊕ XZ ⊕ YZ

Figure 4.3: Symbol of the full adder

 Full Adder using AND-OR

Below implementation show implementing the full adder which AND-OR gates, instead of
using XOR gates.

Figure 4.4: Sum circuit of the full adder using AND-OR gates

Figure 4.5: Carry circuit of the full adder using AND-OR gates
4.2 Encoders

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An encoder is combinational circuit that performs the inverse operation of a decoder. If the
decoder's output code has fewer bits than the input code, the device is usually called an
encoder. e.g. 2n-to-n, priority encoders. The simplest encoder is a 2n-to-n binary encoder
and it is shown in Figure 4.6. Where it has only one of 2n inputs = 1 and the output is the
n-bit binary number corresponding to the active input.

Figure 4.6: The simplest encoder is a 2n-to-n binary encoder

EXAMPLE 4.1: Octal-to-Binary Encoder

Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing opposite to 3-to-8 decoder.
At any one time, only one input line has a value of 1. Table 4.2 shows the truth table of a
Octal-to-binary encoder.

For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2
are:
Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 +I7

Table 4.2: The truth table of a Octal-to-binary encoder.

INPUTS OUTPUTS
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0

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1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

Based on above equations, we can draw the circuit as shown in Figure 4.7.

Figure 4.7: Final implementation of the 8-to-3 binary encoder design

EXAMPLE 4.2: Decimal-to-Binary Encoder

Decimal-to-Binary take 10 inputs and provides 4 outputs, thus doing opposite to 4-to-10
decoder. At any one time, only one input line has a value of 1. Below Table 4.3 shows the
truth table of a Decimal-to-binary encoder.

Table 4.3: The truth table of a Decimal-to-binary encoder.

INPUTS OUTPUTS
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0

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0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1

From the above truth table, the functions of Y3, Y2, Y1 and Y0 can be derived as given
below.

Y0 = I8 + I9
Y1 = I4 + I5 + I6 + I7
Y2 = I2 + I3 + I6 + I7
Y3 = I1 + I3 + I5 + I7 + I9

 Priority Encoder

If we look carefully at the Encoder circuits that we got, we see following limitations. If
more then two inputs are active simultaneously, the output is unpredictable or rather it is
not what we expect it to be. This ambiguity is resolved if priority is established so that only
one input is encoded, no matter how many inputs are active at given point of time.

Priority encoder is the one, which includes the priority function. The operation of
the priority encoder is such that if two or more inputs are active at the same time, the input
having the highest priority will take the precedence.
EXAMPLE 4.3: 4 to 3 Priority Encoder

The truth table of a 4-input priority encoder is as shown in Table 4.4. The input I3 has the
highest priority, I2 has next highest priority, I0 has the lowest priority. What this means is
output is Y0 and Y1 are 0 only when none of the inputs I1, I2, I3 are high and only I0 is
high.
Table 4.4: The truth table of a 4-input priority encoder
INPUTS OUTPUTS
D3 D2 D1 D0 Y2 Y1 Y0
0 0 0 0 0 0 0

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0 0 0 1 0 0 1
0 0 1 x 0 1 0
0 1 x x 0 1 1
1 x x x 1 0 0

Now that we have the truth table, we can draw the Kmaps as shown in Figure 4.8.
From the Kmap we can draw the circuit as shown in Figure 4.9. For Y2, we connect
directly to D3. We can apply same logic to get higher order priority encoders.

Figure 4.8: K map used to obtain the simplified expression

of a 4-input priority encoder

(a) (b)
Figure 4.9(a) and (b): The circuit for the 4-input priority encoder

4.3 Decoders

A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into
coded outputs, where the input and output codes are different. e.g. n-to-2n, BCD decoders.
Enable inputs must be on for the decoder to function, otherwise its outputs assume a single
"disabled" output code word. Decoding is necessary in applications such as data

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multiplexing, 7 segment display and memory address decoding. Figure 4.10 shows the
pseudo block of a decoder.

Figure 4.10: The pseudo block of a decoder.

 Basic Binary Decoder

And AND gate can be used as the basic decoding element. because its output is HIGH only
when all its inputs are HIGH. For example, if the input binary number is 0110, then, to
make all the inputs two the AND gate HIGH, the two middle bits must be inverted by using
two invertors as shown in Figure 4.11.

Figure 4.11: Simple Binary Decoder

 Binary n-to-2n Decoders

A binary decoder has n inputs and 2n outputs. Only the one output is active at any point of
time, corresponding to the input value. Figure 4.12 shows a representation of Binary n-to-
2n decoder.

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Figure 4.12: A representation of Binary n-to-2n

EXAMPLE 4.4: 2-to-4 Binary Decoder

A 2 to 4 decoder consists of two inputs and four outputs, Truth table and symbols of which
is shown in Table 4.4 and Figure 4.13.

Table 4.4: The truth table of a 2-to-4 decoder

X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

Figure 4.13: Symbols of a 2 to 4 decoder

To minimize above truth table we may use kmap, but doing that you will realize that it is
waste of time. One can directly write down the function for each of the outputs. Thus we
can draw the circuit as shown in Figure 4.14.

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Figure 4.14: The circuit of 2-to-4 decoder

Note: Each output is a 2-variable minterm (X'Y', X'Y, XY', XY)

EXAMPLE 4.5: 3-to-8 Binary Decoder

A 3 to 8 decoder consists of three inputs and eight outputs, Truth table and symbols of
which is shown below.

Table 4.5: The truth table of a 3-to-8 decoder

X Y Z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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Figure 4.15: The symbol of a 3-to-8 decoder

From the truth table we can draw the circuit diagram as shown in Figure 4.16

Figure 4.16: The circuit of a 3-to-8 decoder

4.4 Multiplexer

A multiplexer (MUX) is a digital switch, which connects data from one of n sources
to the output. A number of select inputs determine which data source is connected to the
output. The block diagram of MUX with n data sources of b bits wide and s bits wide select
line is shown in Figure 4.17.

MUX acts like a digitally controlled multi position switch where binary code
applied to the select inputs controls the input source that will be switched on to the output

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as shown in figure below. At any given point of time only one input gets selected and is
connected to output, based on the select input signal.

Figure 4.17: The block diagram of MUX with n data sources of b bits wide
and s bits wide select line

EXAMPLE 4.6: 2:1 MUX

A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to

one input of an AND gate. Selection lines S are decoded to select a particular AND gate.
The truth table for the 2:1 mux is given in below table 4.6.

Table 4.6: The truth table for the 2:1 mux

S Y
0 A
1 B

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Figure 4.18: A 2 to 1 line multiplexer

 Design of a 2:1 Mux

To derive the gate level implementation of 2:1 mux we need to have truth table as shown in
figure. And once we have the truth table, we can draw the K-map as shown in Figure 4.19,
for all the cases when Y is equal to '1'.

Combining the two 1' as shown in figure, we can drive the output y as shown below
Y = A.S' + B.S

Table 4.7: Truth Table of 2:1 mux

B A S Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

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Figure 4.19: Kmaps for the 2:1 mux

Figure 4.20: Circuit of a 2:1 Mux

EXAMPLE 4.7: 4:1 MUX

Figure 4.21: Circuit of a 4:1 Mux

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Table 4.8: Truth Table of 4:1 mux

4.5 Demultiplexer.

The opposite of the multiplexer circuit, logically enough, is the demultiplexer. This
circuit takes a single data input and one or more address inputs, and selects which of
multiple outputs will receive the input signal. The same circuit can also be used as a
decoder, by using the address inputs as a binary number and producing an output signal on
the single output that matches the binary address input. In this application, the data input
line functions as a circuit enabler. If the circuit is disabled, no output will show activity
regardless of the binary input number.

Figure 4.22: A one-line to two-line decoder/demultiplexer.

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EXAMPLE 4.8: A one-line to four-line demultiplexer

Figure 4.23: A one-line to four-line demultiplexer

Table 4.9: Truth Table of a one-line to four-line demultiplexer

4.6 Comparator

A comparator is a digital circuit that examines the binary data on two sets of inputs.
By using a combinational logic gates, design a 2-bit comparator, which can compare
between 2 numbers (2-bit each), as shown in Figure 4.24.

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EXAMPLE 4.9: Design a 2-bit comparator

A1 F2 (A > B)
A0 combinational
F1 (A < B)
B1 logic
B0 F0 (A = B)

Figure 4.23: A 2-bit comparator

• Obtain the truth table.

• Find the equation for the output (either by using Boolean algebra or Karnaugh
map).
• Draw the circuit.

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