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Storage Components
7-1
Registers A register can be viewed as a bitwise extension of a FF. The simplest of the storage components: inputs, outputs, and a clock signal.
c Cheng-Wen Wu, Lab for Reliable Computing (LaRC), EE, NTHU
2005
7. Storage Components
7-2
All the FFs are driven by the common clock signal. Registers are readily available as MSI circuits, it becomes convenient at times to employ a register as part of the sequential circuit. The combinationalcircuit part of the sequential circuit can be implemented by any of the methods discussed in Chapters 4 & 5. D-FFs are normally used for registers. The register may be enhanced by asynchronous Preset and Clear (Reset) signals, which are not controlled by the clock signal.
I3 I 2 I 1 I 0 Register Q3 Q 2 Q1 Q0
I3
I2
I1
I0
D3
Q3
D2
Q2
D1
Q1
D0
Q0
Clk
Q3
Q2
Q1
Q0
2005
7. Storage Components
7-3
I3
I2
I1
I0
preset D3 Q3 D2 Q2 D1 Q1 D0 Q0
clear Clk
Q3
Q2
Q1
Q0
2005
7. Storage Components
7-4
* To be able to control when the data will be entered into a register, and for how long it will be stored there before being sent to the output, we add the Load (Enable) input to form a parallel-load register.
Present state Load Next state Q3 Q2 Q1 Q0 No change I
3
Load
I3 I 2 I 1 I 0 Register Q3 Q 2 Q1 Q0
0 1
I3
I2
I1
I0
1 0 Selector
1 0 Selector
1 0 Selector
1 0 Selector
Load
D3
Q3
D2
Q2
D1
Q1
D0
Q0
Clk
Y3
Y2
Y1
Y0
2005
7. Storage Components
7-5
Shift Registers * A shift register can shift the stored data right and/or left.
Present state Shift Next state Q3 Q2 Q1 Q0 No change IL Q3 Q2 Q1
Shift
IL Shift Register Q 3 Q 2 Q1 Q0
0 1
1 0 Selector
1 0 Selector
1 0 Selector
1 0 Selector
Shift
D3
Q3
D2
Q2
D1
Q1
D0
Q0
Clk
Y3
Y2
Y1
Y0
Next state Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 I
3
0 0 0 1 1 0 1 1
Q2 Q1 Q0 I R IL Q3 Q2 Q1
S1 S0 D3 Q3 D2 Q2 D1 Q1 D0 Q0
Clk
Y3
Y2
Y1
Y0
2005
7. Storage Components
7-6
Counters * A counter is a special type of register that counts upward, downward, or in any prespecied sequence.
E Clear E
Counter
Qi C i
C i+1 Di
Q3 Q 2 Q1 Q0
0 1
0 0 1 1
0 1 0 1
0 0 0 1
0 1 1 0
C2
C1
C0
HA
HA
HA
HA
D3
Q3
D2
Q2
D1
Q1
D0
Q0
Clear Clk
Output carry
Q3
Q2
Q1
Q0
Qi C i
C i+1 Di
0 1 1
X 0 1
Q3 Q 2 Q1 Q0
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 1 0 1 0 0
0 1 1 0 0 1 1 0
C2
C1
C0
HAS
HAS
HAS
HAS
D3
Q3 Q 3
D2
Q2
Q2
D1
Q1 Q1
D0
Q0 Q0
Clear Clk
Output carry
Q3
Q2
Q1
Q0
2005
7. Storage Components
7-7
0 0 0 1
0 1 1 X
X 0 1 X
I0
D E
HAS
1 0 Selector
HAS
1 0 Selector
HAS
1 0 Selector
HAS
1 0 Selector
Load
D3
Q3
Q 3
D2
Q2 Q2
D1
Q1 Q1
D0
Q0 Q0
Clk
Output carry
Y3
Y2
Y1
Y0
2005
7. Storage Components
7-8
Selector
D E Load
I3 I 2 I 1 I 0 Up/Down Counter Q3 Q 2 Q1 Q0
"0"
D E Load
I3 I 2 I 1 I 0 Up/Down Counter Q3 Q 2 Q1 Q0
Asynchronous Counter * An asynchronous counter counts without an incrementer or decrementerits FFs are not clocked by the same signal. Counting without an incrementer/decrementer is achieved by toggling each FF at half the frequency of the preceding FF. FF changes state only half as often as FF . FF changes state only when FF goes from 1 to 0, but not from 0 to 1. A T-FF is very convenient for such an asynchronous counter design. The counting frequency (speed) will be limited by the number of FFs due to the linear growth of the clock-to-output delay. To speed up the counting process, we can use the mixed-mode counter.
2005
7. Storage Components
7-9
E
Asyn. Counter
Clear
Q3 Q 2 Q1 Q0
T3
Q3
Q 3
T2
Q2 Q2
T1
Q1 Q1
T0
Q0 Q0
FF 3
Clear Clk
FF 2
FF 1
FF 0
Q3
Q2
Q1
Q0
Clk
Q3
Q2
Q1
Q0
t0
t1
t2
t3
t4
t5
t6
t7
2005
7. Storage Components
Enable E
Asyn. Counter
7-10
E
Asyn. Counter
Q3 Q 2 Q1 Q0
Clear
Q3 Q 2 Q1 Q0
E
Syn. Counter
Q3 Q 2 Q1 Q0
Clear
Q3 Q 2 Q1 Q0
Register Files * A register le has registers of FFs each. $ The registers are arranged as a 2-dimensional array of register-le cells (RFCs). $ In addition, it has read/write decoders and output driving logic. $ Writing is controlled by the Write-Enable (WE) signal. At any time, we can write into only one register (row), unless it has multiple write ports. $ Reading is controlled by the Read-Enable (RE) signal. At any time, we can read from only one register, unless it has multiple read ports. $ Reading from and writing into the same register at the same time normally is not allowed.
2005
7. Storage Components
7-11
The primary advantage of a register le is regularity, which reduces routing (wiring) complexity.
I Write select n Input Clk D Q Output WA WE m n RA RE
RF
2n
X m
RFC
Read select
Clk m O
RFC
RFC
RFC
RFC
RFC
WA1 WA 0 2
RFC
RFC
RFC
1
RA
RE
WE 3
RFC
RFC
RFC
RFC
2
RFC
2to4 write decoder
RFC
RFC
RFC
3
O3
O2
O1
O0
Figure 10: Register le with 1 write port and 1 read port [Gajski].
2005
7. Storage Components
7-12
RF
2 x m n n
RFC
Read select (port A) Read select (port B)
Clk m A B m
REB
RFC
RFC
RFC
RFC
RFC
RFC
RFC
RFC
1 1
RFC
RFC
RFC
RFC
2 2
RFC
2to4 write decoder
RFC
RFC
RFC
3 3
A3 B3
A2B2
A1 B1
A0 B0
Figure 11: Register le with 1 write port and 2 read port [Gajski].
2005
7. Storage Components
7-13
Random Access Memories (RAMs) * A RAM is organized as an array of rows with bits stored in each row. The size of the RAM is bitsit has address lines, input data lines, and output data lines (see Fig. 12). The input data lines can be the same with the output data lines, i.e., the data lines can be bidirectional. For a commodity RAM,
* A memory cell (MC) can be considered as a clocked D latch with an AND gate and an output driver (see Fig. 13(a)). $ For a static RAM (SRAM), MC is constructed by 6 transistors, using cross-coupled inverters to serve as a latch, and implementing the input AND gate and the output driver with one transistor each. $ For a dynamic RAM (DRAM), MC is constructed by only 1 transistor. The latch is implemented by a capacitor. It needs to be refreshed periodically. It has high density (therefore low cost). * The RAM also has a Chip-Select ( input (see Fig. 13(b)).
* Both SRAM and DRAM are volatile memories, i.e., their content is lost if the power is shut down. $ ROM, PROM, EPROM, EEPROM, and ash memories are nonvolatile. * The delay time from address input to data output ( memory access time.
$ The address/data setup time and hold time are shown in Fig. 14. * We can connect several memory chips to get one of longer words (Fig. 15), or connect several memory chips to get one with more words (Fig. 16).
2005
7. Storage Components
7-14
Memory content
0 ... 0 0 0 0 ... 0 0 1 0 ... 0 1 0 0 ... 0 1 1 0 ... 1 0 0 0 ... 1 0 1 0 ... 1 1 0 0 ... 1 1 1 1 ... 1 1 0 1 ... 1 1 1 ...
n n
0 1 2 3 4 5 6 7 2 2 2 1 ...
0 1 1 ... 0 1 0 0 0 1 1 ... 0 1 0 0 1 0 1 ... 1 1 0 0 1 0 1 ... 0 0 0 1 0 1 1 ... 0 1 0 1 0 1 0 ... 0 1 0 1 1 1 0 ... 0 0 1 1 1 0 1 ... 0 0 0 1 0 0 0 ... 0 0 1 0 1 1 1 ... 0 1 1 0
m bits
...
. . .
Im1 . . . I1 I0 A n1 A n1
. . .
A1 A0 CS RWS
. . . 2
n
. . .
x m RAM
A1 A0 CS RWS
. . . 2
n
x m RAM
Om1 . . . O1 O0
. . .
. . .
2005
7. Storage Components
7-15
Row select
Input
D C
Output
MC
Write enable
MC
MC
MC
MC
1 A1 A0 2
MC
MC
MC
MC
MC
MC
MC
MC
MC
MC
MC
MC
IO3
IO 2
IO1
IO0
2005
7. Storage Components
RWS CS
7-16
Address
Valid address
Access time
Output holdtime t2 t3 t4 t5
t0
t1
CS
Address
Valid address
t0
t1
t2
2005
7. Storage Components
7-17
Input bus 32
14 A I A CS RWS O CS RWS
I A M
3
I A M
2
I A M
1
CS RWS O
CS RWS O
CS RWS O
32 Output bus
Figure 15: A
RAMs [Gajski].
2005
7. Storage Components
7-18
RWS
Input bus
2
2to4 Decoder 3 2 1 0
14
I A CS RWS O M
0
I A CS RWS O M
1
I A CS RWS O M
2
I A CS RWS O M
3
Output bus
Figure 16: A
RAMs [Gajski].
2005
7. Storage Components
7-19
*Push-Down Stacks * A push-down stack (or simply stack) is a memory component with limited accessdata can be accessed through only one location (i.e., the top of the stack). $ When data is to be stored, it is pushed on the stack and stays on top of others. $ When data is to be fetched, it has to be in the top position before it can be popped out of the stack. * A stack can be implemented by shift registers, with an up-down counter to detect full/empty stack as shown in Fig. 18. * It can also be implemented by a RAMless expensive for a large stack, but need two pointers (implemented by counters) as shown in Fig. 19.
45 45
34 23 empty empty
45 34 23 empty
34 23 empty empty
2005
7. Storage Components
7-20
Counter controls D E
Counter outputs Q 2 Q1 Q0
Empty
Full
X 0 1
0 1 1
X 0 1
0 1 1
0 1 1
0 1 0
X 0 1
0 1 1
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
1 0 0 0 0
0 0 0 0 1
"0" Reset S1 S0
IL SRwPL IR
...
IN m1 Reset S1 S0 Push/Pop
IL
Reset
...
Q 3 Q2 Q1 Q 0 OUT0
"0"
IR
...
SRwPL
Q 3 Q2 Q1 Q 0
2005
7. Storage Components
7-21
0 1 2
Top1 Top
Push/Pop Enable
Push/Pop
Enable
X 0
0 1 1
X 0 1
0 1 1
X 1 0
0 1 1
0 1 0
X 0 1
0 1 1
D E Reset Reset
Top
D E Set
Top1
Push/Pop
1 Selector
0 1K RAM A CS RWS
Enable
Control logic
2005
7. Storage Components
7-22
*First-in-First-out Queue * A rst-in-rst-out (FIFO) queue (or simply queue or FIFO) is a memory component with limited accessdata can be written through only the head (front) of the queue and read (and removed) through only the tail (back) of the queue. * A queue can be implemented by shift registers, with an up-down counter to detect full/empty queue as shown in Fig. 21. * It can also be implemented by a RAMless expensive for a large queue, but need two pointers (implemented by counters) as shown in Fig. 22.
45
empty empty 34 23
empty 45 34 23
empty empty 45 34
23
(a) Queue content (b) Queue content before 45 is stored after 45 is stored
Figure 20: FIFO queue operations [Gajski].
2005
7. Storage Components
7-23
Read/Write Enable
Read/Write Enable
S1 S 0
X 0 1
0 1 1
X 0 1
0 1 1
0 0 1
0 0 0
X 1 0
0 1 1
IR
2 1 0 Selector
Read/ Write
Reset S1 S0
IL
IR
SRwPL Q 3 Q2 Q1 Q 0
2 1 0 Selector
...
OUTm1 Full Empty
IN
m1
Reset
Output logic
S0
S1
S0
S1
...
Q 3 Q2 Q1 Q 0 OUT0
...
...
2005
7. Storage Components
7-24
Front
Read/Write Enable
Read/Write Enable
X
Back
0 1 1
X 0 1
0 1 1
X 1 0
0 1 1
X 0 1
0 1 0
0 0 1
0 1
E Reset Clk
1
Front
E Reset
Back
10
10
1 Selector
0 1K RAM
Enable Read/Write
(d) Schematic
2005
7. Storage Components
7-25
Simple Datapaths Datapaths are used in all standard CPU and ASIC implementations to perform complex numerical computation or data manipulations; a datapath consists of temporary storage in addition to arithmetic, logic, and shift units. Example 1 Assume we want to perform the summation of 100 numbers: We can use the datapath as shown in Fig. 23 to implement the following algorithm: sum=0; for(i=1; i<=100; i++) sum=sum+x[i];
Input O
1 Selector
7 6 5
M S1 S0
A ALU
4 3 2 1
Clk
S1 S0
IL IR Accumulator
6
ALU controls
4
Shift values
0
Out enable
Accumulator controls
2005
7. Storage Components
Inport
7-26
19
1 Selector
0 M S1 S 0 ALU Operations
1618 15
Clk
WA WE
8x m Register File
1214 11 810 7 6 5 4
3 3
RAA REA
RAB REB
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
M S1 S0
S 2 S1 S 0
Shift Operations
"0" IL
Shifter
"0" IR
3 2 1
S2 S1 S0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
pass pass not used not used shift left rotate left shift right rotate right
Result Bus
Outport
18 17 16 15
Write address
14 13
12 11 10
0
OE
Read address A
Read address B
ALU operation
Shifter operation
2005
7. Storage Components
7-27
1. Data := Inport 2. Ocount := 0 3. Mask := 1 while Data := 0 repeat 4. Temp := Data AND Mask 5. Ocount := Ocount + Temp 6. Data := Data >> 1 end while 7. Outport := Ocount (a) Basic algorithm for ones count Control Words 1 2 3 4 5 6 7
Write address Read address A Read address B
IE
ALU operation
Shifter operation
OE
1 0 0 0 0 0 0
R1 R3 R2 R4 R3 R1 none
X 0 0 R1 R3 R1 R3
X 0 X R2 R4 0 0
0 0 0 0 0 0 1
2005