Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes

!M" The main aim of the project is to design and develop #Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes$% &'() C(" In a recent paper, a method was proposed to accelerate the majority logic decoding of difference set low density parity check codes. This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, this increases the memory access time. The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Since most words in a memory will be error free, the average decoding time is greatly reduced. In this brief, we study the application of a similar technique to a class of !uclidean geometry low density parity check "!# $%&'( codes that are one step majority logic decodable. The results obtained show that the method is also effective for !# $%&' codes. !)tensive simulation results are given to accurately estimate the probability of error detection for different code si*es and numbers of errors.

K.Aravind Reddy (Director) 9652926926, 9640648

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Fig+ Serial one step majority logic decoder for the !# $&%' code.

(ools" ,ilin) -..i IS!, /odelsim 0.1c. ,,lication d-antages" The objective is to reduce the decoding time by stopping the decoding process when no errors are detected. This project e)tend the ones recently presented for %S $%&' codes, making the modified one step majority logic decoding more attractive for memory applications. The designer now has a larger choice of word lengths and error correction capabilities.
K.Aravind Reddy (Director) 9652926926, 9640648 Cell No:

)eferences" 2. '. 3aumann, 42adiation induced soft errors in advanced semiconductor technologies,5 I!!! Trans. %evice /ater. 2eliab., vol. 6, no. 7, pp. 789: 790. /. ;. 3ajura, <. 3oulghassoul, 2. =aseer, S. %as#upta, ;. F.>itulski, ?. Sondeen, S. %. Stansberry, ?. %raper, $. >. /assengill, and ?. =. %amoulakis, 4/odels and algorithmic limits for an !'' based approach to hardening sub 988 nm S2;/s,5 I!!! Trans. =ucl. Sci., vol. 61, no. 1, pp. -76:-16. 2. =aseer and ?. %raper, 4%!' !'' design to improve memory reliability in sub 988 nm technologies,5 &roc. I!!! I'!'S, pp. 6@0:6@-. S. #hosh and &. %. $incoln, 4%ynamic low density parity check codes for fault tolerant nano scale memory,5 presented at the Foundations =anosci. "F=;=A(, Snowbird, Btah. S. #hosh and &. %. $incoln, 4$ow density parity check codes for error correction in nanoscale memory,5 S2I 'omputer Science $ab., /enlo &ark, ';, Tech. 2ep. 'S$ 8C87.

K.Aravind Reddy (Director) 9652926926, 9640648

Cell No: