Constant Delay Logic Style

AIM: The main aim of the project is to design Constant Delay Logic Style.

(ABSTRACT)
A constant delay (CD) logic style is proposed in this paper, targeting at full-custom high-speed applications. The CD characteristic of this logic style regardless of the logic type ma es it suita!le in implementing complicated logic e"pressions such as addition. CD logic e"hi!its a uni#ue characteristic $here the output is pree%aluated !efore the inputs from the preceding stage is ready. This feature offers performance ad%antage o%er static and dynamic domino logic styles in a singlecycle multistage circuit !loc . &e%eral design considerations including timing $indo$ $idth adjustment and cloc distri!ution are discussed. 'sing ()-nm general-purpose C*+& technology, the proposed logic demonstrates an a%erage speed up of ,-. and )(. o%er static and dynamic domino logic, respecti%ely, in fi%e different logic gates. &imulation results of /-!it ripple carry adders sho$ that CD logic is 0,. and 10. faster than the static and dynamic-!ased adders, respecti%ely. CD logic also demonstrates 0,. speedup and (-. (11.) energydelay product (2D3) reduction from static logic at 455. (45.) data acti%ity in 01!it carry loo ahead adders. 6or /-!it 7allace tree multiplier, CD logic achie%es a similar speedup $ith at least )5. 2D3 reduction across all data acti%ities. Proposed Architecture:

V.Mallikarjuna (Project manager)

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8n this architecture delay has !een reduced !y using constant delay logic for ripple carry adder . 6urther $e can apply lo$ po$er techni#ues to reduce static po$er. Ad antage: CD logic9s ad%antages in terms of delay and 2D3 $ere also demonstrated in /-!it 7allace tree multipliers. Compared to 01-!it adders, CD logic achie%es a similar delay impro%ement, !ut has an e%en !etter 2D3 reduction, primarily !ecause the final adder $hich ma es up the critical path of the multiplier is a relati%ely small circuit !loc of the o%erall circuitry. At 1).:, CD logic is )1, 1), and 0;. more 2D3-efficient than static, dynamic, and pseudo-n*+& logic, respecti%ely . BL!C" DIA#RAM:

V.Mallikarjuna (Project manager)

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Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

T!!LS< hspice=%A-155/.50, t-spice R$%$R$&C$: >4? @. Aimmermann and 7. 6ichtner, Bo$-po$er logic styles< C*+& %ersus pass-transistor logic, 8222 C. &olid-&tate Circuits, %ol. 01, no. ;, pp. 45;,D45,5, Cul. 4,,;.

V.Mallikarjuna (Project manager)

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Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

>1? E. Foncal%es and G. De *an, E+@A< A race free dynamic C*+& techni#ue for pipelined logic structures, 8222 C. &olid-&tate Circuits, %ol. 4/, no. 0, pp. 1(4D 1((, Cun. 4,/0. >0? C. Bee and 2. &Heto, Aipper C*+&,8222 Circuits &yst. *ag.,%ol.1, no. 0, pp. 45D4(, *ay 4,/(. >-? @. @afati, &. 6a hraie, and I. &mith, A 4(-!it !arrel-shifter implemented in data-dri%en dynamic logic (D0B),8222 Trans. Circuits &yst.8, @eg. 3apers, %ol. )0, no. 45, pp. 14,-D1151, +ct. 155(. >)? 6. 6rustaci, *. BanuHHa, 3. Aicari, &. 3erri, and 3. Corsonello, Bo$ po$er split-path data-dri%en dynamic logic, Circuits De%. &yst. 82T, %ol. 0, no. (, pp. 050D041, Dec. 155,

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &