DESIGN AND IMPLEMENTATION OF REED SOLOMON CODE USED ON SMSA IN FPGA

By RAMAMOORTHY.S A PROJECT REPORT-PHASE II Submitted to the FACULTY OF INFORMATION& COMMUNICATION ENGINEERING In partial fulfillment of the requirements for the award of the degree Of MASTER OF ENGINEERING IN APPLIED ELECTRONICS

ANNA UNIVERSITY CHENNAI 600 025 JULY, 2013 ANNA UNIVERSITY: CHENNAI 600 025

BONAFIDE CERTIFICATE Certified that this project titled DESIGN AND IMPLEMENTATION OF REED SOLOMON CODE USED ON SMSA IN FPGA is the

bonafide work of RAMAMOORTHY.S (Reg.NO:411911401016) who carried out the research under my supervision. Certified further, that to the best of my knowledge the work reported herein does not from part of any other project report or dissertation on the basis of which a degree or award was conferred on an earlier occasion on this or any other candidate.

SIGNATURE Mrs.V.ANITHA M.E., SUPERVISOR, ASSISTANT PROFESSOR, DEPT OF ECE, ShriAndalAlagar College of Engg, Mamandur-603 111,

SIGNATURE Mr.A.RAJAN M.Tech., HEAD OF THE DEPARTMENT, ASSISTANT PROFESSOR, DEPT OF ECE, ShriAndalAlagar College of Engg, Mamandur-603 111,

Submitted to project and viva examination held on

INTERNAL EXAMINER

EXTERNAL EXAMINER

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ABSTRACT In the present world, communication has got many applications such as telephonic conversations etc. in which the messages are encoded into the communication channel and then decoding it at the receiver end. During the transfer of message, the data might get corrupted due to lots of disturbances in the communication channel. So it is necessary for the decoder tool to also have a function of correcting the error that might occur. Reed Solomon codes are type of burst error detecting codes which has got many applications due to its burst error detection and correction nature. My project Non Binary codes are robust to the simplified min sum algorithm has been proposed. Based on the SMSA, a highthroughput RS decoder is designed. Increasing the parallelism and throughput of decoder are the advantage of the proposed system. The main idea of the RS decoder is to reduce the computational complexity of the design. RS decoder can be used to find the exact solution first, the design increases the parallelism and throughput of the decoder by three to four times. The implementation results for the decoder show high throughput of 64 Mbps at 15 iterations. And design saves memory usage by 38% to76%. Third, this design shows 2.64 area efficiency improvements. Key point: SMSA, LDPC-Decoder, RS-Decoder, FPGA
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ACKNOWLEDGEMENT I submit our sincere heart-felt thanks to our beloved chairperson Mrs.PRREMALATHAVIJAYAKANT and our secretary cum

correspondent Mr.L.K.SUDHISH for being provided good facilities and infrastructure to complete our project. I would like to express our deep sense of gratitude to our respected principal Dr.R.KARTHIKEYAN for his guidance and motivation. I immensely thank Mr.A.RAJAN, head of the department, electronics and communication engineering for constant guidance and motivate ideas through this project work. I also thank our project coordinator Mr.T.R.GANESH BABU, assistant professor, department of ECE for his valuable suggestion which helped us to complete the project successfully. And I also express our sincere thanks to our project guide Mrs.V.ANITHA, assistant professor, department of ECE for guidance. Last but not least we extend our sincere thanks to all the teaching and non teaching staff members who have contributed their ideas for the betterment of the project.

TABLE OF CONTENTS CHAPTER NO TITLE ABSTRACT ACKNOWLEDGEMENT LIST OF FIGURES LIST OF TABLES LIST OF ABBREVIATIONS 1. INTRODUCTION
1.1 OVERVIEW 1.2 ERRORS AND METHODS 1.2.1 AUTOMATIC REPEAT REQUEST 1.2.2 FORWARD ERROR CORRECTION 1.3 ERROR CONTROL CODING

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1 3 3 4 5

1.4 CLASSIFICATION OF FORWARD ERROR CORRECTION CODES 5 1.5 EFFICIENT IMPLEMENTATION OF APPLICATION PRIMITIVES 1.6 ADAPTIVE SYSTEM DESIGN AND SCHEDULING 6 6

2. LITERATURE SURVEY
2.1. LITERATURE SURVEY 2.2 EXISTING SYSTEM 2.3. DRAWBACKS

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7 9 10

3. LDPC CODER
3.1 INTRODUCTION TO LDPC 3.2 TURBO CODES 3.3 PERFORMANCE OF ERROR CORRECTING CODES 3.4 FORWARD ERROR CORRECTION 3.5 HOW IT WORKS 3.5.1 AVERAGING NOISE TO REDUCE ERRORS 3.5.2 TYPES OF FEC 3.5.3 CONCATENATED FEC CODES FOR IMPROVE RFORMANCE 3.6 LOW-DENSITY PARITY-CHECK 3.7 CHANNEL CAPACITY
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11 12 12 12 13 14 14

15 15 16

3.8 BASIC COMMUNICATION MODEL 3.9 DECODING LDPC CODES

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4. REEDSOLOMON CODES
4.1OVERVIEW 4.2 PROPERTIES 4.3 REED SOLOMON ENCODING 4.4 REED SOLOMON DECODING 4.5 REED SOLOMON ERROR PROBABILITY 4.6 ARCHITECTURES FOR ENCODING AND DECODING REED-SOLOMON CODES

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25 25 25 25 27 27 28 28 28 28 28 30 30 30 32 33 34 35 35 36 36 38 38 38

4.6.1FINITE (GALOIS) FIELD ARITHMETIC 4.6.2GENERATOR POLYNOMIAL 4.7 ENCODER ARCHITECTURE 4.8 DECODER ARCHITECTURE 4.8.1 SYNDROME CALCULATION 4.8.2 FINDING THE SYMBOL ERROR LOCATIONS 4.8.3FIND AN ERROR LOCATOR POLYNOMIAL 4.9IMPLEMENTATION OF REED-SOLOMON DECODERS 4.9.1HARDWARE IMPLEMENTATION 4.9.2SOFTWARE IMPLEMENTATION 5. MATHEMATICAL THEOREMS 5.1 GROUPS 5.2 FIELDS 5 .2.1 GLAOIS FIELDS 5.2.2 PRIMITIVE POLYNOMIAL 5.3 SIMPLIFIED MIN-SUM DECODING ALGORITHM 5.3.1 THE EXTENDED MIN-SUM DECODING ALGORITHM 5.3.2 SIMPLIFIED MIN-SUM -DECODING ALGORITHM 5.4 BARREL SHIFTER 5.4.1 IMPLEMENTATION 6. HARDWARE AND SOFTWARE 6.1 HARDWARE DETAILS 6.1.1 FEATURES
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6.2 XILINX ISE TOOL FLOW 6.2.1 DESIGN ENTRY 6.2.2 SYNTHESIS 6.2.3 IMPLEMENTATION 6.2.4 VERIFICATION 6.2.5 DEVICE CONFIGURATION 7. RESULTS AND DISCUSSION 7.1 SYNTHESIS SUMMARY 7.2 INPUT 7.3 RTL SCHEMATIC 7.4 DEVICE UTILIZATION SUMMARY 7.5 SIMULATION RESULT 8. CONCLUSION AND FUTURE ENHANCEMENT 8.1 CONCLUSION 8.2 FUTURE WORK REFERENCES

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LIST OF FIGURES FIGURE NO 3.1 3.2 4.1 4.2 4.3 4.4 4.4 5.1 6.1 6.2 7.1 7.2 7.3 7.4 7.5 TITLE Basic Communication System Channel transition diagram for the BSC. Reed Solomon typical System Reed Solomon Codeword Graph between SNR and Bit error rate (BER) Architecture for a Systematic RS(255,249) Encoder Architecture for a Systematic RS(255,249) Decoder Permutation Network Implementation Flow ISE Simulation Flow Test Bench Input Waveform RTL Schematic View RTL Internal View Device Utilization Summary Simulation Output of RS Decoder PAGE NO 17 18 21 22 24 26 27 33 40 41 44 45 45 46 47

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LIST OF TABLES TABLE NO

3.1 4.1 5.1

TITLE
ERROR CORRECTION CODE RATE SOME PRIMITIVE POLYNOMIALS

PAGE NO
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LIST OF ABBREVIATIONS ADSL CD CER CN DRAM DSP DVD ECC EMSA FEC FPGA GEC HDSL LDPC MLC NB LDPC ASYMMETRIC DIGITAL SUBSCRIBER LINE COMPACT DISCS CODEWORD ERROR RATE CHECK NODE DYNAMIC RANDOM ACCESS MEMORY DIGITAL SIGNAL PROCESSING DIGITAL VIDEO DISCS ERROR CORRECTION CODING EXTENDED MIN-SUM ALGORITHM FORWARD ERROR CORRECTION FIELD PROGRAMMABLE GATE ARRAY GILBERT-ELLIOT CHANNEL HIGH-BIT-RATE DIGITAL SUBSCRIBER LINE LOW-DENSITY PARITY-CHECK CODE MULTI LEVEL CELL NON BINARY LOW-DENSITY PARITY-CHECK CODE QBC QC-LDPC QOS RS RTL SMSA SNR VLSI VN QUEUE-BASED CHANNEL QUASI-CYCLIC LOW-DENSITY PARITY-HECK QUALITY OF SERVICE REED SOLOMON CODE RESISTORTRANSISTOR LOGIC SIMPLIFIED MIN-SUM DECODING ALGORITHM SIGNAL-TO-NOISE RATIO VERY-LARGE-SCALE INTEGRATION VARIABLE NODE

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