ARM ARM Microprocessor Core

Architecture and The ARM Core as part

z ARM is a family of RISC z
Instruction Set architectures, which of a system-on-chip
share the same design
principles and a
common instruction set I/O
ARM
Ingo Sander z ARM does not Core Units

ingo@imit.kth.se manufacture the CPU

itself, but licenses it to Mem
DSP
other manufacturers to
integrate them into their
own system ASIC

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ARM Microprocessor Core ARM assembly language

z The ARM core is widely used in mobile phones, handheld z The assembly language reflects the instruction set (almost one to
organizers, and many other portable consumer devices one)
z Depending on the application ARM processors are available with z One instruction per line
e.g. z Labels provide names for addresses (usually in first column)
z Different Cache Sizes
z Instructions often start in later columns.
z Different Bus Widths
z Columns run to end of line
z Varying Clock Speeds
z Example:
z Different Versions use different architectures, e.g. MOV r1, #100000
z ARM 7: von Neumann Loop SUB r1, r1, #1 ; a wait loop
z ARM 9: Harvard BGE Loop
z The assembly programs are not affected by the underlying Cont …
architecture
Label Instructions Comment

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 Example
Von Neumann Architecture Von Neumann Architecture
z Consists of CPU and one single memory z Start Address: 0x100
z Memory holds instructions and data z Fetch Instruction
Addressbus ... ... Addressbus ... ...
0x100

Instructions

Instructions
Register 1 0x100: LDR R1, =0x400 Register 1 0x100: LDR R1, =0x400
Register 2 0x104: LDR R2, =0x404 Register 2 0x104: LDR R2, =0x404
Register 3 Databus 0x108: ADD R3, R2, R1 Register 3 Databus 0x108: ADD R3, R2, R1
0x10C: STR R3, =0x408 0x10C: STR R3, =0x408
Instruct. Register ... ... IR LDR R1, =0x400 ... ...
... ... LDR R1, =0x400 ... ...
Status Register Status Register
0x400: 2 0x400: 2

Data

Data
PC Read/Write 0x404: 3 PC 0x100 Read/Write 0x404: 3
0x408: ? 0x408: ?
ALU ... ... ALU R ... ...
Simple CPU Single Memory Simple CPU Single Memory
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Example Example
Von Neumann Architecture Von Neumann Architecture
z Execute Instruction z Increment Program Counter
z Fetch Instruction
Addressbus ... ... Addressbus ... ...
2 0x400 2 0x104
Instructions

Instructions
Register 1 0x100: LDR R1, =0x400 Register 1 0x100: LDR R1, =0x400
Register 2 0x104: LDR R2, =0x404 Register 2 0x104: LDR R2, =0x404
Register 3 Databus 0x108: ADD R3, R2, R1 Register 3 Databus 0x108: ADD R3, R2, R1
0x10C: STR R3, =0x408 0x10C: STR R3, =0x408
IR LDR R1, =0x400 ... ... IR LDR R2,
R1, =0x404
=0x400 ... ...
2 ... ... LDR R2, =0x404 ... ...
Status Register Status Register
0x400: 2 0x400: 2
Data

Data
PC 0x100 Read/Write 0x404: 3 PC 0x104 Read/Write 0x404: 3
0x408: ? 0x408: ?
ALU R ... ... ALU R ... ...
Simple CPU Single Memory Simple CPU Single Memory
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Example Example
Von Neumann Architecture Von Neumann Architecture
• Execute Instruction z Increment Program Counter
z Fetch Instruction
Addressbus ... ... Addressbus ... ...
2 0x404 2 0x108

Instructions

Instructions
Register 1 0x100: LDR R1, =0x400 Register 1 0x100: LDR R1, =0x400
Register 2 3 0x104: LDR R2, =0x404 Register 2 3 0x104: LDR R2, =0x404
Register 3 Databus 0x108: ADD R3, R2, R1 Register 3 Databus 0x108: ADD R3, R2, R1
0x10C: STR R3, =0x408 0x10C: STR R3, =0x408
IR LDR R2, =0x404 ... ... LDR R2,
IR ADD R3, =0x404
R2, R1 ... ...
3 ... ... ADD R3, R2, R1 ... ...
Status Register Status Register
0x400: 2 0x400: 2

Data

Data
PC 0x104 Read/Write 0x404: 3 PC 0x108 Read/Write 0x404: 3
0x408: ? 0x408: ?
ALU R ... ... ALU R ... ...
Simple CPU Single Memory Simple CPU Single Memory
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Example Example
Von Neumann Architecture Von Neumann Architecture
z Execute Instruction z Increment Program Counter
z Fetch Instruction
Addressbus ... ... Addressbus ... ...
2 2 0x10C
Instructions

Instructions
Register 1 0x100: LDR R1, =0x400 Register 1 0x100: LDR R1, =0x400
Register 2 3 0x104: LDR R2, =0x404 Register 2 3 0x104: LDR R2, =0x404
Register 3 Databus 0x108: ADD R3, R2, R1 Register 3 5 Databus 0x108: ADD R3, R2, R1
0x10C: STR R3, =0x408 0x10C: STR R3, =0x408
IR LDR R2,
ADD R3, =0x404
R2, R1 ... ... IR STR
LDR R3,
R2, =0x408
=0x404 ... ...
... ... STR R3, =0x408 ... ...
Status Register Status Register
0x400: 2 0x400: 2
Data

Data
PC 0x108 Read/Write 0x404: 3 PC 0x10C Read/Write 0x404: 3
0x408: ? 0x408: ?
ALU 5 ... ... ALU R ... ...
Simple CPU Single Memory Simple CPU Single Memory
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Example
Von Neumann Architecture The von Neumann architecture
z Increment Program Counter z Memory holds data, instructions.
z Fetch Instruction z Central processing unit (CPU) fetches
Addressbus ... ... instructions from memory.
2 0x408

Instructions
Register 1 0x100: LDR R1, =0x400
Register 2 3 0x104: LDR R2, =0x404 z Separate CPU and memory distinguishes
Register 3 5 Databus 0x108: ADD R3, R2, R1 programmable computer.
0x10C: STR R3, =0x408
IR LDR R3,
STR R2, =0x408
=0x404
5
...
...
...
...
z CPU registers help out: program counter
Status Register
0x400: 2 (PC), instruction register (IR), general-

Data
PC 0x10C Read/Write 0x404: 3

ALU W
0x408: 5? purpose registers, etc.
... ...
Simple CPU Single Memory
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Comparison
Harvard Architecture von Neumann and Harvard
z Consists of CPU and two single memories z Harvard allows two simultaneous memory
z In the original Harvard, one memory holds fetches.
instructions and the other data
Addressbus 1
z Harvard can’t use self-modifying code
... ...
Instruction
Memory

Register 1 0x100:
0x104:
LDR R1, =0x400
LDR R2, =0x404
z Most DSPs use Harvard architecture for
Register 2
Register 3
Databus 1 0x108:
0x10C:
ADD R3, R2, R1
STR R3, =0x408
streaming data:
Instruct. Register
... ...
z greater memory bandwidth
Status Register Addressbus 2
... z more predictable bandwidth
Memory

0x400: 2
Data

PC
Databus 2 0x404: 3 z Additional hardware, since two address and
0x408: ?
ALU ... ... data busses are needed
Simple CPU
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Programming Model:
Registers available in User Mode Generic Program Status Register
31 Flags 7 Control 0
z The ARM processor has 17 r0 r8 N Z C V ... Status Extension I F T ...
active registers in user mode r1 r9
z 16 data registers (r0-r15) r2 r10
Overflow Interrupt Thumb State
r3 r11 Negative
z 1 processor status registers Fast Interrupt
Zero Carry
r4 r12
z The registers r13-r15 have a
r5 r13 sp
special task z The cpsr (Current Program Status Register)
r6 r14 lr
z r13 is the stack pointer (sp) r7 r15 cp is used to monitor and control internal
z r14 is the link register (lr)
operations
z r15 is the program counter (pc) cpsr
not available
spsr in user mode!

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Addresses and Endianness Data Movement

z The ARM uses 32-bit addresses
z The ARM has a Load-Store architecture
z A Word is 32 bits (4 bytes) long
z An Address refers to a byte (not a word) z Data operands must be loaded into registers
z The ARM processor can be configured to use a little-endian or before they can be processed by an ALU
big-endian memory system
z Little-endian: lowest-order byte resides in the low-order bits of a z Data is moved between registers by means
word
z Big-endian: lower-order byte resides in highest bits of the word
of Move instructions
MOV r1, r2 ; r1 = r2
bit 31 bit 0 bit 31 bit 0 MOV r3, #1 ; r3 = 1
byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3
z Data is moved between memories by Load
little-endian big-endian and Store Instructions
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Single
Register-Memory Transfers Example for Load
z Data operands must be loaded into registers before Before:
they can be processed by an ALU r0 = 0x00000000
z The Load and Store instructions can be combined r1 = 0x00070000
with different addressing modes mem32[0x00070000] = 0x00000005
z The basic Load instruction is LDR (load word into
register), but there are variations that work on byte LDR r0, [r1]
(LDRB), halfword (LDRH) and signed bytes
(LDRSB) After:
z The basic Store instruction is STR (save word from r0 = 0x00000005
a register), variations are STRB och STRH r1 = 0x00070000

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Useful addressing modes: Useful addressing modes:

Preindexing Preindexing with Writeback
Before: Before:
r0 = 0x00000000 r0 = 0x00000000
r1 = 0x00007000 r1 = 0x00007000
mem32[0x00007000] = 0x00001000 mem32[0x00007000] = 0x00001000
mem32[0x00007004] = 0x00002000 mem32[0x00007004] = 0x00002000

Preindexing: LDR r0, [r1, #4] Preindexing with Writeback: LDR r0, [r1, #4]!

After:
After:
r0 = 0x00002000
r0 = 0x00002000
r1 = 0x00007004
r1 = 0x00007000

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Useful addressing modes: Multiple
Postindexing Register-Memory Transfers
Before: z Load-store multiple instructions are used to transfer
r0 = 0x00000000
multiple registers between memory and processor in
r1 = 0x00007000
mem32[0x00007000] = 0x00001000
a single instruction
mem32[0x00007004] = 0x00002000 z LDM (Load Multiple Registers)
z STM (Save Multiple Registers)
Postindexing: LDR r0, [r1], #4 z There are four addressing modes: IA (increment
after), IB (increment before), DA (decrement after),
After: DB (decrement before)
r0 = 0x00001000 z Be careful, which addressing mode you select,
r1 = 0x00007004
otherwise you may produce self-modifying code!
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Example
Load Store Multiple Instructions Stack Operations
Before: LDMDB r3!, {r0-r2} z The ARM architecture uses load-store multiple instructions to
r0 = 0x00000005
r1 = 0x00000006 pop and push data from and to the stack
After (2):
r2 = 0x00000007
r0 = 0x00000005 z Here you have to decide, if the stack is ascending (A) or
r3 = 0x00007000
r1 = 0x00000006 descending (D) and you use a full (F) or empty (E) stack.
STMIA r3!, {r0-r2} r2 = 0x00000007 Full Stack: Stack Pointer points at last used address
MOV r0,#1 r3 = 0x00007000 Empty Stack: Stack Pointer points at first empty address
MOV r1,#2 z STMFA sp!, {r5,r7} pushes registers r5 and r7 on an
MOV r2,#3 z Such pairs of Load-Store ascending stack and points after the instruction on the memory
After (1):
Multiple Instructions can be location where r7 is stored!
used to temporarily store z STMFA sp!, {r5,r7} is equivalent to STMIB r13, {r5,r7}
mem32[0x00007000] = 0x00000005 registers on the memory.
mem32[0x00007004] = 0x00000006
mem32[0x00007008] = 0x00000007
r3 = 0x0000700C

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Loading Constants Data Processing Instructions
z There are two pseudo-instructions to load z Data processing instructions manipulate data
constants within registers (Move, Arithmetic, Logical,
LDR r1, =0x7000 ; loads r1 with constant 0x7000 Comparison, Multiply)
ADR r2, label ; loads r2 with address for label
z If the S suffix is used the CPSR flags N, Z, C,
V are updated
z ADD r1, r2, r3 does not update CPSR
z ADDS r1, r2, r3 updates the CPSR

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Data Processing Instructions

and CPSR Data Processing Instructions
MOVS r1, #1 z Move: MOV, MVN
⇒ NZCV = 0000
z Arithmetic: ADD, ADC, SUB, SBC, RSB,
MOVS r2, #-1
RSC
⇒ NZCV = 1000

ADD r3, r2, r1 z Logical: AND, ORR, EOR, BIC

⇒ NZCV = 1000 z Comparison: CMP, CMN, TST, TEQ
ADDS r3, r2, r1 z Multiply: MUL, MLA, SMLAL, SMULL,
⇒ NZCV = 0110
UMULL, SMLAL, UMLAL

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Formats for data processing
instructions The Barrel Shifter
z Basic format z The barrel shifter allows an Rn Rm
SUB r3, r2, r1 ; r3 = r2 – r1 initial shift operation before it
z Immediate Operand enters the ALU Barrel
Shifter
SUB r3, r2, #3 ; r3 = r2 - 3 z Shift Operations: LSL,
Result N
z Preprocessing (Barrel-Shifter) LSR, ASR, ROR, RRX
SUB r3, r2, r1, LSL #1 ; r3 = r2 – (r1 * 2)
z Example: Arithmetic
Logic
z MOV r3, r4, LSL #3 Unit

;r3 = 8 * r4
Rd

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Branch Instructions Subroutines

z The branch instruction is used to change the flow of z The BL (Branch and Link) instruction can be
execution (if-then-else, for-loop, while-loop) used for subroutines, since it writes the
z Branch Instructions: B, BL, BX, BLX returnaddress to the link register
z Branches are often used with conditions (EQ, NE,
BL subroutine
CS, CC, MI, PL, VS, HI, LS, GE, LT,
...
GT, LE)
subroutine
z BEQ label ; Branch to label, if Z = 1
... ; code for subroutine
z The address label is stored in the instruction as a MOV pc, lr ; return by moving lr to pc
PC-relative offset and must be within 32MB of the
branch instruction
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Conditional Execution
z Not only branch instructions can be used with
conditions
z ADDEQ r4, r5, r6 is only executed if Z = 1
z Conditional Execution helps to design shorter
programs that do not use so much memory
Summary
z ARM is a family of microprocessor cores
z Load/store architecture
z Most instructions are RISCy, operate in
single cycle
z Some multi-register operations take longer
z All instructions can be executed conditionally

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