SL.

NO 1 2 3

NAME OF THE EXPERIMENT

PAGE NO 2-6 7-9 10-22

4 5 6 7 8

Simulation and realization of all logic gates. Write a HDL code to describe the functions of half adder, half subtractor and Full subtractor. Write HDL codes for the following combinational circuits. a) 2 to 4 decoder b) 8 to 3 encoder c) 8 to 1 multiplexer d) 4 bit binary to gray converter e) Multiplexer f) De-multiplexer g) 1 bit comparator h) 4 bit comparator Write HDL code to describe the functions of a full Adder Using three modeling styles. Write a model for 32 bit ALU using the schematic diagram shown below. Develop the HDL code for the following flip flop: T, D, SR, JK. Design 4 bit Binary, BCD Counter (Synchronous reset and Asynchronous reset and any sequence counters. Simulation and realization of Ring counter.

23-27 28-29 30-35 36-40 41-57

Experiment No. 1
AIM: Simulation and realization of all logic gates. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. Truth table with symbols

Black Box c d e f g h i

a LOGIC GATES

Truth table Basic gates: a 0 0 1 1 b 0 1 0 1 c 0 0 0 1 d 0 1 1 1 E 1 1 0 0 f 1 1 1 0 g 1 0 0 0 h 0 1 1 0 i 1 0 0 1

VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity gates is Port ( a,b : in std_logic; c,d,e,f,g,h,i : out std_logic); end gates; architecture dataflw of gates is begin c<= a and b; d<= a or b; e<= not a; f<= a nand b; g<= a nor b; h<= a xor b; i<= a xnor b; end dataflw;

VERILOG CODE module allgate ( a, b, y ); input a,b; output [1:6] y; assign y[1]= a & b; assign y[2]= a | b, assign y[3]= ~a , assign y[4]= ~(a & b), assign y[5]= ~(a | b), assign y[6]= a ^ b; endmodule

Procedure to view output on Model sim 1) After the program is synthesized create a Test bench, load the input. 2) Highlight the tbw file and click onto Modelsim Simulate behavioral model. 3

3) Now click the waveform and zoom it to view the result.

Modelsim Output

Output (c to i) PROCEDURE TO DOWNLOAD ONTO FPGA 1) Create a UCF (User Constraints File). 2) Click on UCF file and choose assign package pins option as shown in the figure below.

3)Assign the package pins as shown in fig below

3) save the file. 4) Click on the module and choose configure device option. 5) The following icon will be displayed.

6) Right click on the icon and select program option. 7) Program succeeded message will be displayed. 8) Make connections to main board and daughter boards( before configuring ) , give necessary inputs from DIP SWITCH and observe the output on LEDs. NET "a" LOC = "p74" ; NET "b" LOC = "p75" ; NET "c" LOC = "p84" ; NET "d" LOC = "p114" ; NET "e" LOC = "p113" ; NET "f" LOC = "p115" ; NET "g" LOC = "p117" ; NET "h" LOC = "p118" ; NET "i" LOC = "p121" ;

Repeat the above Procedure to all the Programs.

RESULT: The logic gates design has been realized and simulated using HDL codes.

Experiment No. 2
AIM: Write a HDL code to describe the functions of half adder, half subtractor and Full subtractor. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. (a) HALF ADDER TRUTH TABLE INPUTS A 0 0 1 1 B 0 1 0 1 OUTPUTS S 0 1 1 0 C 0 0 0 1 BASIC GATES

BOOLEAN EXPRESSIONS: S=A B C=A B VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HA is Port ( a, b : in std_logic; s, c : out std_logic); end HA; architecture dataflow of HA is begin s<= a xor b; c<= a and b; end dataflow; VERILOG CODE module ha ( a, b, s, c) input a, b; output s, c; assign s= a ^ b; assign c= a & b; endmodule

(b)HALF SUBTRACTOR TRUTH TABLE INPUTS A B 0 0 1 1 BASIC GATES 0 1 0 1 OUTPUTS D Br 0 1 1 0 0 1 0 0 BOOLEAN EXPRESSIONS: D=A B
_

Br = A B

VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity hs is Port ( a, b : in std_logic; d, br : out std_logic); end hs; architecture dataflow of hs is begin d<= a xor b; br<= (not a) and b; end dataflow;

VERILOG CODE module hs ( a, b, d, br) input a, b; output d, br; assign d= a ^ b; assign br= ~a & b; endmodule

(C)FULL SUBTRACTOR TRUTH TABLE INPUTS A 0 0 0 0 1 1 1 1 BASIC GATES B 0 0 1 1 0 0 1 1 Cin 0 1 0 1 0 1 0 1 BOOLEAN EXPRESSIONS: D= A B C
_ _

OUTPUTS D 0 1 1 0 1 0 0 1 Br 0 1 1 1 0 0 0 1

Br= A B + B Cin + A Cin

VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOG IC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity fs is Port ( a, b, c : in std_logic; d, br : out std_logic); end fs; architecture dataflw of fs is begin d<= a xor b xor c; br<= ((not a) and (b xor c)) or (b and c); end datafolw;

VERILOG CODE module fs ( a, b, c, d, br) input a, b, c; output d, br; assign d= a ^ b ^ c; assign br=(( ~a)& (b ^ c)) | (b & c); endmodule

RESULT:The half adder, half subtractor and full subtractor designs have been realized and simulated using HDL codes. 9

Experiment No. 3
AIM: Write HDL codes for the following combinational circuits. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. a) 2 TO 4 DECODER BLACK BOX 2 to 4 Decoder Y0 Y1 Y2 Y4

Sel 0 Sel 1 E

Truth Table of 2 to 4 decoder

E 1 1 1 1 0 Sel1 0 0 1 1 X Sel0 0 1 0 1 X Y3 0 0 0 1 0 Y2 0 0 1 0 0 Y1 0 1 0 0 0 Y0 1 0 0 0 0

DATA FLOW VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dec2_4 is port (a, b, en :in std_logic ; y0, y1, y2, y3:out std_logic); end dec2_4; architecture data flow of dec2_4 is begin y0<= (not a) and (not b) and en; y1<= (not a) and b and en; y2<= a and (not b) and en; y3<= a and b and en; end dataflow; 10 VERILOG CODE module dec2_4 (a,b,en,y0,y1,y2,y3) input a, b, en; output y0,y1,y2,y3; assign y0= (~a) & (~b) & en; assign y1= (~a) & b & en; assign y2= a & (~ b) & en; assign y3= a & b & en; end module

NET "e" LOC = "p74"; NET "sel<0>" LOC = "p75"; NET "sel<1>" LOC = "p76"; NET "y<0>" LOC = "p112"; NET "y<1>" LOC = "p114"; NET "y<2>" LOC = "p113"; NET "y<3>" LOC = "p115";

Simulation is done using Modelsim Waveform window : Displays output waveform for verification.

Output b) 8 TO 3 ENCODER WITH PRIORITY

i7Z3 8:3 Parity Encoder i0 Z1 Z0 enx V

en

Truth table
En 1 0 0 0 0 0 0 0 0 0 I7 X 1 1 1 1 1 1 1 1 0 I6 X 1 1 1 1 1 1 1 0 X I5 X 1 1 1 1 1 1 0 X X I4 X 1 1 1 1 1 0 X X X I3 X 1 1 1 1 0 x X X X I2 X 1 1 1 0 X X X X X I1 X 1 1 0 X X X X X X I0 X 1 0 X X X X X X X Z2 1 1 1 1 1 1 0 0 0 0 Z1 1 1 1 1 0 0 1 1 0 0 Z0 1 1 1 0 1 0 1 0 1 0 enx 1 1 0 0 0 0 0 0 0 0 V 1 0 1 1 1 1 1 1 1 1 11

VHDL CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity encoder8_3 is Port ( i : in std_logic_vector(7 downto 0); en : in std_logic; enx,V : out std_logic; z : out std_logic_vector(2 downto 0)); end enco2; architecture behavioral of encoder8_3 is begin

end behavioral ;

VERILOG CODE module enc8_3 (I, en, y, v); input [7:0]I; input en; output v; output [2:0]y; sig y; sig v; always @ (en, I) begin if(en= =0) v=0; else v=1; end if ( I[7]= =1 & en= =1) y=3b111; else if ( I[6]==1 & en==1) else if ( I[5]==1 & en==1) else if ( I[4]==1 & en==1) else if ( I[3]==1 & en==1) else if ( I[2]==1 & en==1) else if ( I[1]==1 & en==1) else if ( I[0]==1 & en==1) else y=3b000; end end module

y=3b110; y=3b101; y=3b100; y=3b011; y=3b010; y=3b001; y=3b000;

#PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "en" LOC = "p84"; NET "i<0>" LOC = "p85"; NET "i<1>" LOC = "p86"; NET "i<2>" LOC = "p87"; NET "i<3>" LOC = "p93"; NET "i<4>" LOC = "p94"; NET "i<5>" LOC = "p95"; NET "i<6>" LOC = "p100"; NET "i<7>" LOC = "p74"; NET "enx" LOC = "p112"; NET "V" LOC = "p114"; NET "z<0>" LOC = "p113"; NET "z<1>" LOC = "p115"; NET "z<2>" LOC = "p117"; 12

Output

c) 8 TO 1 MULTIPLEXER

a b c d e f g h sel(2 to 0)

8:1Mux

Truth table
Sel2 0 0 0 0 1 1 1 1 Sel1 0 0 1 1 0 0 1 1 Sel0 0 1 0 1 0 1 0 1 Z A B C D E F G H

13

VHDL CODE entity mux8_1 is port(I: in std_logic_vector (7 downto 0); S: in std_logic_vector (2 downto 0); en: in std_logic; y: out std_logic); end mux8_1; architecture behavioral of mux8_1 is begin process (I,s,en) is begin if en=1 then if S=000 then y<=I(0); elsif S=001 then y<=I(1); elsif S=001 then y<=I(2); elsif S=001 then y<=I(3); elsif S=001 then y<=I(4); elsif S=001 then y<=I(5); elsif S=001 then y<=I(6); else y<=I(7); end if; else y<=0; end if; end process; end mux8_1;

VERILOG CODE module mux8_1 input [7:0]I; output [2:0]S; output y; input en; reg y; always @(en,S,I,y); begin if (en= =1) begin if (s= =000 y=I[0]; else if (s==001) y=I[1]; else if (s==001) y=I[2]; else if (s==001) y=I[3]; else if (s==001) y=I[4]; else if (s==001) y=I[5]; else if (s==001) y=I[6]; else if (s==001) y=I[7]; end else y=0; end end endmodule

Output

14

d) 4-BIT BINARY TO GRAY COUNTER CONVERTER Black Box clk en rst 4 bit Binary to gray

q(3 downto 0)

Truth table Rst Clk 1 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

En 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0

G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

15

VHDL CODE entity bintogray is Port ( rst,clk : in std_logic; g : inout std_logic_vector(3 downto 0)); end bintogray; architecture Behavioral of bintogray is signal b: std_logic_vector( 3 downto 0); begin process(clk,rst) begin if rst='1' then b<="0000"; elsif rising_edge(clk) then b<= b+1; end if; end process; g(3)<= b(3); g(2)<= b(3) xor b(2); g(1)<= b(2) xor b(1); g(0)<= b(1) xor b(0); end Behavioral;

VERILOG CODE module b2g(b,g); input [3:0] b; output [3:0] g; xor (g[0],b[0],b[1]), (g[1],b[1],b[2]), (g[2],b[2],b[3]); assign g[3]=b[3]; endmodule

Binary to gray Output PACE: Start of Constraints generated by PACE #PACE: Start of PACE I/O Pin Assignments NET "b<0>" LOC = "p84"; NET "b<1>" LOC = "p85"; NET "b<2>" LOC = "p86"; NET "b<3>" LOC = "p87"; NET "g<0>" LOC = "p112"; NET "g<1>" LOC = "p114"; NET "g<2>" LOC = "p113"; NET "g<3>" LOC = "p115"; 16

e) MULTIPLEXER(4 TO 1) Black Box a b c d sel (1 to 0) 4:1 Mux Z

Truth Table
Sel1 0 0 1 1 Sel0 0 1 0 1 Z a b c d VERILOG CODE module mux4_1(I0,I1,I2,I3,s2,s1,y,en) input I0,I1,I2,I3,s2,s1,en; output y; assigny<=((~s2)&(~s1)&en&I0)| ((~s2)&(s1)&en&I1)|(s2&(~s1)&en&I2)|(s2&s1& en&I3); dataflow of mux1 is endmodule

VHDL CODE entity mux1 is Port ( en,I : in std_logic; sel:in std_logic_vector(1downto 0); y : out std_logic); end mux1; architecture begin z<= I0 when sel= "00" else I1 when sel= "01" else I2 when sel= "10" else I3; end dataflow;

Multiplexer Output

17

f) DE-MULTIPLEXER ( 1 TO 4)

Black Box

a en sel(1 downto 1) 1:4 Demux Y(3 downto 0)

Truth table
a 1 1 1 1 0 En 0 0 0 0 1 Sel1 0 0 1 1 X Sel0 0 1 0 1 X Y3 0 0 0 1 0 Y2 0 0 1 0 0 Y1 0 1 0 0 0 Y0 1 0 0 0 0

VHDL CODE entity demux is Port ( I,en : in std_logic; sel: in std_logic_vector(1 downto 0); y:outstd_logic_vector(3downto0)); end demux; architecture dataflow of demux is signal x: std_logic_vector( 1 downto 0); begin x<= en & a; y <="0001" when sel="00" and x="01" else "0010" when sel="01" and x="01" else "0100" when sel="10" and x="01" else "1000" when sel="11" and x="01" else "0000"; end dataflow;

VERILOG CODE module demux (s2,s1,I,en,y0,y1,y2,y3) input s2,s1,I,en; output y0,y1,y2,y3; assign y0=(~s2)&(~s1)& I& en; assign y1=(~s2)& s1& I& en; assign y2=s2&(~s1)& I & en; assign y3=s2& s1 & I & en; endmodule

18

output

NET "a" LOC = "p84"; NET "en" LOC = "p85"; NET "sel<0>" LOC = "p86"; NET "sel<1>" LOC = "p87"; NET "y<0>" LOC = "p112"; NET "y<1>" LOC = "p114"; NET "y<2>" LOC = "p113"; NET "y<3>" LOC = "p115";

Output

g) 1-BIT COMPARATOR (STRUCTURAL)

Black Box

a 1bit Comparat or

L E G

19

Truth table

A 0 0 1 1

B 0 1 0 1

L 0 1 0 0

E 1 0 0 1

G 0 0 1 0

VHDL CODE entity b_comp1 is port( a, b: in std_logic; L,E,G: out std_logic); end; architecture structural of b_comp1 is component not_2 is port( a: in std_logic; b: out std_logic); end component; component and_2 is port( a, b: in std_logic; c: out std_logic); end component; component xnor_2 is port( a, b: in std_logic; c: out std_logic); end component; signal s1,s2: std_logic; begin X1: not_2 port map (a, s1); X2: not_2 port map (a, s2); X3: and_2 port map (s1, b, L); X4: and_2 port map (s2, a, G); X5: xnor_2 port map (a, b, E); end structural;

VERILOG CODE module b_comp1 (a, b, L, E,G); input a, b; output L, E, G; wire s1, s2; not X1(s1, a); not X2 (s2, b); and X3 (L,s1, b); and X4 (G,s2, a); xnor X5 (E, a, b); end module

20

output NET "a" LOC = "p74" ; NET "b" LOC = "p75" ; NET "E" LOC = "p86" ; NET "G" LOC = "p85" ; NET "L" LOC = "p84" ;

1-BIT COMPARATOR (DATA FLOW) VHDL CODE entity bcomp is port( a, b: in std_logic; c, d, e: out std_logic); end bcomp; architecture dataflow of bcomp is begin c<= (not a) and b; d<= a xnor b; e<= a and (not b); end dataflow; VERILOG CODE module bcomp (a, b, c, d, e) input a, b; output c, d, e; assign c= (~a) & b; assign d= ~(a ^ b); assign e= a & (~b); end module

h) 4-BIT COMPARATOR Black Box a(3 to 0) 4bit Comparator b(3 to 0) x y z

21

VHDL CODE entity compart4bit is Port ( a,b : in std_logic_vector(3 downto 0); aeqb,agtb,altb: out std_logic); end compart4bit; architecture Behavioral of

VERILOG CODE module comp(a,b,aeqb,agtb,altb); input [3:0] a,b; output aeqb,agtb,altb; reg aeqb,agtb,altb; always @(a or b) begin aeqb=0; agtb=0; if(a==b) aeqb=1; else if (a>b) agtb=1; else altb=1; end endmodule

compart4bit is begin process (a,b) begin if a > b then aeqb<='1';agtb<=0;altb<=0; elsif a < b then agtb<='1';aeqb<=0;altb<=0; else altb<='1'; aeqb<=0; agtb<=0; end if ; end process; end Behavioral;

altb=0;

output Greater than

Equal to

Less than

RESULT: Combinational designs have been realized and simulated using H

22

Experiment No. 4
AIM: Write HDL code to describe the functions of a full Adder Using three modeling styles. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. DATA FLOW Black box

a b c FULL ADDER Sum

Cout

Truth table
INPUTS a 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 cin 0 1 0 1 0 1 0 1 OUTPUTS SUM 0 1 1 0 1 0 0 1 Cout 0 0 0 1 0 1 1 1

VHDL CODE entity fulladder is Port ( a,b,c : in std_logic; s,cout : out std_logic); end fulladr; architecture data of fulladr is begin sum<=a xor b xor cin; cout<= ( a and b) or ( b and cin) or ( cin and a); end data;

VERILOG CODE module fulladder ( a, b, c,s,cout) input a, b,c; output s, cout; assign s= a ^ b^c; assign cout= a & b & c; endmodule

23

BEHAVIORAL STYLE VHDL CODE entity fulladder beh is Port ( a,b,c : in std_logic; sum,carry : out std_logic); end fulladrbeh; architecture Behavioral of fulladrbeh is begin process( a,b,c) begin if(a='0' and b='0' and c='0') then sum<='0'; carry<='0'; elsif(a='0' and b='0' and c='1') then sum<='1'; carry<='0'; elsif(a='0' and b='1' and c='0') thensum<='1'; carry<='0'; elsif(a='0' and b='1' and c='1') thensum<='0'; carry<='1'; elsif(a='1' and b='0' and c='0') thensum<='1'; carry<='0'; elsif(a='1' and b='0' and c='1') thensum<='0'; carry<='1'; elsif(a='1' and b='1' and c='0') thensum<='0'; carry<='1'; else sum<='1'; carry<='1'; end if; end process; end Behavioral; VERILOG CODE module fulladd(cin,x,y,s,co); input cin,x,y; output s,co; reg s,co; always@(cin or x or y) begin case ({cin,x,y}) 3'b000:{co,s}='b00; 3'b001:{co,s}='b01; 3'b010:{co,s}='b01; 3'b011:{co,s}='b10; 3'b100:{co,s}='b01; 3'b101:{co,s}='b10; 3'b110:{co,s}='b10; 3'b111:{co,s}='b11; endcase end endmodule

24

STRUCTURAL STYLE VHDL CODE entity fullstru is Port ( a,b,cin : in std_logic; sum,carry : out std_logic); end fullstru; architecture structural of fullstru is signal c1,c2,c3:std_logic; component xor_3 port(x,y,z:in std_logic; u:out std_logic); end component; component and_2 port(l,m:in std_logic; n:out std_logic); end component; component or_3 port(p,q,r:in std_logic; s:out std_logic); end component; begin X1: xor_3 port map ( a, b, cin,sum); A1: and_2 port map (a, b, c1); A2: and_2 port map (b,cin,c2); A3: and_2 port map (a,cin,c3); O1: or_3 port map (c1,c2,c3,carry); end structural; VERILOG CODE module fa (x,y,z,cout,sum); input x,y,z; output cout,sum; wire P1,P2,P3; HA HA1 (sum(P1),cout(P2),a(x), b(y)); HA HA2 (sum(sum),carry(P3),a(P1),b(Z)); OR1 ORG (P2,P3, Cout); endmodule

25

Supporting Component Gates for Stuctural Full Adder

//and gate// library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity and2 is Port ( l,m : in std_logic; n : out std_logic); end and2; architecture dataf of and2 is begin n<=l and m; end dataf; //or gate// library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity or3 is Port ( p,q,r : in std_logic; s : out std_logic); end or3; architecture dat of or3 is begin s<= p or q or r; end dat; //xor gate// library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity xor3 is Port ( x,y,z : in std_logic; u : out std_logic); end xor3; architecture dat of xor3 is begin u<=x xor y xor z; end dat;

26

Full adder data flow i/o pins NET "a" LOC = "P74"; NET "b" LOC = "P75"; NET "cin" LOC = "P76"; NET "cout" LOC = "P84"; NET "sum" LOC = "P85";

Sum output

carry output

RESULT: Three modeling styles of full adder have been realized and simulated using HDL. codes.

27

Experiment No. 5
AIM: Write a model for 32 bit ALU using the schematic diagram shown below. COMPONENTS REQUIRED:FPGA/CPLD board, FRCs, jumper and power supply. OPCODE 1 2 3 4 5 6 7 8 9 10 11 ALU OPERATION A+B A-B A Complement A*B A and B A or B A nand B A xor B Right shift Left Shift Parallel load

Black box

A1(3 to 0) B1(3 to 0) ALU opcode (2 to 0) Zout (7 downto 0)

Truth table
Operation A+B A-B A or B A and B Not A A1*B1 A nand B A xor B Opcode 000 001 010 011 100 101 110 111 A 1111 1110 1111 1001 1111 1111 1111 0000 B 0000 0010 1000 1000 0000 1111 0010 0100 Zout 00001111 00001100 00001111 00001000 11110000 11100001 11111101 00000100

28

VHDL CODE entity alunew is Port( a1,b1:in std_logic_vector(3 downto 0); opcode : in std_logic_vector(2 downto 0); zout : out std_logic_vector(7 downto 0)); end alunew; architecture Behavioral of alunew is signal a: std_logic_vector( 7 downto 0); signal b: std_logic_vector( 7 downto 0); begin a<= "0000" & a1; b<= "0000" & b1; zout<= a+b when opcode ="000" else a-b when opcode ="001" else a or b when opcode ="010" else a and b when opcode ="011" else not a when opcode ="100" else a1 * b1 when opcode ="101" else a nand b when opcode ="110" else a xor b; end Behavioral;

VERILOG CODE module ALU ( a, b, s, en, y ); input signal [3:0]a, b; input [3:0]s; input en; output signal [7:0]y; reg y; always@( a, b, s, en, y ); begin if(en==1) begin case 4d0: y=a+b; 4d1: y=a-b; 4d2: y=a*b; 4d3: y={4 bww, ~a}; 4d4: y={4 d0, (a & b)}; 4d5: y={4 d0, (a | b)}; 4d6: y={4 d0, (a ^ b)}; 4d7: y={4 d0, ~(a & b)}; 4d8: y={4 d0, ~(a | b)}; 4d9: y={4 d0, ~(a ^ b)}; default: begin end end case end else y=8d0; end endmodule

RESULT: 32 bit ALU operations have been realized and simulated using HDL codes. 29

Experiment No. 6
AIM: Develop the HDL code for the following flip flop: T, D, SR, JK. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. T FLIPFLOP Black Box

t clk T ff rst

q qb

VHDL CODE entity tff is Port ( t,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end tff; architecture Behavioral of tff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process (clk) variable temp:std_logic:='0'; begin if rising_edge(clk) then if (t='1') then temp:=not temp; else temp:=temp; end if; end if; q<=temp;qb<=not temp; end process; end Behavioral;

VERILOG CODE module tff(t,clk,rst, q,qb); input t,clk,rst; output q,qb; reg q,qb; reg temp=0; always@(posedge clk,posedge rst) begin

if (rst==0) begin if(t==1) begin temp=~ temp; end else temp=temp; end q=temp;qb=~temp; end

endmodule

30

Truth table
Rst 1 1 1 0 T 0 1 X X Clk 1 1 No +ve edge X q q qb Previous state 0

Rising edge Output D FLIP-FLOP Black Box d D FF clk q qb

VHDL CODE entity dff is Port ( d,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end dff; architecture Behavioral of dff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process (clk) variable temp: std_logic; begin if rising_edge(clk) then temp:=d; end if; q<=temp;qb<=not temp; end process; end Behavioral;

VERILOG CODE module dff(d,clk,rst,q,qb); input d,clk,rst; output q,qb; reg q,qb; reg temp=0; always@(posedge clk,posedge rst) begin if (rst==0) temp=d; else temp=temp; q=temp; qb=~ temp ; end endmodule

31

Truth table
clk X 1 1 D 1 1 0 Q 1 1 0 qb 0 0 1

Output at rising edge NET "clk" LOC = "P18"; NET "d" LOC = "P74"; NET "q" LOC = "P84"; NET "qb" LOC = "P85"; SR FLIP FLOP Black Box clk s r rst pr q SR FF qb

Truth table
Rst 1 0 0 0 0 0 pr X 1 0 0 0 0 Clk X X 1 1 1 1 s X X 0 0 1 1 r X X 0 1 0 1 q 0 1 Qb 0 1 1 qb 1 0 Qbprevious 1 0 1

32

VHDL CODE entity srff is Port ( s,r,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end srff; architecture Behavioral of srff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process;

process(clk,rst) variable sr:std_logic_vector(1 downto 0); variable temp1,temp2:std_logic:='0'; begin sr:=s&r; if (rst ='0')then if rising_edge(clk) then case sr is when "01"=> temp1:='0'; temp2:='1'; when "10"=> temp1:='1'; temp2:='0'; when "11"=> temp1:='1'; temp2:='1'; when others=> null; end case; end if; else temp1:='0'; temp2:='1'; end if; q<=temp1;qb<=temp2; end process; end Behavioral;

VERILOG CODE module srff(s,r,clk,rst, q,qb); input s,r,clk,rst; output q,qb; reg q,qb; reg [1:0]sr; always@(posedge clk,posedge rst) begin sr={s,r}; if(rst==0) begin case (sr) 2'd1:q=1'b0; 2'd2:q=1'b1; 2'd3:q=1'b1; default: begin end endcase end else begin q=1'b0; end qb=~q; end

endmodule

S output

33

JK FLIPFLOP Black Box j k JK FF clk rst qb

VHDL CODE entity jkff is Port ( j,k,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end jkff; architecture Behavioral of jkff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clk,rst) variable jk:std_logic_vector(1 downto 0); variable temp:std_logic:='0'; begin jk:=j&k; if (rst ='0')then if rising_edge(clk) then case jk is when "01"=> temp:='0'; when "10"=> temp:='1'; when "11"=> temp:=not temp; when others=> null; end case; end if; else temp:='0'; end if; q<=temp; qb<=not temp; end process; end Behavioral;

VERILOG module jkff(j,k,clk,rst, q,qb); input j,k,clk,rst; output q,qb; reg q,qb; reg [1:0]jk; always@(posedge clk,posedge rst) begin jk={j,k}; if(rst==0) begin case (jk) 2'd1:q=1'b0; 2'd2:q=1'b1; 2'd3:q=~q; default: begin end endcase end else q=1'b0; qb=~q; end endmodule

34

Truth table
Rst 1 1 1 1 1 0 Clk 1 1 1 1 No+ve egde J 0 0 1 1 K 0 1 0 1 Q Previous 0 1 Qb Previous 0 Qb state 1 0 Q state 1

Output (when input 00 and rising edge) NET "clk" LOC = "p18"; NET "j" LOC = "p84"; NET "k" LOC = "p85"; NET "rst" LOC = "p86"; NET "q" LOC = "p112"; NET "qb" LOC = "p114";

RESULT: Flip-flop operations have been realized and simulated using HDL codes

35

Experiment No. 7
AIM: Design 4 bit Binary, BCD Counter (Synchronous reset and Asynchronous reset and any sequence counters. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. a) BCD COUNTER Black Box clk BCD counter q(3 downto 0)

rst

Truth table
Rst 1 0 0 0 0 0 0 0 0 0 Clk X 1 1 1 1 1 1 1 1 1 Q 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001

36

VHDL CODE entity bcd is Port ( clr,clk,dir : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0); tc : out STD_LOGIC); end bcd; architecture Behavioral of bcd is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) variable temp:std_logic_vector(3 downto 0); begin if(clr='1')then temp:="0000";tc<='0'; elsif rising_edge(clkd(21)) then if (dir='1') then temp:=temp+1; elsif(dir='0') then temp:=temp-1; end if; if(dir='1' and temp="1010") then temp:="0000"; tc<='1'; elsif(dir='0' and temp="1111") then temp:="1001"; tc<='1'; else tc<='0'; end if; end if; q<=temp; end process; end Behavioral;

VERILOG CODE module bcd(clr,clk,dir, tc, q); input clr,clk,dir; output reg tc; output reg[3:0] q; always@(posedge clk,posedge clr) begin if(clr==1) q=4'd0; else begin if (dir==1) q=q+1; else if(dir==0) q=q-1; if(dir==1 & q==4'd10) begin q=4'd0;tc=1'b1; end else if(dir==0 & q==4'd15) begin q=1'd9;tc=1'b1; end else tc=1'b0; end end endmodule

37

b) GRAY COUNTER Black Box clk en rst 4 bit Binary to gray

q(3 downto 0)

VHDL CODE entity gray is Port ( clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0)); end gray; architecture Behavioral of gray is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clr,clkd) variable temp:std_logic_vector(2 downto 0); begin if(clr='0') then if rising_edge(clkd(21)) then case temp is when "000"=> temp:="001"; when "001"=> temp:="011"; when "011"=> temp:="010"; when "010"=> temp:="110"; when "110"=> temp:="111"; when "111"=> temp:="101"; when "101"=> temp:="100"; when "100"=> temp:="000"; when others => null; end case; end if; else temp:="000"; end if; q<=temp; end process; end Behavioral;

VERILOG CODE module gray(clr,clk, q); input clr,clk; output reg[2:0] q; reg temp=3'd0; always@(posedge clk,posedge clr) begin if(clr==0) begin case(temp) 3'd0:q=3'd1; 3'd1:q=3'd3; 3'd2:q=3'd6; 3'd3:q=3'd2; 3'd6:q=3'd7; 3'd7:q=3'd5; 3'd5:q=3'd4; 3'd4:q=3'd0; endcase end else q=3'd0; end

endmodule

38

Truth table
Rst 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Clk X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 En 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

c) BINARY COUNTER(UP/DOWN) Black Box clk Binary counter qout(3 dt 0)

rst

Truth table
Clk X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Rst 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Qout 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 39

VHDL CODE entity bin_as is Port ( dir,clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (3 downto 0)); end bin_as; architecture Behavioral of bin_as is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd) variable temp:std_logic_vector(3 downto 0):="0010"; begin if rising_edge(clkd(21)) then if (clr='0') then if (dir='1') then temp:=temp+'1'; else temp:=temp-'1'; end if; else temp:="0000"; end if; end if; q<=temp; end process; end Behavioral;

VERILOG module bin_as(clk,clr,dir, temp); input clk,clr,dir; output reg[3:0] temp; always@(posedge clk,posedge clr) begin if(clr==0) begin if(dir==0) temp=temp+1; else temp=temp-1; end else temp=4'd0; end endmodule

Output 0000

Output 1111

RESULT: Asynchronous and Synchronous counters have been realized and simulated using HDL codes. 40

Experiment No. 8
AIM: Simulation and realization of Ring counter. COMPONENTS REQUIRED: FPGA board, FRCs, jumper and power supply. RING COUNTER Implement design Configure device (impact)after switching on power supply Select the slave serial mode Select the source file Right click on xilinx and select program

Connect input port to dip switch and output port to leds. Vary the inputs and view the corresponding outputs.

41

SL. NO. 4.2.0

Infrastructure

Requirement AICTE/University Norms

Actually provided

Cost/
Amount

Year of purchase

VHDL LAB

4.2.1
Multi-Vendor Universal Demo Board(kit includes motherboard along with downloading Cables)

10

12

20000/ 240000

1-02-05

Power supply, Xilinx FPGA-100k gate density Xilinx CPLD. Interfacing cards VTU interface-1 & VTU interface-2 along with above motherboards to perform all experiments of VHDL lab as per revised VTU syllabus 4.2.2
CM 640 Chipmax

04 Pattern generator cum Logic Analyzer-64 channel

06

40000/ 240000

1-02-05

4.2.3
Chipscope Pro-logic

01

01

20000/ 20000

1-02-05

Analyzer from AGILENT Technologies for on-chip debugging and real-time analysis of Xilinx FPGAs 4.2.4 SiMS-VLSI Universal VLSI Trainer/Evaluation Kit J Tag Cable 1No Power Supply 1No Operation Manual 1No 4.2.5 SiMS PLD (Spartan-II, CPLD cool runner, SPROM)(3 Nos) 4.2.6 SiMS-GPIO General purpose Integrated Interface module 4.2.7 Foundation Express: XILINX 6.1i Version: ISE Inclusive of all taxes

02

02

38,270.40

19-07-04

1 set each 01 01

1 set each 01 01

9,954.00 4,725.00 42,000.00 Grand Total:

19-07-04 19-07-04

5,44,949.40

42

entity bcd is Port ( clr,clk,dir : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0); tc : out STD_LOGIC); end bcd; architecture Behavioral of bcd is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) variable temp:std_logic_vector(3 downto 0); begin if(clr='1')then temp:="0000";tc<='0'; elsif rising_edge(clkd(21)) then if (dir='1') then temp:=temp+1; elsif(dir='0') then temp:=temp-1; end if; if(dir='1' and temp="1010") then temp:="0000"; tc<='1'; elsif(dir='0' and temp="1111") then temp:="1001"; tc<='1'; else tc<='0'; end if; end if; q<=temp; end process; end Behavioral; entity bin_as is Port ( dir,clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (3 downto 0)); end bin_as; architecture Behavioral of bin_as is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process;

process(clkd)

43

variable temp:std_logic_vector(3 downto 0):="0010"; begin if rising_edge(clkd(21)) then if (clr='0') then if (dir='1') then temp:=temp+'1'; else temp:=temp-'1'; end if; else temp:="0000"; end if; end if; q<=temp; end process;

end Behavioral; entity binary is Port ( dir,clk,clr : in STD_LOGIC; q : out STD_LOGIC_vector(3 downto 0)); end binary; architecture Behavioral of binary is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) variable temp:std_logic_vector(3 downto 0):="0010"; begin if (clr='0') then if rising_edge(clkd(21)) then if dir='1' then temp:=temp+'1'; else temp:=temp-'1'; end if; else temp:="0000"; end if; end if; q<=temp; end process;

end Behavioral; entity gray is Port ( clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0)); end gray;

44

architecture Behavioral of gray is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clr,clkd) variable temp:std_logic_vector(2 downto 0); begin if(clr='0') then if rising_edge(clkd(21)) then case temp is when "000"=> temp:="001"; when "001"=> temp:="011"; when "011"=> temp:="010"; when "010"=> temp:="110"; when "110"=> temp:="111"; when "111"=> temp:="101"; when "101"=> temp:="100"; when "100"=> temp:="000"; when others => null; end case; end if; else temp:="000"; end if; q<=temp; end process; end Behavioral; entity johnc is Port ( clk,clr : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end johnc; architecture Behavioral of johnc is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) begin if (clr='1') then q<="0000"; elsif rising_edge(clkd(21)) then q<=(not q(0))& q(3 downto 1); end if;

45

end process;

end Behavioral; entity ring is Port ( clk,clr,l : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end ring; architecture Behavioral of ring is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) begin if (clr='1') then q<="0000"; elsif rising_edge(clkd(21)) then if (l='1') then q<="1000"; else q<=q(0) & q(3 downto 1); end if; end if; end process;

end Behavioral;

module alu1(a,b,s,en,y); input [3:0] s,a,b; input en; output reg [7:0] y; always@(a,b,s,en,y) begin if(en==1) begin case(s) 4'd0:y=a+b; 4'd1:y=a-b; 4'd2:y=a*b; 4'd3:y={4'd0,~a}; 4'd4:y={4'd0,(a&b)}; 4'd5:y={4'd0,(a|b)}; 4'd6:y={4'd0,(a^b)}; 4'd7:y={4'd0,~(a&b)}; 4'd8:y={4'd0,~(a|b)};

46

4'd9:y={4'd0,(~a^b)}; default:begin end endcase end else y=8'd0; end endmodule module bcd(clr,clk,dir, tc, q); input clr,clk,dir; output reg tc; output reg[3:0] q; always@(posedge clk,posedge clr) begin if(clr==1) q=4'd0; else begin if (dir==1) q=q+1; else if(dir==0) q=q-1; if(dir==1 & q==4'd10) begin q=4'd0;tc=1'b1; end else if(dir==0 & q==4'd15) begin q=1'd9;tc=1'b1; end else tc=1'b0; end end endmodule module bin_as(clk,clr,dir, temp); input clk,clr,dir; output reg[3:0] temp; always@(posedge clk,posedge clr) begin if(clr==0) begin if(dir==0) temp=temp+1; else temp=temp-1; end else temp=4'd0; end endmodule module binary(clk,clr,dir, temp); input clk,clr,dir; output reg[3:0]temp; always@(posedge clk) begin if(clr==0)

47

begin if(dir==0) temp=temp+1; else temp=temp-1; end else temp=4'd0; end

endmodule module gray(clr,clk, q); input clr,clk; output reg[2:0] q; reg temp=3'd0; always@(posedge clk,posedge clr) begin if(clr==0) begin case(temp) 3'd0:q=3'd1; 3'd1:q=3'd3; 3'd2:q=3'd6; 3'd3:q=3'd2; 3'd6:q=3'd7; 3'd7:q=3'd5; 3'd5:q=3'd4; 3'd4:q=3'd0; endcase end else q=3'd0; end

endmodule module jhonson(clk,clr, q); input clk,clr; output reg[3:0] q; always@(posedge clk,posedge clr) begin if(clr==1) q=4'd0; else q={(~q[0]), q[3:1]}; end endmodule module ring(clk,clr,l, q); input clk,clr,l; output reg[3:0] q; always@(posedge clk,posedge clr) begin if(clr==1) q=4'd0; else begin

48

if (l==1) q=4'd8; else q={q[0], q[3:1]}; end end

endmodule entity bcd is Port ( clr,clk,dir : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0); tc : out STD_LOGIC); end bcd; architecture Behavioral of bcd is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) variable temp:std_logic_vector(3 downto 0); begin if(clr='1')then temp:="0000";tc<='0'; elsif rising_edge(clkd(21)) then if (dir='1') then temp:=temp+1; elsif(dir='0') then temp:=temp-1; end if; if(dir='1' and temp="1010") then temp:="0000"; tc<='1'; elsif(dir='0' and temp="1111") then temp:="1001"; tc<='1'; else tc<='0'; end if; end if; q<=temp; end process; end Behavioral; entity bin_as is Port ( dir,clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (3 downto 0)); end bin_as; architecture Behavioral of bin_as is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then

49

clkd<= clkd + '1'; end if; end process;

process(clkd) variable temp:std_logic_vector(3 downto 0):="0010"; begin if rising_edge(clkd(21)) then if (clr='0') then if (dir='1') then temp:=temp+'1'; else temp:=temp-'1'; end if; else temp:="0000"; end if; end if; q<=temp; end process;

end Behavioral; ntity binary is Port ( dir,clk,clr : in STD_LOGIC; q : out STD_LOGIC_vector(3 downto 0)); end binary; architecture Behavioral of binary is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) variable temp:std_logic_vector(3 downto 0):="0010"; begin if (clr='0') then if rising_edge(clkd(21)) then if dir='1' then temp:=temp+'1'; else temp:=temp-'1'; end if; else temp:="0000"; end if; end if; q<=temp; end process;

50

end Behavioral; entity gray is Port ( clr,clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (2 downto 0)); end gray; architecture Behavioral of gray is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clr,clkd) variable temp:std_logic_vector(2 downto 0); begin if(clr='0') then if rising_edge(clkd(21)) then case temp is when "000"=> temp:="001"; when "001"=> temp:="011"; when "011"=> temp:="010"; when "010"=> temp:="110"; when "110"=> temp:="111"; when "111"=> temp:="101"; when "101"=> temp:="100"; when "100"=> temp:="000"; when others => null; end case; end if; else temp:="000"; end if; q<=temp; end process; end Behavioral; entity johnc is Port ( clk,clr : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end johnc; architecture Behavioral of johnc is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) begin

51

if (clr='1') then q<="0000"; elsif rising_edge(clkd(21)) then q<=(not q(0))& q(3 downto 1); end if; end process;

end Behavioral; entity ring is Port ( clk,clr,l : in STD_LOGIC; q : inout STD_LOGIC_VECTOR (3 downto 0)); end ring; architecture Behavioral of ring is signal clkd:std_logic_vector(21 downto 0); begin process(clk) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process; process(clkd,clr) begin if (clr='1') then q<="0000"; elsif rising_edge(clkd(21)) then if (l='1') then q<="1000"; else q<=q(0) & q(3 downto 1); end if; end if; end process;

end Behavioral;

FLIP FLOPS
entity dff is Port ( d,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end dff; architecture Behavioral of dff is signal clkd:std_logic_vector(21 downto 0);

52

begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process;

process (clk) variable temp: std_logic; begin if rising_edge(clk) then temp:=d; end if; q<=temp;qb<=not temp; end process;

end Behavioral; entity jkff is Port ( j,k,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end jkff; architecture Behavioral of jkff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process;

process(clk,rst) variable jk:std_logic_vector(1 downto 0); variable temp:std_logic:='0'; begin jk:=j&k; if (rst ='0')then if rising_edge(clk) then case jk is when "01"=> temp:='0'; when "10"=> temp:='1'; when "11"=> temp:=not temp; when others=> null; end case; end if; else temp:='0'; end if; q<=temp; qb<=not temp; end process;

53

end Behavioral; entity srff is Port ( s,r,rst,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end srff; architecture Behavioral of srff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process;

process(clk,rst) variable sr:std_logic_vector(1 downto 0); variable temp1,temp2:std_logic:='0'; begin sr:=s&r; if (rst ='0')then if rising_edge(clk) then case sr is when "01"=> temp1:='0'; temp2:='1'; when "10"=> temp1:='1'; temp2:='0'; when "11"=> temp1:='1'; temp2:='1'; when others=> null; end case; end if; else temp1:='0'; temp2:='1'; end if; q<=temp1;qb<=temp2; end process; end Behavioral; entity tff is Port ( t,clk : in STD_LOGIC; q,qb : out STD_LOGIC); end tff; architecture Behavioral of tff is signal clkd:std_logic_vector(21 downto 0); begin process(clkd) begin if rising_edge(clk) then clkd<= clkd + '1'; end if; end process;

process (clk) variable temp:std_logic:='0'; begin

54

if rising_edge(clk) then if (t='1') then temp:=not temp; else temp:=temp; end if; end if; q<=temp;qb<=not temp; end process; end Behavioral;

VERILOG FP
module dff(d,clk,rst,q,qb); input d,clk,rst; output q,qb; reg q,qb; reg temp=0; always@(posedge clk,posedge rst) begin if (rst==0) temp=d; else temp=temp; q=temp; qb=~ temp ; end endmodule module jkff(j,k,clk,rst, q,qb); input j,k,clk,rst; output q,qb; reg q,qb; reg [1:0]jk; always@(posedge clk,posedge rst) begin jk={j,k}; if(rst==0) begin case (jk) 2'd1:q=1'b0; 2'd2:q=1'b1; 2'd3:q=~q; default: begin end endcase end else q=1'b0; qb=~q; end endmodule module srff(s,r,clk,rst, q,qb); input s,r,clk,rst; output q,qb; reg q,qb; reg [1:0]sr;

55

always@(posedge clk,posedge rst) begin sr={s,r}; if(rst==0) begin case (sr) 2'd1:q=1'b0; 2'd2:q=1'b1; 2'd3:q=1'b1; default: begin end endcase end else begin q=1'b0; end qb=~q; end

endmodule module tff(t,clk,rst, q,qb); input t,clk,rst; output q,qb; reg q,qb; reg temp=0; always@(posedge clk,posedge rst) begin

if (rst==0) begin if(t==1) begin temp=~ temp; end else temp=temp; end q=temp;qb=~temp; end

endmodule module alu1(a,b,s,en,y); input [3:0] s,a,b; input en; output reg [7:0] y; always@(a,b,s,en,y) begin if(en==1) begin case(s) 4'd0:y=a+b; 4'd1:y=a-b; 4'd2:y=a*b;

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4'd3:y={4'd0,~a}; 4'd4:y={4'd0,(a&b)}; 4'd5:y={4'd0,(a|b)}; 4'd6:y={4'd0,(a^b)}; 4'd7:y={4'd0,~(a&b)}; 4'd8:y={4'd0,~(a|b)}; 4'd9:y={4'd0,(~a^b)}; default:begin end endcase end else y=8'd0; end endmodule

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