IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.

12, DECEMBER 2010 3003

Three Degree of Freedom Robust Voltage Controller
for Instantaneous Current Sharing Among Voltage
Source Inverters in Parallel
Shahil Shah and Partha Sarathi Sensarma, Member, IEEE
AbstractVoltage controlled voltage source inverters (VCVSI)
are predominantly used as an interface between source and grid in
distributed generation. Modularity of system is achieved by paral-
lel operation of several VCVSI of reduced rating. In this paper, a
3-DOF control scheme is proposed for parallel operation of three
phase inverters to enable equal load sharing even during transients
while tracking a common sinusoidal voltage reference. The voltage
reference is either free running or derived from grid voltage and
can be used to synchronize a parallel inverter module with any
utility grid. The control algorithm for each inverter is identical,
and it is independent of terminal parameters of other inverters,
granting N+1 modularity to the system. The proposed fast inner
voltage loop with second-order controller and lead compensators
enable stable operation at lowswitching frequencies. Avoltage cor-
rection is added to the reference to ensure sharing of higher order
load current harmonics among inverters. A method to estimate the
system tolerance to parametric uncertainties and delays is devel-
oped using -analysis and a method is presented to improve it. The
analysis is validated with simulation and experimental results on
two 110 Vac/2.5 kVA three-phase inverters, paralleled to form a
stand-alone grid and feeding a nonlinear load.
Index Terms-analysis, instantaneous current sharing, multi-
inverter system, parallel operation.
I. INTRODUCTION
P
ARALLEL CONNECTED arrays of voltage controlled
voltage source inverters (VCVSI) have a wide range of
applications including modular uninterruptible power supply
systems and microgrids with renewable energy sources (RES).
However, parallel operation requires an effective control strat-
egy to avoid circulating currents and ensure commensurate shar-
ing of the total load current among the parallel VSIs, in propor-
tion to their ratings, both in steady-state and dynamic conditions.
Classical approaches for parallel operation of inverters in-
corporate droop characteristics, similar in principle to parallel
operation of alternators in power systems [1][10]. Although
these methods do not require control interconnection among
Manuscript received November 5, 2009; revised April 24, 2010; accepted
April 28, 2010. Date of current version December 27, 2010. This work was
supported by the research grant under National Mission for Power Electronics
Technology initiative of Department of Information Technology, Government
of India. Recommended for publication by Associate Editor F. Blaabjerg.
S. Shah is with the Accelerator and Pulsed Power Division, Bhabha Atomic
Research Centre, Mumbai 400085, India (e-mail: shahil@barc.gov.in).
P. S. Sensarma is with the Department of Electrical Engineering, Indian
Institute of Technology, Kanpur 208016, India (e-mail: sensarma@iitk.ac.in).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TPEL.2010.2050150
inverters, they exhibit poor frequency and voltage regulation.
Though it is possible to share harmonics currents of nonlinear
loads by using harmonic droop coefcients [8], it requires the
use of extra droop coefcients for each harmonic and is limited
to lower order harmonics due to poor dynamics of the method.
Masterslave methods [11][14] employ one VCVSI acting as
a master and remaining (n-1) current controlled VSIs as slaves.
However, the system has to be shut down in the event of failure
of master unit. Effects on circulating currents among inverters
caused by various factors, like dead-time effects [15] and com-
mon mode circulating currents due to common dc link [16],
have also been investigated.
Continuous improvement in device switching speeds has
enabled higher hardware bandwidth of VCVSIs, which has
inspired a series of instantaneous current sharing schemes
[17] [25]. These schemes are based on a control mechanism,
which requires information of current in every parallel unit. Al-
though the instantaneous current sharing ensures proportionate
sharing of load harmonic currents, the overall systembandwidth
is limited due to lower order controllers [17]. Controller design
is done using classical stability margins, although these are
multiloop control systems [17]. On one hand, this restricts the
achievable closed-loop performance and, on the other, it does not
consider the cumulative effects of parametric and delay uncer-
tainties in various loops on relative stability of the system [26].
Also, in [17], the effects of uncertainties in parameters are an-
alyzed collectively by a single-disturbing current source. This
is an indirect approach and results in conservative design. A
common voltage controller for all paralleled inverters, instead
of individual voltage controllers for each inverter, has also been
proposed [19]. But this topology results in inadequate redun-
dancy since no inverter is allowed to operate as an independent
unit. Available methods for instantaneous current sharing dis-
cuss the design of outer current controller, considering only the
aspect of system stability [17], [18]. Efcacy of the controllers
in reducing circulating currents and the corresponding dynamics
of current equalization among parallel units are crucial gures-
of-merit, which have been generally de-emphasized. Moreover,
despite the fact that resonating effects of long wiring cables are
discussed in literature [25], the critical consequences of delays
caused by sampling and transmission delays due to distant lo-
cation of loads have not been addressed. Such delays are crucial
for high-power inverter units operating at low switching fre-
quencies, where these loop delays make the operation of units
at low switching frequencies unstable. It is shown in this paper
that, in fact, the existing schemes are completely unsuitable at
low switching frequencies.
0885-8993/$26.00 2010 IEEE
3004 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 12, DECEMBER 2010
Fig. 1. Distributed generation conguration of parallel inverters.
In this paper, a novel perturbed plant model is proposed for
parallel inverters to segregate the perturbed plant and to ana-
lyze the effectiveness of the outer current controller in reducing
circulating currents and equalizing load currents from different
inverters. To realize the feature of instantaneous current sharing
while addressing the aforementioned issues, a -analysis-based
second-order unied voltage controller is proposed, which quan-
titatively evaluates the effect of uncertainties on system stabil-
ity by modeling parametric uncertainty, using linear fractional
transformation (LFT) [27]. Structured singular value () is used
to determine the maximum tolerable parametric uncertainty and
the measure of relative stability. The voltage controller is de-
signed with higher bandwidth to simultaneously track a free-
running voltage reference and correction terms from an outer
current loop. The outer current loop is commanded by the instan-
taneous weighted fraction of the load current. Specic compen-
sation schemes in the multiloop voltage controller are proposed
in this paper, which allows 3 DOF for compensation of switch-
ing and sampling lag. Compensator performance is evaluated
at different sampling frequencies using -analysis, which re-
veals substantial improvement with the proposed scheme. This
allows stable operation at lower switching frequencies as well as
higher uncertainty in parameter values can be accommodated.
Also, the system remains stable even with higher transmission
lag. Stability analysis of the whole system, in presence of param-
eter variation, is done by superposing an equivalent perturbed
system on an ideal system, characterized by identical param-
eters for all inverters. Design issues for the proposed strategy
are discussed, and all analysis is supported by simulation and
experimental results.
II. SYSTEM CONFIGURATION AND MODELING
Fig. 1 shows the conceptual layout of n parallel inverters
being fed from various RES modules. Modulation signals for
each three-phase inverter are generated through voltage control
scheme, consisting of stabilizing inner capacitor current loop
and output capacitor voltage feedback loop [17]. The voltage
control loop tracks the common synchronized reference v
o

along with correction signal v

p
from outer current sharing
loop to minimize current imbalance among parallel units, as
shown in Fig. 2, for the pth inverter. The common current ref-
erence i
avg
is the averaged signal of output currents from all
inverters and i
p
is output current from the pth inverter. Devia-
TABLE I
NOMINAL PARAMETER VALUES FOR THREE-PHASE INVERTER AND
RIPPLE FILTER
tion of inverter output current from i
avg
drives the proportional
current sharing controller to produce correction signal v
p
. Fil-
ter inductor current i
l
is sum of inverter output current i
p
and
capacitor current i
c
.
A. Modeling of Plant
The inverter with ripple lter forms the basic plant and each
phase of these second-order ripple lters is congured with a
tuned inductor (L
f
) and capacitor (C
f
) along with consideration
of parasitic resistance of inductor (R
f
). Fig. 2 shows the mul-
tiloop structure of voltage control scheme for inverter having
feedback loops, using lter capacitor current i
c
and the capaci-
tor voltage v
p
. The switching harmonics of output voltage from
inverter v
i
are ltered using LC lter. Nominally, modeling the
inverter as an algebraic gain (M) [17], the control and distur-
bance transfer functions for the open-loop plant are derived from
Fig. 2 as in (1).
v
p
(s)
v
i
(s)

= G
c
(s) =
1 +R
c
C
f
s
L
f
C
f
s
2
+ (R
c
+R
f
)C
f
s + 1
v
p
(s)
i
p
(s)

= G
d
(s) =
R
f
+L
f
s
L
f
C
f
s
2
+ (R
c
+R
f
)C
f
s + 1
. (1)
Nominal parameter values used for design and hardware are
listed in Table I. Bode plots for nominal plant transfer func-
tion G
c
(s) and disturbance transfer function G
d
(s) are shown
in Fig. 3. Although the forms of these functions are similar,
the difference in the bode plots is due to the positions of the
respective zeros.
B. Robust Voltage Controller
Inner loop voltage controller bandwidth is decided by the
highest order of harmonic in the load current. In usual nonlinear
loads, magnitude of current harmonics higher than 21st is suf-
ciently small to pose any major challenge to stability. Additional
damping is provided by an inner capacitor current loop with gain
k
c
, which actively damps the system and imparts robustness to-
ward external disturbances [28], [29]. Modied system transfer
functions in presence of active damping loop are as follows.
G
/
c
(s) =
v
p
(s)
v
i
(s)
=
1 +R
c
C
f
s
L
f
C
f
s
2
+ (R
c
+R
f
+k
c
)C
f
s + 1
G
/
d
(s) =
v
p
(s)
i
p
(s)
=
(R
f
+L
f
s)
L
f
C
f
s
2
+ (R
c
+R
f
+k
c
)C
f
s + 1
.
(2)
SHAH AND SENSARMA: THREE DEGREE OF FREEDOM ROBUST 3005
Fig. 2. Per phase schematic of complete control loop for pth inverter.
Fig. 3. Bode plot of nominal plant and disturbance transfer function.
Fig. 4. Bode plot of nominal plant and disturbance transfer function with
active damping loop.
It is evident from (2) that the loop emulates the effect of an
additional resistance of k
c
. Bode plots of plant and disturbance
transfer function in Fig. 4 illustrate the reduction in resonant
peaks.
1) LFT Model of Perturbed Plant: Parametric uncertainties
in lter parameters and delays in digitized feedback loops are
unavoidable, and their effects on performance and stability of
voltage control loop has to be analyzed. Fig. 5 shows the block
diagrammatic representation of plant transfer function G
/
c
(s). It
is, however, obvious that the output impedance G
/
d
(s) is spar-
ingly affected by parameter variations, especially in the low-
Fig. 5. Block diagram of plant.
frequency zone, and this effect is further lowered by the stable
closed loop.
Although the plant parameters L
f
, C
f
, and R
f
exhibit certain
variations from their nominal values, it can be assumed that
their values lie within certain known intervals by anticipating
the worst-case perturbations. Mathematically,
L
f
=

L
f
(1 +p
L
f

L
f
) and C
f
=

C
f
(1 +p
C
f

C
f
)
(3)
where

L
f
and

C
f
are nominal values from Table I. Also, the
terms p
L
f

L
f
and p
C
f

C
f
in (3) represent the possible relative
perturbations on these two lter parameters. The uncertainty
interval is dened by assuming p
L
f
=0.3, p
C
f
=0.3, and 1

L
f
,
C
f
1. Note that this represents up to 30% uncertainty
in lter inductance and lter capacitance. Perturbation in R
f
is
not considered as it is evident from Fig. 5 that the uncertainty
in R
f
will not affect the performance of system owing to the
large xed value of active damping constant k
c
compared to the
small parasitic resistance.
Upper LFT (ULFT) is used to represent parametric uncer-
tainties in the block diagram to express the system equations in
M-conguration [30]. The perturbed parameter, 1/x (x = L
f
or C
f
), can be represented in LFT in
x
as in (4).
1
x
=
1
x
1
(1 +p
x

x
)
=
1
x

p
x
x

x
(1 +p
x

x
)
1
=F
U
(M
x
,
x
) with M
x
=
_
p
x
1
x
p
x
1
x
_
. (4)
The system model of Fig. 5 as an LFT of the unknown, real per-
turbations
L
f
and
C
f
with inputs and outputs of
L
f
and
C
f
as y
L
f
, y
C
f
, and u
L
f
, u
C
f
, respectively, along with denition
of states is shown in Fig. 6.
3006 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 12, DECEMBER 2010
Fig. 6. Block diagram of plant with LFT model of uncertain parameters.
Fig. 7. Close-loop system structure.
Equation (5) describes the dynamic behavior of perturbed
plant of Fig. 6, using (4) with y (=x) as its output.

t
y
L
f
y
C
f
y

=
G
L C
..

0
1

C
f
0 p
C
f
0

L
f

R
f
+k
c

L
f
p
L
f
0
1

L
f

L
f

R
f
+k
c

L
f
p
L
f
0
1

L
f
0
1

C
f
0 p
C
f
0
1 0 0 0 0

x
t
u
L
f
u
C
f
v
i

_
u
L
f
u
C
f
_
=

..
_

L
f
0
0
C
f
_
_
y
L
f
y
C
f
_
. (5)
The uncertain behavior of original plant of Fig. 5 is described
by an upper LFT representation (y = F
u
(G
LC
, ) v
i
) using
system matrix G
LC
and uncertainty matrix , as shown in
shaded portion of Fig. 7. It also shows the close-loop control
topology with voltage controller and performance weighting
transfer function W
p
.
2) Controller Design: The capacitor voltage feedback con-
troller is designed to ensure required close-loop bandwidth
higher than 26th harmonic to minimize phase errors at the edge
of the target passband (21st harmonic). To achieve optimum
tracking performance and good disturbance rejection, sensitivity
function (S = 1/(1 +G
/
c
H)) has to be minimized. Performance
objectives are closely related to the sensitivity function [27],
and they are dictated by shaping sensitivity function using W
p
by relation
[ W
p
(j)S(j) [ 1 . (6)
Sensitivity function shows the additional attenuation to the effect
of disturbing load current i
p
apart from

G
d
achieved through
feedback controller. A rst-order high-gain low-pass weighting
function tailors the performance requirements like bandwidth
Fig. 8. Inverse weighting function and closed-loop sensitivity functions for
nominal and perturbed systems.
TABLE II
PARAMETER VALUES FOR VOLTAGE CONTROLLER
and load current disturbance attenuation in lowfrequency range,
as shown in Fig. 8.
From (6), it is obvious that the singular value plot of 1/W
p
determines the upper bound for the sensitivity function. The
performance requirement becomes less stringent with increasing
frequency, and it can be seen fromFig. 8 that beyond the required
bandwidth, the disturbance is no longer attenuated.
The -analysis-based controller design is more appealing be-
cause it is capable of considering robust performance and robust
stability simultaneously and it takes into account the uncertain-
ties in different loops of the multiloop structure [26]. For stan-
dard M-conguration, value gives the measure of the small-
est size of uncertainty that makes system M unstable and it is
dened such that

1
(M) is equal to the smallest of maximum
singular value of ( ()), which makes (I M(j)(j))
singular at some frequency [30]. Mathematically,

1
(M) := min

_
() : det(I M) = 0 for some
_
(7)
where is set of possible uncertainties matrices, . Hence, if

(M(s)) < 1/, it implies that the structured uncertainty in

the system can be times higher than the stipulated bound of
p
L
f
and p
C
f
. This quanties the robust stability of controller
H in dealing with structured uncertainty [30]. For the pro-
posed -analysis-based second-order controller H(s), it is of
the form shown in (8), which may be conceived as a cascaded
P-I controller with a phase-lead network.
H(s) =
K(s +z1)(s +z2)
s(s +p)
. (8)
All relevant controller parameters are listed in Table II.
SHAH AND SENSARMA: THREE DEGREE OF FREEDOM ROBUST 3007
Fig. 9. Robust stability analysis responses.
The structured singular value () lies within the following
bound
(M)

(M) (M) (9)

where (M) is spectral radius and (M) is maximum singular
value of system transfer function matrix M(s). The frequency
responses of the upper and lower bounds of for closed loop
are shown in Fig. 9, and it is clear that the close-loop system
achieves robust stability as is less than unity [27].
The peak at resonant frequency signies that the most desta-
bilizing effect of parametric uncertainties is in that frequency
range. Also, the peak value of of 0.4195 shows that the struc-
tured perturbations with norm less than 1/ are permissible,
i.e., the voltage control loop remains stable for | |< 1/ .
The designed -analysis-based controller accommodates para-
metric uncertainties of up to 71.5% (30 1/ ). Fig. 8 also
shows the nominal closed-loop sensitivity function, which re-
mains below the inverse performance weighting function over
a large frequency range, thus assuring specied nominal track-
ing and disturbance rejection performances. Also, the sensitivity
function for perturbed systems remains belowthe 1/W
p
plot for
frequency range of concern, as shown in Fig. 8, assuring robust
performance.
3) Modeling of Inner Loop: The nominal close-loop transfer
function G
clp
of the voltage control loop and the disturbance
transfer function in form of impedance Z
o
are stated as follows:
G
clp
=
v
p
v
p

=

G
c
H
1 +

G
c
HS
=

G
c
HS
Z
o
=
v
p
i
p
=

G
d
1 +

G
c
H
=

G
d
S. (10)
These two transfer functions are succinctly represented as
a controlled voltage source with gain G
clp
in series with
impedance Z
o
, as shown in Fig. 10.
4) Lead Compensation Scheme for Feedback Delays: The
distributed nature of sources and loads imply sensing of the
load currents at local feeders, which need to be transmitted over
some distance to the inverters for feedback. This results in de-
Fig. 10. Circuit representation of inverter and lter integrated with damping
and inner voltage loops.
Fig. 11. Voltage controller with ZOH and delay compensators in feedback
loops.
lays within the feedback loops with consequent degradation of
stability margins. Additionally, sampling of the feedback signals
introduces a linear phase delay, which further compromises rel-
ative stability as the sampling frequency
s
is reduced. Since
s
also largely decides the minimum inverter switching frequency,
obvious attempts to stabilize the system degrades efciency and
cost-benet of the inverter. Existing current sharing schemes
do not account for this fact and are generally unsuitable for
low-frequency (high power) applications.
Since it is difcult to analyze the effect of delays on relative
stability of a multiloop system using classical stability margins
[26], -analysis is used here to quantify the delays, which it can
accommodate while maintaining performance and robustness.
It also provides a generalized platform to study the effect of
various compensation techniques, which can be used to alleviate
the degrading effects of any such delays.
Effect of sampling delay at different sampling frequency,
which is assumed to be same as switching frequency, is analyzed
here by introducing ZOH (zero-order hold) block in the inner
capacitor current and output voltage loops, as shown in Fig. 11.
First-order Pade approximationshownin(11) is usedtomodel
ZOH.
ZOH =
(1 e
2s/
s
)
(2s/
s
)

_
1
1 s/
s
1 +s/
s
_
/(2s/
s
) =
1
1 +s/
s
.
(11)
Fig. 12 shows the frequency responses for upper bound of for
close loop at different switching frequencies. It is evident that
the system loses stability and the instantaneous current sharing
is not possible at lower switching frequencies, where SSV is
beyond unity.
It is also observed that the instability caused due to sam-
pling delays lies mostly around the resonant frequency (
r
=
3008 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 12, DECEMBER 2010
Fig. 12. -responses versus switching frequency for inner voltage loop.
Fig. 13. -responses versus switching frequency with lead compensation
included.
1/
_
L
f
C
f
), indicated by values exceeding unity. Sampling
lag in feedback signals at the resonant frequency
r
is

lag
(
r
) =

r

s
radian. (12)
First order lead compensators L(s) with unity gain and phase
lead of
lag
at
r
are proposed and included for compensation
of sampling delays in active damping and voltage feedback loop
of inner-voltage controller, as shown in Fig. 11. Fig. 12 shows
the closed-loop frequency responses for upper bound of values
at different switching frequencies, and Fig. 13 shows the corre-
sponding -responses after inclusion of lead compensation. In
both cases, the sampling frequency is assumed to be same as the
switching frequency. The value is brought within unity even
for lower switching frequencies and makes it possible to stably
operate the current sharing scheme at lower switching speeds.
The transmission delays, which are also deterministic in nature,
can be compensated in the same manner.
The peaks of , from Fig. 12 are plotted for different switch-
ing frequencies in Fig. 14 for different control congurations,
namely, tuned P-I controller, using classical stability margins
[17], proposed -analysis-based second-order voltage controller
and combination of -analysis-based controller, and lead com-
Fig. 14. Peak values of SSV() versus switching frequency for different con-
trol congurations.
Fig. 15. Block diagrammatic representation of multiinverter system with cur-
rent sharing controller.
pensation for sampling delays. It shows that stable operation is
not possible for switching frequencies below 38 kHz with rst-
order voltage controllers. Thus, it demonstrates the signicant
benets of the proposed scheme over reported methods, using
lower order voltage controllers designed based on classical sta-
bility margins.
C. Current Sharing Controller
Fig. 15 shows the schematic representation of multiple invert-
ers in parallel, feeding the local grid through their corresponding
transformers. Despite the voltage controller, imbalance in cur-
rents shared by different inverters is still perceptible at higher
frequencies due to unavoidable deviation in lter parameters.
An outer current loop is proposed here to improve transient
sharing of currents among the paralleled units.
The common current reference for all inverters is derived
from the instantaneous weighted average of the load current.
Specically, current reference for the pth inverter is derived as
SHAH AND SENSARMA: THREE DEGREE OF FREEDOM ROBUST 3009
Fig. 16. Equivalent circuit of multiparallel inverters.
follows.
i

p
=
S
p

n
k=1
S
k
i
L
(13)
where S
k
is the VArating of the kth inverter. In the present case,
without loss of generality, all inverters are considered to be of
identical rating. Hence (13) reduces to
i

p
=
i
L
n

=i
avg
. (14)
A proportional controller ensures adequate reference tracking,
as the effective plant comprises a rst-order line admittance (R
L). For the rst inverter path, v
1
is the control input and the grid
voltage v
o
acts as the disturbance input. This controller output
generates a correction voltage term(v), over the synchronized
voltage reference, to track the current command, as shown in
Fig. 2. So, for the pth inverter
v
p
= k
corr
i
avg
i
p
(15)
where k
corr
is the gain of the proportional controller.
1) Analysis of Current Sharing Controller: Fig. 10 shows the
circuit equivalent of the close-loop voltage controller, designed
in the previous section. Effect of the current sharing controller
is appended to this equivalent circuit by a dependent voltage
source in series. Consequently, the n-inverter model of Fig. 15
is updated to the circuit shown in Fig. 16.
In Fig. 15, all inverters would have shared the load current
equally if their lter, line, and control parameters were exactly
identical. But due to parameter mismatch, apart from average
current (i
avg
), each inverter in general carries a perturbation
current (i
p
). Each of these perturbation currents represent the
circulating current in that branch, which is the instantaneous
deviation of the total branch current from the ideal value of
i
avg
. So,
i
p
= i
avg
+ i
p
. (16)
From Fig. 16, loop equation for the pth inverter and load is
G
clp
V

o
+k
corr
G
clp
(i
avg
i
p
) i
p
(Z
o
+R
l
+L
l
s)
= i
L
Z
L
= V
o
. (17)
Dening the internal impedance (Z
ip
) of the pth branch as
Z
ip
= G
clp
k
corr
+Z
op
+R
l
+L
l
s (18)
Fig. 17. Equivalent circuit of perturbed portion of parallel inverters system.
(a) Conguration 1. (b) Conguration 2.
(17) reduces to
G
clp
V

o
i
avg
(Z
o
+R
l
+L
l
s) (i
p
)Z
ip
= i
L
Z
L
= V
o
.
(19)
For the ideal systemwithout any mismatchall inverters
carry equal load current (i
avg
) and all circulating currents reduce
to zero. Hence,

G
cl
V

o
i
avg
(Z
o
+R
l
+L
l
s) = i
L
Z
L
= V
o
(20)
where

G
cl
is the nominal closed-loop gain. Parameter variation
within each inverter introduces slight variation in the closed-
loop gains G
clp
. Dening
G
clp
V

o
=

G
cl
V

o
+ v
p
(21)
manipulation of (19), (20), and (21) yields the following equa-
tion of the perturbed system.
v
p
(i
p
)Z
ip
= 0. (22)
It is obvious that, for the ideal plant, any investigation into the
current sharing is superuous. Thus the effect on the perturbed
plant is considered here in greater detail. Equation (22) repre-
sents the voltage equation for the pth branch of the perturbed
plant, which is schematically shown in Fig. 17(a) and its Nor-
ton equivalent in Fig. 17(b). The excitation v
p
(i
p
) represents
inner-loop variations and disturbances in the pth inverter volt-
age (current). The perturbed system is not affected by load
variations and describes the dynamic behavior of the circulating
currents.
Equation (18) represents the complex impedance Z
ip
to the
circulating current i
p
of the pth branch whose poles can be
tuned by tuning the gain k
corr
. The current controller (k
corr
) acts
as a constant virtual impedance of high value added in series
with low valued Z
o
and line impedance, when G
clp
is approxi-
mated as unity in the frequency range of concern due to faster
inner loop. This decreases the percentage deviance and abso-
lute value of admittance of branches of perturbed plant. Hence,
current controller not only equalizes the impedances of all in-
verters, but it also decreases the amount of circulating current to
a large extent by selectively increasing the impedance offered.
All inverters will share equal currents if all these currents (i
p
)
in the perturbed plant decay fast.
3010 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 12, DECEMBER 2010
Considering the pth branch in Fig. 17, the Thevenin equivalent
of the remaining network is specied by
Z
Th
=
1

n
k=1,k,=p
(1/Z
ik
)
and V
Th
=

k=1,k,=p
i
p

Z
Th
.
(23)
Obviously, both V
Th
and Z
Th
progressively decrease as the
number of units (n) increases. Thus, branch current i
p
is
chiey decided by v
p
as
i
p
= Y
p
v
p
=
1
Z
ip
+Z
Th
v
p
. (24)
For the ideal situation of identical parameters, the quantity Y
p
in (24) reduces to
Y
p
=
n 1
n

Z
i
=
n 1
n

Y
i

=Y
total
. (25)
where

Z
i
(= 1/

Y
i
) is the nominal internal impedance function.
Asymptotic stability of admittance Y
total
(all poles in the left
half of s-plane) assures all circulating currents (i) decay ex-
ponentially to zero and poles in the deep left half imply better
dynamic response. Equation (25) shows that the number of in-
verters (n) only affects the gain of Y
total
, but not the location of
its poles (stability). As the number of parallel units increases, in a
real case, Y
Th
approaches (n 1)

Y
i
. Also, its stability depends
upon the stability of the admittance of single inverter Y
i
, because
the denominator of Y
Th
is equal to the product of denominators
of admittances of remaining network (n-1 inverters). Moreover,
the stability of Y
i
in presence of worst parametric perturbations
proves the stability of admittances of all inverters and hence of
Y
Th
.
In low-frequency region, rst term of (18) shadows the ef-
fect of remaining terms due to chosen high value of k
corr
. This
decreases and equalizes the admittances of individual inverters.
For nominal values of lter and line parameters,

Y
i
is stable.
The locus of its dominant poles is plotted in Fig. 18(a) and (b)
for perturbations in the lter parameters. Fig. 18(a) shows the
loci of poles with different k
corr
values, which illustrates the
controllability of pole locations by outer-loop controller gain.
The poles are observed to be somewhat less sensitive to varia-
tions in C
f
than to variations in L
f
. Fig. 18(c) shows the wide
variation of poles of Y
total
with variation in the proportional
gain k
corr
and its limiting value for stability. Hence, it is suf-
cient, even for substantial variations in system parameters, to
ensure arbitrary pole placement. Thus it is possible to uniquely
decide relative stability of Y
ip
, even in presence of deviations in
parameter values.
Apart from ensuring stability under parameter variations, the
control scheme is supposed to ensure proper sharing of the
load current among the various units. The extent of mismatch
among the paralleled units may be visualized by the spread of
the internal complex impedance of all branches. To this end, the
effectiveness of each subsequent stage in the control scheme is
summarized in Fig. 19. Each trace corresponds to a lter param-
eter pair, within a 30% range of variation around the nominal
values. Fig. 19(a) shows the open-loop internal impedance (G
d
),
TABLE III
PERTURBED PARAMETER VALUES OF TWO INVERTERS USED FOR SIMULATION
and Fig. 19(b) shows the frequency response of

G
d
. The admit-
tance function 1/Z
ip
is plotted in Fig. 19(c) for convenience. It
is to be noted that the admittances for all cases are equal in low
frequency range to the inverse of proportional gain of current
controller (20 log(1/k
corr
) = 4.7 dB). Also, the signicant
reduction in the spread of both the phase and magnitude plots
demonstrates that strict current sharing is ensured among the
various parallel branches.
Current in the pth branch, as a fraction of the total load current,
is dened by the sharing factor (
p
) as follows.

=
_
_
_
_
_
_
i
p

n
k=1
i
k
_
_
_
_
_
_
=
_
_
_
_
_
_
Y
ip

n
k=1
Y
ik
_
_
_
_
_
_
. (26)
Equation (26) is applicable for the close-loop system. In open
loop, the sharing factor is still obtainable from (26) by replacing
Y
i
with G
d
. Fig. 19(d) shows a comparison of the open- and
close-loop sharing factors for a two-inverter system. Filter pa-
rameters for the two inverters are at the two extreme bounds of
the range mentioned earlier. From (24), it follows that this is the
worst-case scenario, for which the sharing is observed to have
signicantly improved.
Since branch impedance Z
ip
limits the circulating current
ow among paralleled units, a high value of line impedance
parameters simplies the outer-loop design by reducing the re-
quired value of k
corr
.
2) Simulation Results for Current Sharing Loop: Fig. 20
shows the simulated currents of each of the three phases of two
parallel inverters under different load transients. A step load of
80% is applied at t = 40 ms and thrown off at t = 60 ms. Filter
parameters used in simulation of each of the two inverters are
given in Table III. It is observed that there is excellent sharing
of the load current in all phases of the two inverters.
III. EXPERIMENTAL RESULTS
The instantaneous current sharing loop and voltage controller
are implemented using two three-phase 110 V, 2.5 kVA, insu-
lated gate bipolar transistor inverters. The lter parameters are
same as listed in Table I. Switching frequency used in the exper-
imental studies is 20 kHz. The entire controller is realized on an
eld-programmable gate array (FPGA) (ALTERA-Cyclone 2)-
based platform. Current feedback is obtained with Hall-effect
current transducers, while voltages are sensed using optical iso-
lation ampliers. Sensor gains are tuned to optimum values to
utilize full resolution of A/D converters on FPGA card. All
SHAH AND SENSARMA: THREE DEGREE OF FREEDOM ROBUST 3011
Fig. 18. Stability and tuning of Y
total
in presence of perturbations in system parameters. (a) Variation of location of Poles of Y
i
with 30% variation in L
f
.
(b) Variation of location of Poles of Y
i
with 30% variation in C
f
. (c) Control on Location of Poles of Y
i
using k
corr
.
Fig. 19. Effect of control scheme on internal impedance and sharing factor. (a) Internal impedance (open-loop). (b) Internal impedance (with active damping).
(c) Branch admittance. (d) Sharing factor with two units.
sensed signals to FPGA card are passed through clamp circuits
to protect A/D converter from spurious peaks. Apart from local
parameters, each inverter also requires the information of the
total load current, i
L
. The load used was a three-phase diode
rectier feeding an RL circuit. Fig. 21 shows the experimen-
tal setup of two inverters with their ripple lters and rectier
load. To emulate the worst-case situation, experiments are per-
formed without line transformers, giving the lowest possible
line impedances.
Fig. 22 shows steady state responses of the voltage controller
and demonstrates the role of the damping loop. Fig. 22(a) and
22(b) shows the tracking performance in absence and presence,
respectively, of active damping. It is observed that oscillatory be-
havior of lter severely hampers waveformquality, when damp-
ing is absent. Fig. 23 shows the transient responses of the inner
voltage controller. Fig. 23(a) shows the reference and actual
voltages during inverter start-up. Response of voltage controller
clearly demonstrates the increased relative stability due to active
damping. Fig. 23(b) shows the phase-A current in one inverter
and the common grid voltage after application of full load. It is
observed that higher bandwidth of inner loop has ensured volt-
age tracking even in presence of such severe transients. As the
oscilloscope bandwidth was set to observe the high frequency
components of load current, the load current response shows
probe noise which were not present.
Fig. 24(a) and (b) demonstrates the operation of the current
sharing controller with nonlinear loads. Fig. 24(a) shows the
phase-A currents of both inverters, during step application of
3012 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 12, DECEMBER 2010
Fig. 20. Output currents from all phases of two inverters superimposed; load
transient applied at 0.04 s and 0.06 s.
Fig. 21. Experimental setup.
Fig. 22. Steady-state response of voltage controller. (a) v
o
with k
c
= 0. (b) v
o
(blue) and v
o

(red) for k
c
= 3.
Fig. 23. Voltage controller results. (a) Step response of voltage controller with
initial transients. (b) Transients at application of full load.
Fig. 24. Current sharing for phase-A. (a) Current sharing for phase-A during
switching ON of rectier load. (b) Current sharing for phase-A during increase
in load.
SHAH AND SENSARMA: THREE DEGREE OF FREEDOM ROBUST 3013
full load. It is observed that the load currents are shared equally
even during severe load transients. Fig. 24(b) shows the same
waveform for an intermediate load step.
IV. CONCLUSION
The use of three phase parallel inverters as an interfacing
link between grid and nonconventional energy sources have
been presented in this paper. A unied 3-DOF robust voltage
control scheme for output voltage tracking and instantaneous
current sharing was introduced. Modeling of parametric uncer-
tainties of plant using LFT was presented and robustness of
-analysis-based designed controller against such perturbations
was analyzed. The effect of sampling delays in feedback loops
on stability was analyzed in terms of SSV(). The generalized
platform to analyze different compensating schemes for various
kind of delays, which is crucial for distributed generation sys-
tems, was presented. The lead compensators for sampling delays
were proposed, which allows the stable operation of inverters at
lower switching frequencies. The dynamics of circulating cur-
rents were studied using proposed perturbed plant model of the
system. It was established that the current controller acts directly
as an impedance to circulating current, and it can be designed
to suit the specications of instantaneous current sharing. The
stability of perturbed network was analyzed using branch ad-
mittance Y
i
in presence of parametric uncertainties. Following
conclusions were drawn from analysis.
1) The low-bandwidth controllers designed based on clas-
sical stability margins are not suitable for operation of
inverters at low switching frequencies. The -analysis-
based controller takes into account the multiloop structure
and are robust toward uncertainties in lter parameters.
2) The destabilizing effect of delays in feedback loops can
be reduced substantially by proper inclusion of compen-
sators in loop. The performance of such system with mul-
tiple compensators can be evaluated in terms of structured
singular value ().
3) The constant gain k
corr
of outer-loop current controller
acts as high resistance to circulating currents, and it de-
creases and equalizes themresulting in truly instantaneous
current sharing.
The experimental validation of all analytical and simulation
studies comprehensively demonstrate the effectiveness and re-
alizability of the proposed scheme.
ACKNOWLEDGMENT
The authors would like to acknowledge Department of In-
formation Technology for their support and the nodal agency
CDAC, Thiruvananthapuram. They would also like to acknowl-
edge Mr. A. Basu and Mr. Nandkishor for their support toward
hardware development.
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Shahil Shah received the B.E. degree from the Gov-
ernment Engineering College, Gandhinagar, India, in
2006, and the M.Tech. degree from the Indian In-
stitute of Technology (IIT), Kanpur, India, both in
electrical engineering.
In 2006, he was a Postgraduate student at the IIT,
Kanpur, where he was engaged in research on micro-
grid, using nonconventional energy sources. This in-
cludes the parallel operation of uninterruptible power
supply to form a microgrid, using renewable energy
sources. The project was supported by Centre for De-
velopment of Advanced Computing, Trivandrum, India. He is currently a Sci-
entic Ofcer at the Bhabha Atomic Research Centre, Mumbai, India, where
he is engaged in research on high-voltage MARX generator systems and pulse
modulator supplies for linear induction accelerators.
Partha Sarathi Sensarma (M00) received the
B.E.E. degree from Jadavpur University, Calcutta,
India, in 1990, the M.Tech degree from the Indian
Institute of Technology (IIT), Kharagpur, India, in
1992, and the Ph.D. degree from the Indian Institute
of Science, Bangalore, India, in 2001, all in electrical
engineering.
He was with the Bharat Bijlee Ltd., Thane, In-
dia, CESC Ltd., India, and ABB Corporate Research,
Baden-Daettwil, Switzerland, where he was a Staff
Scientist with the Power Electronics Department.
Since 2002, he has been with the Department of Electrical Engineering, IIT,
Kanpur, where he is currently an Associate Professor. He is actively involved
in research, design, and deployment of power electronic interfaces for wind
energy-based power plants as well as grid-interactive and islanded solar pho-
tovoltaic plants. His other research interests include power quality, exible ac
transmission system devices, power supplies, and motor drives.