KE40703

COMPUTER ARCHITECTURE AND NETWORK

COMP. ARCHITEC LAB 4

COMPUTER ARCHITECTURE LAB 4

Outcomes Students should be able 1) to understand the Datapath Module of computer architecture. 2) to write a test-bench for the Datapath module. 3) to analyse the function of the Datapath in microprocessor.

Introduction

PC+1 1 0

PC_inc

16 Rs2
PC
ReadPC_1 ReadPC_2

Rs1

Mux1_out

WritePC
WriteR1

R0 R1 R2

ReadR0_2

ReadR0_1

Rd
WriteR2

ReadR1_2

ReadR1_1

16

ReadR2_2

ReadR2_1

16

Zero

16

WriteR3

R3
ReadR3_2

ReadR3_1

LoadDR

16 DR 1 nTrisRd 0

Rs2_sel
Mux2_out

ALU

result

Function

16

TrisRd

16

TrisRs2

TrisALU TrisPC

Fig. 1. Processor Datapath Module Architecture

KE40703

COMPUTER ARCHITECTURE AND NETWORK

COMP. ARCHITEC LAB 4

The following are the main task of datapath unit that has to be behaviourally model by verilog code to suit the definition of design processor as can be view in figure 1: 1. 2. 3. To model the read operation for both Rs1 (source1 register) and Rs2 (source2 register) from any one of 5 available register (R0, R1, R2, R3, PC). To model the write operation for Rd (destination register) from any one of 4 available register (R1, R2, R3, PC). To model the tri-state buffer (TrisALU, TrisPC, TrisRs2, TrisRd) for system bus.

Experiment #1 Datapath Module 1. Create datapath.v in a text editor using the following Verilog Code and add into Project.
`include "opcodes.v" `timescale 100ps / 10ps module datapath( Sysbus, Zero, Function, TrisALU, TrisPC, TrisRs2, TrisRd, nTrisRd, Clock, nReset, ReadPC_1, ReadPC_2, ReadR0_1, ReadR0_2, ReadR1_1, PC_inc, ReadR1_2, ReadR2_1, ReadR2_2, ReadR3_1, ReadR3_2, PC_inc, WriteR1, WriteR2, WriteR3, Rs2_sel, LoadDR, LoadPC); inout [15:0] Sysbus; output Zero; input [2:0] Function; input TrisALU, TrisPC, TrisRs2, TrisRd, nTrisRd, Rs2_sel, ReadPC_1, ReadPC_2, ReadR0_1, ReadR0_2, ReadR1_1, ReadR1_2, ReadR2_1, ReadR2_2, ReadR3_1, ReadR3_2, PC_inc, WriteR1, WriteR2, WriteR3, LoadDR, LoadPC; input Clock, nReset; reg [15:0] PC, R1, R2, R3, R0, DR; wire Zero; wire [15:0] Rd, Rs1, Rs2, result; wire [15:0] Mux2_out, Mux1_out; assign assign assign assign assign Rs1 Rs1 Rs1 Rs1 Rs1 = = = = = ( ( ( ( ( ReadPC_1) ReadR0_1) ReadR1_1) ReadR2_1) ReadR3_1) ? ? ? ? ? PC R0 R1 R2 R3 : : : : : 16'bz; 16'bz; 16'bz; 16'bz; 16'bz;

KE40703

COMPUTER ARCHITECTURE AND NETWORK

COMP. ARCHITEC LAB 4

assign assign assign assign assign

Rs2 Rs2 Rs2 Rs2 Rs2

= = = = =

( ( ( ( (

ReadPC_2) ReadR0_2) ReadR1_2) ReadR2_2) ReadR3_2)

? ? ? ? ?

PC R0 R1 R2 R3

: : : : :

16'bz; 16'bz; 16'bz; 16'bz; 16'bz;

always @(posedge Clock) begin if (LoadPC) PC = Mux1_out; if (WriteR1) R1 = Rd; if (WriteR2) R2 = Rd; if (WriteR3) R3 = Rd; if (LoadDR) DR = Sysbus; end assign Mux2_out = ( Rs2_sel ) ? Rs2 : DR; assign Zero = (result == 0); assign Mux1_out = ( PC_inc ) ? PC + 1 : Rd; assign Rd = (TrisRd ) ? Sysbus : 16'bz; assign Rd = (nTrisRd) ? result : 16'bz; assign Sysbus = ( TrisALU ) ? result : 16'bz; assign Sysbus = ( TrisPC ) ? PC : 16'bz; assign Sysbus = ( TrisRs2) ? Rs2 : 16'bz; always @(nReset) if (!nReset) begin assign PC = 0; assign R1 = ; assign R2 = ; assign R3 = ; assign DR = ; assign R0 = ; end else begin deassign PC; deassign R1; deassign R2; deassign R3; deassign DR; end endmodule

2.

Save the Verilog Code.

3.

Right click on the Project Window and select Add to Project Existing File

KE40703

COMPUTER ARCHITECTURE AND NETWORK

COMP. ARCHITEC LAB 4

4. 5.

Browse your File and Select Copy to Project Directory at the bottom then click OK. Select the file and compile it.

Experiment #2 Test bench and analysis of Datapath Module

1. Create a test bench to verify the functionality of datapath module and save it as datapath_tst.v. 2. Select all the files and compile it. 3. Select the test bench and simulate it. 4. Add Waveform to the window and then verify the design. Save the waveform in Drawing Tools Software. Include all results in your report. 5. From the waveform obtained, analyze the functionality of control unit based on the Computer Architecture Theory. 6. Describe and discuss any problems encountered of the design. Login to http://www.ke26604.webs.com to complete the report and results submission. All results must be in a document format. Please ask the instructions from lab demonstrator. 7. All report must be submit before end of the lab. Late submission will NOT BE accepted automatically. 8. YOU ARE REQUIRED TO SUBMIT A FULL REPORT AND DISCUSSION INCLUDING ALU, CONTROL UNIT, DATAPATH, AND OPCODES AT THE END OF THE LAB.