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Unit 2

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UNIT 2

Counter

OBJECTIVES

General Objective:
Distinguish between the asynchronous and synchronous counters.

Specific Objectives:
At the end of this unit, you should be able to:

state that the basic counter circuit can be constructed using JK and T flip-flop. describe the operation of the asynchronous counter. draw the circuit diagram and timing diagram of the asynchronous counter. analyze the design of the asynchronous counter circuit. describe the operation of the synchronous counter. draw the circuit diagram, truth table and timing diagram of the synchronous counter. state the applications of multi-stage counter. analyze the design of the synchronous counter circuit. analyze the design of the synchronous counter using Karnaugh Map. state the applications of IC counter.

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INPUT INPUT

2.0 INTRODUCTION
One common requirement in digital circuits is counting, both forward and backward. Digital clocks and watches are everywhere, timers are found in a range of appliances from microwave ovens to VCRs, and counters for other reasons are found in everything from automobiles to test equipment. Although we will see many variations on the basic counter, they are all fundamentally very similar. In this unit, we will examine the different types of asynchronous and synchronous counters.

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2.1 Basic Counter Circuit

There are basically two types of counter; asynchronous and synchronous. In a asynchronous counter, each flip-flop does not trigger exactly in step with the clock pulse. On the contrary, all flip-flops in a synchronous counter will trigger simultaneously. The basic counter circuits can be built using T flip-flops or JK flip-flops. The figure below shows the circuit of a basic counter using the above mentioned flipflops.

Figure 2.1: Counter circuit forms by JK flip-flop

Figure 2.2: Counter circuit forms by T flip-flop

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2.2 Asynchronous Counter

Most of the flip-flops of an asynchronous counter are not connected to the clock signal, and therefore the flip-flops do not change state in sync with the master clock signal. To better understand this distinction, let us examine some of the different types of asynchronous counters.

2.2.1 Frequency Divider

You are already aware that counters are used as frequency dividers in digital time-pieces, such as electronic digital clocks, automobile digital clocks, and digital wristwatches. Frequency division is also used in frequency counters, oscilloscopes, and television servicing dot-and-bar generators. A two bit asynchronous counter acts as a frequency divider is illustrated in Figure 2.3. The external clock is connected to the clock input of the first flip-flop (FF 0) only. So, FF 0 changes state at the falling edge of each clock pulse, but FF 1 changes only when triggered by the falling edge of the Q output of FF 0. Because of the inherent propagation delay through a flip-flop, the transition of the input clock pulse and a transition of the Q output of FF 0 can never occur at exactly the same time. Therefore, the flip-flops cannot be triggered simultaneously, producing an asynchronous operation. Note that for simplicity, the transitions of Q 0, Q1 and CLK in the timing diagram below (Figure 2.4) are shown as simultaneous even though this is an asynchronous counter.

FF 0

FF 1

Figure 2.3: The circuit of a Frequency divider

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CLK
Q0 Q1

fin
fin 2 f in 4

Figure 2.4: Timing diagram of the frequency divider

The output frequency Q 0 has become half of the input clock frequency. Meanwhile the output frequency at Q 1 will become one fourth of the input clock frequency, (
fin ) . This is due to the division of the clock frequency at the first 4

flip-flop. Therefore, one flip-flop divides by 2, two flip-flops divide by 4, 3 flipflops divide by 8, and so on. The frequency division performed by a counter circuit can be calculated with the following formula; Division Factor = 2n , where n = the number of flip-

Example 2.1 Calculate the following for a 5-bit asynchronous counter :a. maximum count b. Modulus c. division factor

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Solution to Example 2.1 a. The 5-bit asynchronous counter consists of five flip-flops. Therefore, the maximum number that can be counted is
N = 2n 1 = 25 1 =31 (11111 ) 2

b. c.

Mod = 2 n = 2 5 = 32.

2 n = 2 5 = 32.

2.2.2 Asynchronous Binary Up Counter

Consider the three-stage circuit of Figure 2.5 using JK flip-flops connected in the toggle mode.

FF A

FF B

FF C

Figure 2.5: Asynchronous three-stage up counter

Assume that all outputs are initially reset to zero by an input going low in the clear line prior to the input signal appearing. If the JK flip-flops are master-slave, then the input pulse to FF A will have no effect on the Q A output until the pulse changes from logic 1 to logic 0 level. However, the output Q B remains at 0 since the input pulse to FF B has gone from 0 to 1. Similarly, Q C will remain at 0.

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Figure 2.6: Timing diagram of the asynchronous three-stage up counter

When the second input pulse has arrived and gone from logic 1 to logic 0, then FF A output again changes state and returns to 0. However, this is a negative transition and as such will cause the output of FF B to toggle so that Q B goes to 1. Since this is a positive transition QC wil be unaffected and remains at 0. At the end of the third input pulse, Q A again toggles, this time to logic 1 but Q B and QC retain their values of 1 and 0 respectively. At the end of the fourth input pulse, QA toggles and falls to 0. The transition from 1 to 0 at the input to FF B causes QB to fall to 0 and this transition in turn causes FF C to toggle so that QC goes to 1. The procedure repeats until the counter reset itself and begins to repeat the count should the input signals still be present. Since the counter counts up from 0 to its maximum value, in this case of 7, the counter is known as an up-counter.

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Example 2.2 Determine the MOD number of the counter in figure below. Also determine the frequency at the D output.

Assume all J, K inputs are HIGH

Solution to Example 2.2 This is a 4-bit counter, which would normally count from 0000 through 1111. The NAND inputs are QD, QC and QB, which means that the counter will immediately recycle to 0000 when the 1110 (decimal 14) count is reached. Thus, the counter actually has 14 stable states 0000 through 1101 and is therefore a MOD-14 counter. Since the input frequency is 30kHz, the frequency at output D will be
30kHz 14 = 2.14kHz

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2.2.3 Asynchronous Binary Down Counter

Figure 2.7: Asynchronous three-stage down counter

Since the flip-flops used have outputs that are complementary it follows that if the counter were initially preset (i.e. all Q outputs set to 1) the
Q

must be 0 and if

these outputs were used to trigger the following stage then a down-counter could be produced. Figure 2.7 shows how a three-stage asynchronous binary down counter circuit can be constructed with three JK flip-flops. The input pulses are applied to the FF A. The input for the FF B; the
Q

of FF A serves as the CLK

of FF B serves as the CLK input for the FF C. The

waveforms at FF A, FF B and FF C show that FF B toggles whenever FF A goes from 0 to 1 and FF C toggles whenever FF B goes from 0 to 1. This results in the desired down-counting sequence at the QA, QB and QC. The clock input and Q output waveforms for this 3-bit binary down counter are shown in Figure 2.8.

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Figure 2.8: Timing diagram of the asynchronous three-stage down-counter

2.2.4 Asynchronous Binary Up-Down Counter

In certain applications a counter must be able to count both up and down. The circuit in Figure 2.9 is a 3-bit up-down counter. It counts up or down depending on the status of the control signals UP and DOWN. When the UP input is at 1 and the DOWN input is at 0, the NAND network between FF0 and FF1 will gate the noninverted output (Q) of FF0 into the clock input of FF1. Similarly, Q of FF1 will be gated through the other NAND network into the clock input of FF 2. Thus the counter will count up.

Figure 2.9: Asynchronous up-down counter

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When the control input UP is at 0 and DOWN is at 1, the inverted outputs of FF 0 and FF 1 are gated into the clock inputs of FF 1 and FF 2 respectively. If the flip-flops are initially reset to 0's, then the counter will go through the following sequence as input pulses are applied as shown in Table 2.1.

FF 0 FF 1 FF 2 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 0 1 0 0 0 1

Table 2.1: Sequence output of 3-bit Up-Down counter

Notice that an asynchronous up-down counter is slower than an up counter or a down counter because of the additional propagation delay introduced by the NAND networks.

No day in which you learn something is a complete loss. No day in which you learn something is a complete loss. - David Eddings - David Eddings

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Activity 2A

TEST YOUR UNDERSTANDING BEFORE YOU PROCEED TO THE NEXT INPUT..! 2.1 What type of flip-flops is needed to form a counter?

2.2

State whether the statement is true or false:

In an asynchronous counter, all flip-flops change states at the same time.

2.3

What is the difference between the counting sequence of an up counter and a down counter?

2.4

Find the value of the output frequency, f out if fin = 15kHz in each of the following asynchronous counters. a. 6-bit b. 5-bit c. MOD-10

2.5 2.6

What is a presettable counter? Design a MOD-16 asynchronous down counter using T flip-flop.

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Feedback To Activity 2A

2.1 2.2 2.3

A flip-flop that can toggle such as, T flip-flop and JK flip-flop. False. In an up counter, the count is increased by 1 with each clock pulse; in a down counter, the count is decreased by 1 in each pulse.
f 15 10 fout = in n = 6 2 2 3

2.4

a.

= 234.675Hz

b.

f 15 10 fout = in n = 5 2 2

= 468.75Hz

c.

f 15 10 fout = in n = 2 10

= 1.5kHz

2.5 2.6

It can be preset to any desired starting count.

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INPUT INPUT

2.3 Synchronous Counter

A synchronous counter is an arrangement of flip-flops and logic gates in which all flip-flops are clocked simultaneously. The advantage is that a synchronous counter does not suffer false states during its output sequence. On the other hand, there is a requirement for extra gates between flip-flops to produce the correct sequence.

2.3.1 Synchronous Binary Up Counter

Figure 2.10 shows how three JK flip-flops and one AND gate can be connected to form a 3-bit synchronous binary up counter. All of the flip-flops clock inputs are connected to the same common CLK signal. This parallel connectiom makes the counter synchronous, since all of the flip-flops will operate in step with the input clock signal.

Figure 2.10: 3-bit Synchronous counter

The synchronous binary up counter shown in Figure 2.10 will operate as follows. J and K inputs of FF0 are tied HIGH, and therefore the Q 0 output will

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continually toggle, like a single-stage asynchronous counter. This fact is verified by looking at the Q0 waveform in Figure 2.11, which shows how the Q0 output continually alternates HIGH and LOW. The J and K inputs of FF1 are controlled by the divide-by-two output of FF0. This means that when Q 0 is LOW, the Q1 output of FF1 will not change; however, when Q0 is HIGH, the Q1 output of FF1 will toggle. This action can be confirmed by referring to the Q 1 waveform in Figure 2.11, which shows that when the Q0 output goes HIGH, the Q1 output will toggle or change state on the next positive edge clock signal. The J and K inputs of FF2 are controlled by the ANDed outputs of Q0 and Q1. This means that only when Q0 and Q1 are both HIGH will the output of AND gate be HIGH, and this HIGH will enable FF2 to toggle. Referring to the Q2 waveform in Figure 2.11, you will notice that only when Q 0 and Q1 are HIGH will Q2 toggle or change state on the next positive edge of the clock.

Q0 Q1 Q2
Figure 2.11: Timing diagram of 3-bit synchronous counter

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2.3.2 Synchronous Binary Down Counter

In section 2.2.3, we noticed that a asynchronous counter could be made to count down by using the inverted output of each flip-flop to drive the next flip-flop in the counter. A synchronous down counter can be constructed in a similar manner, that is, by using the inverted flip-flop outputs to drive the following J, K inputs. Figure 2.12 illustrates the counter.

Figure 2.12: 3-bit synchronous down counter

Figure 2.13: Timing diagram of the synchronous three-stage down-counter

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2.4 Cascaded Connection

Counters can be connected in cascade to achieve higher modulus operation. In essence, cascading means that the last-stage output of one counter drives the input of the next counter. An example of two counters connected in cascade is shown for a 2 bit and a 3 bit counter in Figure 2.14 and Figure 2.15. Propagation delay will occur if the synchronous counter is connected in cascaded arrangement. To overcome this problem, an input which is known as Enable Input is to be added in most of the IC synchronous counter. It is illustrated in Figure 2.16. The main function of the enable input is to enable the counting process.

Figure 2.14: Cascaded connection for MOD-4 and MOD-8 counter

Figure 2.15: Cascaded connection (in IC configuration) for MOD-4 and MOD-8 counter

Figure 2.16: Synchronous Counter in cascaded connection.

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Example 2.3 Determine the overall modulus of the two cascaded counter configurations in figure below.
CTR DIV 8 CTR DIV 12 CTR DIV 16

(a)

CTR DIV 10

CTR DIV 4

CTR DIV 7

CTR DIV 5

(b)

Solution to Example 2.3 (a) The overall modulus for the 3-counter configuration is 8 x 12 x 16 = 1536 (b) The overall modulus for the 4-counter configuration is 10 x 4 x 7 x 5 = 1400

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2.5 Synchronous Counter Design

Many different counter arrangements are available as ICs. Most of these counts are in a normal binary sequence although their counting sequences can be somewhat altered using some techniques. There are situations, however, where a counter is required that follows a sequence that is not counting in normal binary, for example 000, 010, 101, 001, 110, 000,.. We will now go through a complete synchronous counter design procedure. Although we will do it for a specific counting sequence, the same steps can be followed for any desired sequence. i. Determine the desired number of bits (FFs) and the desired counting sequence. For this example, we will design a 3-bit counter that goes through the sequence shown in Table 2.2. Notice that this sequence does not include the 101, 110, and 111 states. We will refer to these states as undesired states. C 0 0 0 0 1 0 0 B 0 0 1 1 0 0 0 A 0 1 0 1 0 0 1

Table 2.2: State transition table for a 3-bit synchronous counter

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ii.

Draw the state transition diagram showing all possible states, including those that are not a part of the desired counting sequence. For example, the state transition diagram appears as shown in Figure 2.17. The 000 to 100 states are connected in the expected sequence. The new idea used in this diagram is the inclusion of the undesired states. They must be included in this design in case of the counter accidentally gets into one of these states upon power-up or due to noise. The circuit designer can choose to have each of these undesired states go to any state upon the application of the next clock pulse. We choose to have them all go to the 000 state from which the correct sequence will be generated.

Figure 2.17: State transition diagram for the synchronous counter design example.

iii.

Use the state transition diagram to set up a table that lists all PRESENT states and their NEXT states. As shown in Table 2.3, the left hand portion of the table lists every possible state, even those that are not the part of the sequence. We label these as the PRESENT states. The right hand portion lists the NEXT state for each PRESENT state.

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Line 1 2 3 4 5 6 7 8

PRESENT state NEXT state C B A C B A 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0

Table 2.3: State transition table for 3-bit synchronous counter

These are obtained from the state transition diagram in Figure 2.17. For instance, line 1 shows that the PRESENT state of 000 has the NEXT state of 001, and line 5 shows that the PRESENT state of 100 has the NEXT state of 000. Lines 6, 7 and 8 show that the undesired PRESENT states 101, 110, and 111 all have the NEXT state of 000. iv. Add a column to this table for each J and K input. For each PRESENT state, indicate the levels required at each J and K input in order to

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produce the transition to the NEXT state. Our design example uses three FFs ( C, B and A ) and each one has a J and a K input. Therefore, we must add six new columns as shown in Table 2.4. This completed table is called the circuit excitation table. The six new columns are the J and K inputs of each FF. The entries under each J and K are obtained by using Table 2.5, the JK flip-flop excitation table.

PRESENT state NEXT state Line 1 2 3 4 5 6 7 8 C 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 A 0 1 0 1 0 1 0 1 C 0 0 0 1 0 0 0 0 B 0 1 1 0 0 0 0 0 A 1 0 1 0 0 0 0 0

Flip-flops JC KC JB KB JA KA 0 x 0 x 1 x 0 x 1 x x 1 0 x x 0 1 x 1 x x 1 x 1 x 1 0 x 0 x x 1 0 x x 1 x 1 x 1 0 x x 1 x 1 x 1

Table 2.4: Excitation table for 3-bit synchronous counter

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Transition at Output 0 0 0 1 1 0 1 1

PRESENT State, Q(N) 0 0 1 1

NEXT State, Q(N+1) 0 1 0 1

J 0 1 x x

K x x 1 0

Table 2.5: JK flip-flop excitation table

Let us look at line 1 in Table 2.4. The PRESENT state of 000 is to go to the NEXT state of 001 on the occurrence of a clock pulse. For this state transition, the C flip-flop goes from 0 to 0. From the JK excitation table, we see that JC must be at 0 and KC at x for this transition to occur. The B flip-flop also goes from 0 to 0, and so J B = 0 and KB = x. The A flip-flop goes from 0 to 1. Also from Table 2.5, we can see that JA = 1 and KA = x for this transition. The required J and K levels for all other lines in Table 2.4 can be determined in the same manner. b. Design the logic circuit to generate the level required at each J and K input. Table 2.4, the circuit excitation table, lists six J, K inputs ( J C, KC, JB, KB, JA, KA ). We must consider each of these as an output from its own logic circuit with inputs from flip-flops C, B and A. Then we must design the circuit for each one. Lets design the circuit for J A. To do this we need to look at the PRESENT states of C, B and A and the desired levels at JA for each case. This information has been extracted from Table 2.4 and presented in Figure 2.18. This truth table shows the desired level at JA for each PRESENT state. Of course, for some cases, JA is a dont care. To develop the logic circuit for J A, we must first determine its expression in terms of C, B and A. We will do this by transferring the truth table information to a three-variable

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Karnaugh map (K-map) and performing the K-map simplification as in Figure 2.18. PRESENT C B A 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

JA 1 x 1 x 0 x 0 x

Figure 2.18: Excitation table and K-map for JA

There are only two 1s in this K-map, and they can loop to obtain the term
A C

, but if we use the dont-care conditions at

C

A B C

and

A B C

as

1s, we can loop a quad to obtain the simpler term expression is

J A =C

. Thus, the final

Now lets consider KA. We can follow the same step as we did for JA. However, the entries under KA in the circuit excitation table shows only 1s and

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dont cares. If we change all the dont cares to 1s, then K A is always a 1. Thus, the final expression is
K A =1

In a similar manner, we can derive the expressions for J C, KC, JB, and KB. The K maps for these expression are given in Figure 2.19.

Figure 2.19: K mappings for JC, KC, JB and KB logic circuits.

c.

Implement the final expressions. The logic circuits for each J and K input are implemented from the expressions obtained from the K mapping. To complete synchronous counter design is implemented in Figure 2.20. Note that all FFs are clocked in parallel.

Figure 2.20: Final implementation of the synchronous counter design example.

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2.6 Applications of IC Counter

There are several TTL and CMOS asynchronous counter ICs. The most common IC counters that are widely being used are 7490 (Decade counter), CD4022 (Octal counter), and 7493 (4-bit binary counter).

2.6.1 4-bit Binary Counter

Now, we are going to cover a 4-bit binary counter IC which is 7493. The diagram for 7493 is shown in Figure 2.21.

Figure 2.21: Block Diagram and Pin Configuration of a 4-bit binary counter IC (7493)

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By referring to Figure 2.21, you will note the following points :i. The 7493 has four JK flip-flops with outputs Q0 , Q1, Q2 , Q3 , where Q0 is the LSB (least significant bit) and Q3 is the MSB (most significant bit). The FFs are shown arranged with the LSB on the left. This is done to satisfy the convention that the circuit input signals appear on the left. We have been drawing our counters with the LSB on the right so that the order of the FFs is the same as the order of the bits in the binary count. ii. Each FF has a CP (clock pulse) input, which is just another name for the CLK input. The clock inputs to Q0 and Q1, labeled
CP0

and CP 1

respectively, are externally accessible. The inversion bars over these inputs indicate that they are activated by a NGT ( Negative-going transition ). iii. Each FF has an asynchronous clear input (CLR). These are connected together to the output of a two-input NAND gate with inputs MR 1 and MR2, where MR stands for master reset. Both MR inputs must be HIGH to clear the counter to 0000. iv. Flip-flops Q1, Q2, and Q3 are already connected as a 3-bit asynchronous counter. Flip-flop Q0 is not connected to anything internally. This allows the user has the option of either connecting Q 0 to Q1 to form a 4-bit counter or using Q0 separately if desired.

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Example 2.4 Show how the 7493 should be connected to operate as a MOD-16 counter with a 10kHz clock input. Solution to Example 2.4 A MOD-16 counter requires four FFs, and so we must connect the Q 0 output to CP 1 , the clock input of flip-flop Q1 (see Figure 2.22). The 10kHz pulses are applied to
CP0

, the clock input of Q0. The output, fout is taken at Q3.

f 10kHz fout = in = = 625Hz 16 16

Figure 2.22: 7493 wired as a MOD-16 counter

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2.6.2

Decade Counter
A commercially available decade counter is the 7490. This circuit is
a 2

internally divided into two section giving

and

a 5

representation. The

circuit arrangement is shown in Figure 2.23.

Figure 2.23: 7490 decade counter

Example 2.5 Show how the 7490 can be connected to operate as MOD-6 counter. Solution to Example 2.5 A MOD-6 counter could be produced using the circuit of Figure 2.24. The connections from QB and QC to the R0(1) and R0(2) inputs respectively produced a reset counter without the need for an external gate since the gate is internal to the 7490 chip. In this case, QB = QC = 1 uniquely on the count of 6 so, giving a reset after the binary equivalent of decimal 6 has appeared on the output lines for a short period of time.

Figure 2.24: MOD-6 counter using the 7490.

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2.6.3

Octal Counter
The CD4022 is a 4 stage divide-by-8 counter with 8 decoded outputs and a

carry out bit. This counter is cleared to its 0 count by a logical 1 on its RESET line. The counter is advanced on the positive-edge of the clock signal when the CLOCK ENABLE signal is in the logical 0 state. The pin assignment and the logic diagram of the CD4022 can be shown in Figure 2.25 and Figure 2.26 respectively.

Figure 2.25: Pin assignment for IC CD4022

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Figure 2.26: Logic diagram of Octal Counter IC (CD4022)

One of the secrets of life is to make stepping stones of stumbling blocks. One of the secrets of life is to make stepping stones of stumbling blocks. - Jack Penn - Jack Penn

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Activity 2B

2.7

Clock inputs are connected in ______________ (parallel, serial) on a synchronous counter.

2.8

List down the steps according to the procedure of designing a synchronous counter.

2.9

What information contains in the circuit excitation table?

2.10

State whether the statement is true or false. The synchronous counter design procedure can be used for the following sequence: 0010, 0011, 0100, 0111, 1010, 1110, 1111 and repeat.

2.11

Write the truth table for the counter shown below.

2.12

What is the primary advantage of a synchronous counter? (a) high counting speed (b) long propagation delay (c) circuit simplicity (d) ripple action

2.13 Why are counters cascaded ?

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Feedback To Activity 2B

2.7 2.8

Parallel. Step 1: Determine the desired number of flip-flop and the desired counting sequence. Step 2: Draw the state transition diagram showing all possible states, including those that are not part of the desired counting sequence. Step 3: Use the state transition diagram to set up a table that lists all PRESENT states and their NEXT states. Step 4: Add a column to this table for each J and K input. For each PRESENT state, indicate the levels required at each J and K input in order to produce the transition to the NEXT state. Step 5: Design the logic circuits ti generate the levels required at each J and K input. Step 6: Implement the final expressions.

2.9

It shows the necessary level at each flip-flops J and K input to produce the counters state transitions.

2.10 2.11

True.

MOD-4 up counter

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2.12 2.13

(a) To gain a higher modulus counter.

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KEY FACTS

1. In synchronous counters, the clock inputs of all the the flip-flops are connected together and are triggered by the input pulses. Thus, all the flipflops change state simultaneously. 2. In asynchronous counters, each flip-flop does not trigger exactly in step with the clock pulse. 3. The frequency division of the asynchronous counter can be expressed as

f out =
4.

f in 2n

where n = the number of flip-flops

Counters can be cascaded to obtain a higher modulus.

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SELF-ASSESSMENT 2

You are approaching success. Try all the questions in this self-assessment section and check your answers with those given in the Feedback on SelfAssessment 2 on the foolowing page. If you face any problems, discuss it with your lecturer. Good luck! Question 2-1 a. b. Design a counter that has a modulo of 7 using JK flip-flop. A 5-bit asynchronous counter has an input clock pulse 8MHz. Find the value of the frequency for the last flip-flop. Question 2-2 a. Draw a circuit diagram of a MOD-16 counter operating synchronously with JK flip-flops. Show, by using the truth table, the transitions that occur at each flip-flop output for the complete count. Assume that the flip-flops are triggered on the positive edge of the clock waveform. b. c. d. e. Show how the 7490 should be connected to operate as a MOD-1000 counter. Draw a decade counter using T flip-flop. Draw the block diagram of MOD-6 synchronous counter using MOD-2 and MOD-3 counter. Construct a state transition table for question (d).

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Feedback To Self-Assessment 2

Answer for Question 2-1 a.

b.

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Answer for Question 2-2 a.

CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0

C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

B 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

A 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

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b.

c. d.

250kHz.

CLK Q2 Q1 Q0 0 0 0 0 1 0 0 1 2 0 1 0 3 0 1 1 4 1 0 0 5 1 0 1 6 0 0 0

e.

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Educations purpose is to replace an empty mind to an open one. Educations purpose is to replace an empty mind to an open one. - Malcolm S. Forbes - Malcolm S. Forbes