MTW14N50E

Preferred Device

Power MOSFET 14 Amps, 500 Volts

NChannel TO247
This high voltage MOSFET uses an advanced termination scheme to provide enhanced voltageblocking capability without degrading performance over time. In addition, this advanced Power MOSFET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a draintosource diode with a fast recovery time. Designed for high voltage, high speed switching applications in power supplies, converters and PWM motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. Robust High Voltage Termination Avalanche Energy Specified SourcetoDrain Diode Recovery Time Comparable to a Discrete Fast Recovery Diode Diode is Characterized for Use in Bridge Circuits IDSS and VDS(on) Specified at Elevated Temperature Isolated Mounting Hole Reduces Mounting Hardware
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating DrainSource Voltage DrainGate Voltage (RGS = 1.0 M) GateSource Voltage Continuous Drain Current Continuous Drain Current Continuous @ 100C Drain Current Single Pulse (tp 10 s) Total Power Dissipation Derate above 25C Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy Starting TJ = 25C (VDD = 50 Vdc, VGS = 10 Vpk, IL = 14 Apk, L = 8.8 mH, RG = 25 ) Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS Value 500 500 20 14 9.0 60 180 1.44 55 to 150 860 Unit Vdc Vdc Vdc Adc Apk Watts W/C C mJ 1 Gate 2 Drain RJC RJA TL 0.7 40 260 C/W C LL Y WW = Location Code = Year = Work Week 3 Source MTW14N50E LLYWW

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14 AMPERES 500 VOLTS RDS(on) = 400 m

NChannel D

G S 4 TO247AE CASE 340K Style 1 1 2 3

MARKING DIAGRAM & PIN ASSIGNMENT

4 Drain

ORDERING INFORMATION
Device MTW14N50E Package TO247 Shipping 30 Units/Rail

Preferred devices are recommended choices for future use and best overall value.

Semiconductor Components Industries, LLC, 2000

November, 2000 Rev. 5

Publication Order Number: MTW14N50E/D

MTW14N50E
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DrainSource Breakdown Voltage (VGS = 0 V, ID = 250 Adc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 500 Vdc, VGS = 0) (VDS = 500 Vdc, VGS = 0, TJ = 125C) GateBody Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 1.) Gate Threshold Voltage (VDS = VGS, ID = 250 Adc) Temperature Coefficient (Negative) Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.0 Adc) DrainSource OnVoltage (VGS = 10 Vdc) (ID = 14 Adc) (ID = 7.0 Adc, TJ = 125C) Forward Transconductance (VDS = 15 Vdc, ID = 7.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Notes 1. & 2.) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 400 Vdc, ID = 14 Adc, VGS = 10 Vdc) (VDD = 250 Vdc, ID = 14 Adc, VGS = 10 Vdc, Vdc RG = 4.7 ) td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS (Note 1.) OnVoltage Forward On Voltage Reverse Recovery Time (IS = 14 Adc, VGS = 0, dIS/dt = 100 A/s, VGS = 0) Reverse Recovery Stored Charge INTERNAL PACKAGE INDUCTANCE Internal Drain Inductance (Measured from the drain lead 0.25 from package to center of die) Internal Source Inductance (Measured from the source lead 0.25 from package to source bond pad) 1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%. 2. Switching characteristics are independent of operating junction temperature. LD LS 5.0 13 nH nH (IS = 14 Adc, VGS = 0) (IS = 14 Adc, VGS = 0, TJ = 125C) VSD trr ta tb QRR 1.0 0.9 390 245 145 5.35 1.6 C Vdc ns 28 80 80 60 65 17 47 34 60 160 160 120 85 nC ns (VDS = 25 Vdc, Vd VGS = 0 0, f = 1.0 MHz) Ciss Coss Crss 2510 280 67 3510 392 94 pF VGS(th) 2.0 RDS(on) VDS(on) gFS 5.0 6.7 5.6 mhos 3.2 7.0 0.32 4.0 0.40 Vdc mV/C Ohm Vdc V(BR)DSS 500 IDSS IGSS 250 1000 100 nAdc 520 Vdc mV/C Adc Symbol Min Typ Max Unit

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RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

TYPICAL ELECTRICAL CHARACTERISTICS

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RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

MTW14N50E

MTW14N50E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. The resistive switching time variation versus gate resistance (Figure 10) shows how typical switching performance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most power electronic loads are inductive; the data in the figure is taken with a resistive load, which approximates an optimally snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces switching losses.

8000 7000 C, CAPACITANCE (pF) 6000 5000 4000 3000 2000 1000 0 10

VDS = 0 V VGS = 0 V

TJ = 25C

10000

TJ = 25C

Ciss

VGS = 0 V

2000 C, CAPACITANCE (pF) 1000

Ciss

200 100

Coss Crss

Coss Crss 5 VGS 0 VDS 5 10 15 20 25 20 10 1 2

20 10 100 200 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

1000

GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)

Figure 7a. Low Voltage Capacitance Variation

Figure 7b. High Voltage Capacitance Variation

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MTW14N50E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS) 15 12 9 6 3 0 Q3 20 Q1 Q2 VGS VDS TJ = 25C ID = 14 A VDS = 400 V 500 400 300 200 100 0 100 10000 TJ = 25C ID = 14 A VDD = 250 V VGS = 10 V td(off) VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

QT

2000 1000

td(on) 200 100 tr tf 1 2 10 20 100 200 1000

20 10

10

30

40

50

60

70

80

90

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource Voltage versus Total Charge

Figure 9. Resistive Switching Time Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

14 I S , SOURCE CURRENT (AMPS) 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) 1 TJ = 25C VGS = 0 V dIS/dt = 100 A/s

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, Transient Thermal ResistanceGeneral Data and Its Use. Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded and the transition time (tr,tf) do not exceed 10s. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A Power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of draintosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 12). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.

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MTW14N50E
SAFE OPERATING AREA
100 I D , DRAIN CURRENT (AMPS) 900 800 700 600 500 400 300 200 100 0 25 50 75 100 125 TJ, STARTING JUNCTION TEMPERATURE (C) 150 PEAK ID = 14 A VDD = 50 V

10s 100s 1ms

20 10

2 1 THERMAL LIMIT PACKAGE LIMIT RDS(on) LIMIT 1 2 20 10 100 200 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

10ms

0.2 0.1

dc 1000

E AS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ)

VGS = 20 V SINGLE PULSE TC = 25C

Figure 11. Maximum Rated Forward Biased Safe Operating Area

Figure 12. Maximum Avalanche Energy versus Starting Junction Temperature

1 r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE

D = 0.5 = 0.2 = 0.1 = 0.05 = 0.02 = 0.01 SINGLE PULSE RJC(t) = r(t) RJC RJC = 0.7C/W MAX D CURVES APPLY FOR POWER PULSE TRAIN SHOWN READ TIME AT t1 TJ(pk) - TC = P(pk) RJC(t) 0.1 0.2 1 2 t, TIME (ms) 10 20

0.2 0.1

0.02 0.01

DUTY CYCLE, D = t1/t2 P(pk) t1 t2 200 1000

0.002 0.001 0.01 0.02

100

Figure 13. Thermal Response

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MTW14N50E
PACKAGE DIMENSIONS
TO247 CASE 340K01 ISSUE C

0.25 (0.010)

Q T B M U A
1

T E B L R
2 3 DIM A B C D E F G H J K L P Q R U V

NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. MILLIMETERS MIN MAX 19.7 20.3 15.3 15.9 4.7 5.3 1.0 1.4 1.27 REF 2.0 2.4 5.5 BSC 2.2 2.6 0.4 0.8 14.2 14.8 5.5 NOM 3.7 4.3 3.55 3.65 5.0 NOM 5.5 BSC 3.0 3.4 INCHES MIN MAX 0.776 0.799 0.602 0.626 0.185 0.209 0.039 0.055 0.050 REF 0.079 0.094 0.216 BSC 0.087 0.102 0.016 0.031 0.559 0.583 0.217 NOM 0.146 0.169 0.140 0.144 0.197 NOM 0.217 BSC 0.118 0.134

V F D 0.25 (0.010)
M

H J

Y Q

STYLE 1: PIN 1. 2. 3. 4.

GATE DRAIN SOURCE DRAIN

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MTW14N50E

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

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MTW14N50E/D