FPGA HOW-TO GUIDE

Interfacing SPI-DAC with Spartan-3an FPGA

Contents at a Glance
12 Bit SPI DAC ..................................................................3 Interfacing SPI DAC with Spartan-3an FPGA .....................3 Pin Assignment with Spartan-3an FPGA ...........................3 Circuit Diagram to Interface SPI DAC with Spartan-3an.....4 VHDL Program for DAC using Spartan-3an FPGA...............5

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12 Bit SPI DAC These DAC (Digital to Analog Converter) are SPI Bus based which is a serial bus. So the number of pins in IC is very low. Interfacing SPI DAC with Spartan-3an FPGA The Spartan-3an board has 2-channel 12 Bit SPI DAC, indicated as in Figure. The controller designed to covert the digital data into analog, where the digital data is transferred using SPI Controller and DAC (MCP4921) converts the serial data into the analog. SPI Controller controls the speed, data transmission, DAC selection etc. Based on the inputs from the SPI line, DAC (MCP4921) coverts the 12 bit data to analog. Pin Assignment with Spartan-3an FPGA
DAC PIN CS SCK SDI SPARTAN3AN FPGA Lines P58 P59 P60

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Circuit Diagram to Interface SPI DAC with Spartan-3an

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VHDL Program for DAC using Spartan-3an FPGA

*************************************************************************************** Title : Program for UART to LED Display ***************************************************************************************

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity dac is port( clk cs sck end dac; architecture Behavioral of dac is : in std_logic; : out std_logic; : out std_logic; sdi : out std_logic);

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signal data : std_logic_vector(0 to 15) := "0100111111110001"; begin process(clk) variable i,k:integer:=0; begin if rising_edge(clk) then i:=i+1; if i<65 then cs<='0'; else cs<='1'; end if; if i<3 then sck<='0'; sdi<=data(k); elsif i<5 then sck<='1'; sdi<=data(k); k:=k+1; elsif i<7 then sck<='0'; sdi<=data(k);

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elsif i<9 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<11 then sck<='0'; sdi<=data(k); elsif i<13 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<15 then sck<='0'; sdi<=data(k); elsif i<17 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<19 then sck<='0'; sdi<=data(k);

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elsif i<21 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<23 then sck<='0'; sdi<=data(k); elsif i<25 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<27 then sck<='0'; sdi<=data(k); elsif i<29 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<31 then sck<='0';

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sdi<=data(k); elsif i<33 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<35 then sck<='0'; sdi<=data(k); elsif i<37 then sck<='1'; sdi<=data(k); K:=k+1;

elsif i<39 then sck<='0'; sdi<=data(k); elsif i<41 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<43 then

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sck<='0'; sdi<=data(k); elsif i<45 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<47 then sck<='0'; sdi<=data(k); elsif i<49 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<51 then sck<='0'; sdi<=data(k); elsif i<53 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<55 then

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sck<='0'; sdi<=data(k); elsif i<57 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<59 then sck<='0'; sdi<=data(k); elsif i<61 then sck<='1'; sdi<=data(k); K:=k+1; elsif i<63 then sck<='0'; sdi<=data(k); elsif i<65 then sck<='1'; sdi<=data(k); K:=k+1; end if;

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end if; end process; end Behavioral;

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